diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig index 197c126363..b0385a9d3c 100644 --- a/arch/arm/src/lpc43xx/Kconfig +++ b/arch/arm/src/lpc43xx/Kconfig @@ -67,7 +67,7 @@ config ARCH_CHIP_LPC4357FET256 config ARCH_CHIP_LPC4370FET100 bool "LPC4370FET100" -endchoice +endchoice # LPC43XX Chip Selection config ARCH_FAMILY_LPC4310 bool @@ -143,7 +143,7 @@ config LPC43_BOOT_CS2FLASH config LPC43_BOOT_CS3FLASH bool "Running in external FLASH CS3" -endchoice +endchoice # LPC43XX Boot Configuration menu "LPC43xx Peripheral Support" @@ -179,6 +179,138 @@ config LPC43_ETHERNET bool "Ethernet" default n +config LPC43_EVNTMNTR + bool "Event Monitor" + default n + +config LPC43_GPDMA + bool "GPDMA" + default n + +config LPC43_I2C0 + bool "I2C0" + default n + +config LPC43_I2C1 + bool "I2C1" + default n + +config LPC43_I2S0 + bool "I2S0" + default n + +config LPC43_I2S1 + bool "I2S1" + default n + +config LPC43_LCD + bool "LCD" + default n + +config LPC43_MCPWM + bool "Motor Control PWM (MCPWM)" + default n + +config LPC43_QEI + bool "Quadrature Controller Interface (QEI)" + default n + +config LPC43_RIT + bool "Repetitive Interrupt Timer (RIT)" + default n + +config LPC43_RIT_RES + int "Interrupt schedule resolution (nS)" + default 250 + depends on LPC43_RIT + +config LPC43_RTC + bool "Real Time Clock (RTC)" + default n + +config LPC43_SCT + bool "State Configurable Timer (SCT)" + default n + +config LPC43_SDMMC + bool "SD/MMC" + default n + +config LPC43_SPI + bool "SPI" + default n + +config LPC43_SPIFI + bool "SPI Flash Interface (SPIFI)" + default n + +config LPC43_SSP0 + bool "SSP0" + default n + +config LPC43_SSP1 + bool "SSP1" + default n + +config LPC43_TMR0 + bool "ADC1" + default n + +config LPC43_TMR1 + bool "Timer 1" + default n + +config LPC43_TMR2 + bool "Timer 2" + default n + +config LPC43_TMR3 + bool "Timer 3" + default n + +config LPC43_USART0 + bool "USART0" + default n + select ARCH_HAVE_USART0 + select ARCH_HAVE_SERIAL_TERMIOS + +config LPC43_UART1 + bool "UART1" + default n + select ARCH_HAVE_UART1 + select ARCH_HAVE_SERIAL_TERMIOS + +config LPC43_USART2 + bool "USART2" + default n + select ARCH_HAVE_USART2 + select ARCH_HAVE_SERIAL_TERMIOS + +config LPC43_USART3 + bool "USART3" + default n + select ARCH_HAVE_USART3 + select ARCH_HAVE_SERIAL_TERMIOS + +config LPC43_USBOTG + bool "USB EHCI" + default n + select USBHOST_HAVE_ASYNCH + +config LPC43_USB0 + bool "USB0" + default n + +config LPC43_USB1 + bool "USB1" + default n + +config LPC43_WWDT + bool "Windowing Watchdog Timer (WWDT)" + default n + +endmenu # LPC43xx Peripheral Support + if LPC43_ETHERNET menu "Ethernet MAC configuration" @@ -313,7 +445,6 @@ config LPC43_RMII bool default y if !LPC43_MII - config LPC43_ETHERNET_REGDEBUG bool "Register-Level Debug" default n @@ -321,131 +452,121 @@ config LPC43_ETHERNET_REGDEBUG ---help--- Enable very low-level register access debug. Depends on DEBUG. -endmenu -endif +endmenu # Ethernet MAC configuration +endif # LPC43_ETHERNET -config LPC43_EVNTMNTR - bool "Event Monitor" - default n +menu "RS-485 Configuration" +if LPC43_USART0 -config LPC43_GPDMA - bool "GPDMA" +config USART0_RS485MODE + bool "RS-485 on USART0" default n + ---help--- + Enable RS-485 interface on USART0. -config LPC43_I2C0 - bool "I2C0" +config USART0_RS485_DTRDIR + bool "USART0 DTR for DIR" default n + ---help--- + Use the USART DTR pin for the DIR pin + +endif # LPC43_USART0 + +if LPC43_UART1 + +config UART1_RS485MODE + bool "RS-485 on UART1" + default n + ---help--- + Enable RS-485 interface on USRT1. + +config UART1_RS485_DTRDIR + bool "UART1 DTR for DIR" + default n + ---help--- + Use the UART DTR pin for the DIR pin + +endif # LPC43_USART0 + +if LPC43_USART2 + +config USART2_RS485MODE + bool "RS-485 on USART2" + default n + ---help--- + Enable RS-485 interface on USART2. + +config USART2_RS485_DTRDIR + bool "USART2 DTR for DIR" + default n + ---help--- + Use the USART DTR pin for the DIR pin + +endif # LPC43_USART2 + +if LPC43_USART3 + +config USART3_RS485MODE + bool "RS-485 on USART3" + default n + ---help--- + Enable RS-485 interface on USART3. + +config USART3_RS485_DTRDIR + bool "USART3 DTR for DIR" + default n + ---help--- + Use the USART DTR pin for the DIR pin + +endif # LPC43_USART3 +endmenu # RS-485 Configuration + +if LPC43_I2C0 +menu "I2C Configution" config LPC43_I2C0_SUPERFAST bool "I2C0 super fast mode" default n depends on LPC43_I2C0 -config LPC43_I2C1 - bool "I2C1" - default n +endmenu # I2C Configution +endif # LPC43_I2C0 -config LPC43_I2S0 - bool "I2S0" - default n +if LPC43_USBOTG && USBHOST +menu "USB host controller driver (HCD) options" -config LPC43_I2S1 - bool "I2S1" - default n +config LPC43_EHCI_NQHS + int "Number of Queue Head (QH) structures" + default 4 + ---help--- + Configurable number of Queue Head (QH) structures. The default is + one per Root hub port plus one for EP0 (4). -config LPC43_LCD - bool "LCD" - default n +config LPC43_EHCI_NQTDS + int "Number of Queue Element Transfer Descriptor (qTDs)" + default 6 + ---help--- + Configurable number of Queue Element Transfer Descriptor (qTDs). + The default is one per root hub plus three from EP0 (6). -config LPC43_MCPWM - bool "Motor Control PWM (MCPWM)" - default n +config LPC43_EHCI_BUFSIZE + int "Size of one request/descriptor buffer" + default 128 + ---help--- + The size of one request/descriptor buffer in bytes. The TD buffe + size must be an even number of 32-bit words and must be large enough + to hangle the largest transfer via a SETUP request. -config LPC43_QEI - bool "Quadrature Controller Interface (QEI)" - default n +config LPC43_EHCI_PREALLOCATE + bool "Preallocate descriptor pool" + default y + ---help--- + Select this option to pre-allocate EHCI queue and descriptor + structure pools in .bss. Otherwise, these pools will be + dynamically allocated using kmm_memalign(). -config LPC43_RIT - bool "Repetitive Interrupt Timer (RIT)" - default n - -config LPC43_RIT_RES - int "Interrupt schedule resolution (nS)" - default 250 - depends on LPC43_RIT - -config LPC43_RTC - bool "Real Time Clock (RTC)" - default n - -config LPC43_SCT - bool "State Configurable Timer (SCT)" - default n - -config LPC43_SDMMC - bool "SD/MMC" - default n - -config LPC43_SPI - bool "SPI" - default n - -config LPC43_SPIFI - bool "SPI Flash Interface (SPIFI)" - default n - -config LPC43_SSP0 - bool "SSP0" - default n - -config LPC43_SSP1 - bool "SSP1" - default n - -config LPC43_TMR0 - bool "ADC1" - default n - -config LPC43_TMR1 - bool "Timer 1" - default n - -config LPC43_TMR2 - bool "Timer 2" - default n - -config LPC43_TMR3 - bool "Timer 3" - default n - -config LPC43_USART0 - bool "USART0" - default n - select ARCH_HAVE_USART0 - select ARCH_HAVE_SERIAL_TERMIOS - -config LPC43_UART1 - bool "UART1" - default n - select ARCH_HAVE_UART1 - select ARCH_HAVE_SERIAL_TERMIOS - -config LPC43_USART2 - bool "USART2" - default n - select ARCH_HAVE_USART2 - select ARCH_HAVE_SERIAL_TERMIOS - -config LPC43_USART3 - bool "USART3" - default n - select ARCH_HAVE_USART3 - select ARCH_HAVE_SERIAL_TERMIOS - -config LPC43_USBOTG - bool "USB EHCI" - default n - select USBHOST_HAVE_ASYNCH +endmenu # USB host controller driver (HCD) options +endif # LPC43_USBOTG && USBHOST if LPC43_USBOTG && USBHOST @@ -484,31 +605,24 @@ config LPC43_EHCI_PREALLOCATE endmenu # USB host controller driver (HCD) options endif # LPC43_USBOTG && USBHOST -config LPC43_USB0 - bool "USB0" - default n +if LPC43_USB0 || LPC43_USB1 + +menu "USB device controller driver (DCD) options" config LPC43_USB0DEV_NOVBUS bool "No USB0 VBUS sensing" default n depends on LPC43_USB0 && USBDEV -config LPC43_USB1 - bool "USB1" +config LPC43_USB1_ULPI + bool "USB1 with ULPI" default n + depends on LPC43_USB1 config LPC43_USB1DEV_NOVBUS bool "No USB1 VBUS sensing" default n depends on LPC43_USB1 && USBDEV -config LPC43_USB1_ULPI - bool "USB1 with ULPI" - default n - depends on LPC43_USB1 - -config LPC43_WWDT - bool "Windowing Watchdog Timer (WWDT)" - default n - -endmenu +endmenu # USB device controller driver (DCD) options +endif # LPC43_USB0 || LPC43_USB1 diff --git a/arch/arm/src/lpc43xx/lpc43_config.h b/arch/arm/src/lpc43xx/lpc43_config.h index 1e7c5c84a3..8a4509b8f0 100644 --- a/arch/arm/src/lpc43xx/lpc43_config.h +++ b/arch/arm/src/lpc43xx/lpc43_config.h @@ -73,20 +73,25 @@ #ifndef CONFIG_LPC43_USART0 # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART0_RS485MODE +# undef CONFIG_USART0_RS485_DTRDIR #endif #ifndef CONFIG_LPC43_UART1 # undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART1_RS485MODE +# undef CONFIG_UART1_RS485_DTRDIR #endif #ifndef CONFIG_LPC43_USART2 # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART2_RS485MODE +# undef CONFIG_USART2_RS485_DTRDIR #endif #ifndef CONFIG_LPC43_USART3 # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART3_RS485MODE +# undef CONFIG_USART3_RS485_DTRDIR #endif /* Is there a serial console? There should be at most one defined. It could be on diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index 5ac9d0c158..9d51f9a405 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc43xx/lpc43_serial.c * - * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -91,6 +91,9 @@ struct up_dev_s uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (7 or 8) */ bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +#ifdef HAVE_RS485 + bool dtrdir; /* DTR pin is the direction bit */ +#endif }; /**************************************************************************** @@ -166,6 +169,9 @@ static struct up_dev_s g_uart0priv = .parity = CONFIG_USART0_PARITY, .bits = CONFIG_USART0_BITS, .stopbits2 = CONFIG_USART0_2STOP, +#if defined(CONFIG_USART0_RS485MODE) && defined(CONFIG_USART0_RS485_DTRDIR) + .dtrdir = true; +#endif }; static uart_dev_t g_uart0port = @@ -198,6 +204,9 @@ static struct up_dev_s g_uart1priv = .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, .stopbits2 = CONFIG_UART1_2STOP, +#if defined(CONFIG_UART1_RS485MODE) && defined(CONFIG_UART1_RS485_DTRDIR) + .dtrdir = true; +#endif }; static uart_dev_t g_uart1port = @@ -230,6 +239,9 @@ static struct up_dev_s g_uart2priv = .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, +#if defined(CONFIG_USART2_RS485MODE) && defined(CONFIG_USART2_RS485_DTRDIR) + .dtrdir = true; +#endif }; static uart_dev_t g_uart2port = @@ -262,6 +274,9 @@ static struct up_dev_s g_uart3priv = .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, +#if defined(CONFIG_USART3_RS485MODE) && defined(CONFIG_USART3_RS485_DTRDIR) + .dtrdir = true; +#endif }; static uart_dev_t g_uart3port = @@ -939,7 +954,8 @@ static inline int up_set_rs485_mode(struct up_dev_s *priv, * RXDIS 0 = Receiver is not disabled * AADEN 0 = Auto Address Detect (ADD) is disabled * DCTRL 1 = Auto Direction Control is enabled - * OINV ? = Value control by user mode settings + * OINV ? = Value controlle by user mode settings + * SEL ? = Value controlled by user mode settings */ regval = UART_RS485CTRL_DCTRL; @@ -957,6 +973,17 @@ static inline int up_set_rs485_mode(struct up_dev_s *priv, regval |= UART_RS485CTRL_OINV; } +#ifdef BOARD_LPC43_UART1_DTRDIR + if (priv->dtrdir) + { + /* If we ar using DTR for direction then ensure the H/W is + * configured correctly. + */ + + regval |= UART_RS485CTRL_SEL; + } +#endif + up_serialout(priv, LPC43_UART_RS485CTRL_OFFSET, regval); /* We only have control of the delay after send. Time provided