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Fix clang compiler warning in boards/arm/stm32/

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Error: board/stm32_ssd1289.c:290:33: error: shifting a negative signed value is undefined [-Werror,-Wshift-negative-value]
  putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) |
  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~
/github/workspace/sources/nuttx/arch/arm/src/chip/hardware/stm32_fsmc.h:164:42: note: expanded from macro 'FSMC_BTR_ADDHLD'
                                         ^
/github/workspace/sources/nuttx/arch/arm/src/common/arm_internal.h:135:54: note: expanded from macro 'putreg32'
                                                     ^
Error: board/stm32_ssd1289.c:291:33: error: shifting a negative signed value is undefined [-Werror,-Wshift-negative-value]
           FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) |
           ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~
/github/workspace/sources/nuttx/arch/arm/src/chip/hardware/stm32_fsmc.h:172:42: note: expanded from macro 'FSMC_BTR_BUSTURN'
                                         ^
/github/workspace/sources/nuttx/arch/arm/src/common/arm_internal.h:135:54: note: expanded from macro 'putreg32'
                                                     ^
Error: board/stm32_ssd1289.c:292:12: error: shifting a negative signed value is undefined [-Werror,-Wshift-negative-value]
           FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) |
           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/github/workspace/sources/nuttx/arch/arm/src/chip/hardware/stm32_fsmc.h:176:42: note: expanded from macro 'FSMC_BTR_CLKDIV'
                                         ^
/github/workspace/sources/nuttx/arch/arm/src/common/arm_internal.h:135:54: note: expanded from macro 'putreg32'
                                                     ^
Error: board/stm32_ssd1289.c:292:33: error: shifting a negative signed value is undefined [-Werror,-Wshift-negative-value]
           FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) |
           ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~
/github/workspace/sources/nuttx/arch/arm/src/chip/hardware/stm32_fsmc.h:180:42: note: expanded from macro 'FSMC_BTR_DATLAT'
                                         ^
/github/workspace/sources/nuttx/arch/arm/src/common/arm_internal.h:135:54: note: expanded from macro 'putreg32'
                                                     ^

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2022-10-30 01:26:11 +08:00 committed by Petro Karashchenko
parent 2d6503646d
commit e9f630ecb5
8 changed files with 14 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c
View File

@ -165,7 +165,7 @@ void stm32_selectlcd(void)
putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(0) | putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(0) |
FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(0) | FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(0) |
FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); FSMC_BTR_ACCMODA, STM32_FSMC_BTR1);
putreg32(0xffffffff, STM32_FSMC_BWTR4); putreg32(0xffffffff, STM32_FSMC_BWTR4);

2
boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c
View File

@ -296,7 +296,7 @@ static void stm32_selectlcd(void)
/* Bank1 NOR/SRAM timing register configuration */ /* Bank1 NOR/SRAM timing register configuration */
putreg32(FSMC_BTR_ADDSET(2) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(2) | putreg32(FSMC_BTR_ADDSET(2) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(2) |
FSMC_BTR_BUSTURN(0) | FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_BUSTURN(0) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
FSMC_BTR_ACCMODA, FSMC_BTR_ACCMODA,
STM32_FSMC_BTR1); STM32_FSMC_BTR1);

2
boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c
View File

@ -375,7 +375,7 @@ static void stm32_selectlcd(void)
/* Bank1 NOR/SRAM timing register configuration */ /* Bank1 NOR/SRAM timing register configuration */
putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(2) | putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(2) |
FSMC_BTR_BUSTURN(0) | FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_BUSTURN(0) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
FSMC_BTR_ACCMODA, FSMC_BTR_ACCMODA,
STM32_FSMC_BTR1); STM32_FSMC_BTR1);

2
boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c
View File

@ -117,7 +117,7 @@ void stm32_selectlcd(void)
putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(0) | putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(0) |
FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(0) | FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(0) |
FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
FSMC_BTR_ACCMODA, STM32_FSMC_BTR4); FSMC_BTR_ACCMODA, STM32_FSMC_BTR4);
putreg32(0xffffffff, STM32_FSMC_BWTR4); putreg32(0xffffffff, STM32_FSMC_BWTR4);

6
boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c
View File

@ -136,9 +136,9 @@ void stm32_selectlcd(void)
/* Bank3 NOR/SRAM timing register configuration */ /* Bank3 NOR/SRAM timing register configuration */
putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(1) |
FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(1) |
FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); FSMC_BTR_ACCMODA, STM32_FSMC_BTR3);
putreg32(0xffffffff, STM32_FSMC_BWTR3); putreg32(0xffffffff, STM32_FSMC_BWTR3);

6
boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c
View File

@ -136,9 +136,9 @@ void stm32_selectlcd(void)
/* Bank3 NOR/SRAM timing register configuration */ /* Bank3 NOR/SRAM timing register configuration */
putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(1) |
FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(1) |
FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); FSMC_BTR_ACCMODA, STM32_FSMC_BTR3);
putreg32(0xffffffff, STM32_FSMC_BWTR3); putreg32(0xffffffff, STM32_FSMC_BWTR3);

6
boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c
View File

@ -287,9 +287,9 @@ void stm32_selectlcd(void)
/* Bank1 NOR/SRAM timing register configuration */ /* Bank1 NOR/SRAM timing register configuration */
putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(1) |
FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(1) |
FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); FSMC_BTR_ACCMODA, STM32_FSMC_BTR1);
putreg32(0xffffffff, STM32_FSMC_BWTR1); putreg32(0xffffffff, STM32_FSMC_BWTR1);

2
boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c
View File

@ -445,7 +445,7 @@ static void stm32_selectlcd(void)
putreg32( putreg32(
FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(0) |
FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(0) | FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(0) |
FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
FSMC_BTR_ACCMODA, FSMC_BTR_ACCMODA,
STM32_FSMC_BTR1); STM32_FSMC_BTR1);