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Merged in raiden00/nuttx (pull request #469)

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* stm32f0/Kconfig: remove references to HRTIM

* STM32F33: missing SYSCFG CFGR3 definitions

* stm32_hrtim.h: remove redundant definitions

* stm32_hrtim.c: fix DAC triggers configuration

* stm32_hritm.c: warning message when default value selected

* stm32_hrtim.c: missing master timer logic

* stm32_hrtim.c: add more assertions

* stm32_dac.c: fix conditional

* stm32_dac.c: conditional logic for timer triggering

* stm32_dac.c: fix TSEL configuration when HRTIM

* stm32_dac.c: unnecessary condition

* stm32_dac.c: DMA request remapping

* stm32_dac.c: fix commpilation errors

* stm32_dac.c: add DMA buffers initialization logic

* stm32_hrtim.c: enable DAC triggering

* analog/comp.c: fix compilation errors when poll disabled

* stm32_hrtim.c: remove doubled assertions

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Mateusz Szafoni 2017-08-27 12:49:53 +00:00 committed by Gregory Nutt
parent 7858ed834b
commit ea35f31f73
7 changed files with 327 additions and 115 deletions
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36
arch/arm/src/stm32/chip/stm32f33xxx_syscfg.h
View File

@ -92,10 +92,10 @@
#define SYSCFG_CFGR1_TIM16_DMARMP (1 << 11) /* Bit 11: TIM16 DMA request remapping bit */
#define SYSCFG_CFGR1_TIM17_DMARMP (1 << 12) /* Bit 12: TIM17 DMA request remapping bit */
#define SYSCFG_CFGR1_TIM6_DMARMP (1 << 13) /* Bit 13: TIM6 DMA remap, or */
#define SYSCFG_CFGR1_DAC1_DMARMP (1 << 13) /* Bit 13: DAC channel DMA remap */
#define SYSCFG_CFGR1_DAC1CH1_DMARMP (1 << 13) /* Bit 13: DAC1 channel1 DMA remap */
#define SYSCFG_CFGR1_TIM7_DMARMP (1 << 14) /* Bit 14: TIM7 DMA remap */
#define SYSCFG_CFGR1_DAC2CH2_DMARMP (1 << 14) /* Bit 14: DAC channel2 DMA remap */
#define SYSCFG_CFGR1_DAC2CH1_DMARMP (1 << 15) /* Bit 14: DAC channel1 DMA remap */
#define SYSCFG_CFGR1_DAC1CH2_DMARMP (1 << 14) /* Bit 14: DAC1 channel2 DMA remap */
#define SYSCFG_CFGR1_DAC2CH1_DMARMP (1 << 15) /* Bit 15: DAC2 channel1 DMA remap */
#define SYSCFG_CFGR1_I2C_PBXFMP_SHIFT (16) /* Bits 16-19: Fast Mode Plus (FM+) driving capability */
#define SYSCFG_CFGR1_I2C_PBXFMP_MASK (15 << SYSCFG_CFGR1_I2C_PBXFMP_SHIFT)
#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 fast mode Plus driving capability */
@ -176,7 +176,35 @@
#define SYSCFG_CFGR2_SRAM_PEF (1 << 8) /* Bit 8: SRAM parity error */
/* SYSCFG configuration register 3 */
/* TODO */
#define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_SHIFT (0) /* Bits 0-1: SPI1_RX_DMA remap */
#define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_MASK (3 << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_SHIFT)
# define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 (0 << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_SHIFT) /* 00: SPI1_RX mapped on DMA1CH2 */
# define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 (1 << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_SHIFT) /* 01: SPI1_RX mapped on DMA1CH2 */
# define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_2 (2 << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_SHIFT) /* 10: SPI1_RX mapped on DMA1CH6 */
# define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_3 (3 << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_SHIFT) /* 11: SPI1_RX mapped on DMA1CH2 */
#define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_SHIFT (2) /* Bits 2-3: SPI1_TX_DMA remap */
#define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_MASK (3 << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_SHIFT)
# define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 (0 << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_SHIFT) /* 00: SPI1_TX mapped on DMA1CH3 */
# define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 (1 << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_SHIFT) /* 01: SPI1_TX mapped on DMA1CH5 */
# define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_2 (2 << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_SHIFT) /* 10: SPI1_TX mapped on DMA1CH7 */
# define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_3 (3 << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_SHIFT) /* 11: SPI1_TX mapped on DMA1CH3 */
#define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_SHIFT (4) /* Bits 4-5: I2C1_RX_DMA remap */
#define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_MASK (3 << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_SHIFT)
# define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 (0 << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_SHIFT) /* 00: I2C1_RX mapped on DMA1CH7 */
# define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 (1 << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_SHIFT) /* 01: I2C1_RX mapped on DMA1CH3 */
# define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_2 (2 << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_SHIFT) /* 10: I2C1_RX mapped on DMA1CH5 */
# define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_3 (3 << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_SHIFT) /* 11: I2C1_RX mapped on DMA1CH7 */
#define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_SHIFT (6) /* Bits 6-7: I2C1_TX_DMA remap */
#define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_MASK (3 << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_SHIFT)
# define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 (0 << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_SHIFT) /* 00: I2C1_TX mapped on DMA1CH6 */
# define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 (1 << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_SHIFT) /* 01: I2C1_TX mapped on DMA1CH2 */
# define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_2 (2 << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_SHIFT) /* 10: I2C1_TX mapped on DMA1CH4 */
# define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_3 (3 << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_SHIFT) /* 11: I2C1_TX mapped on DMA1CH6 */
#define SYSCFG_CFGR3_ADC2_DMA_RMP (8) /* Bits 8: ADC2 mapped on DMA1CH1 remap */
#define SYSCFG_CFGR3_DAC1_TRIG3_RMP (1 << 16) /* Bit 16: HRTIM1_DAC1_TRIG1 remap */
#define SYSCFG_CFGR3_DAC1_TRIG3_RMP (1 << 16) /* Bit 16: HRTIM1_DAC1_TRIG1 remap */
#define SYSCFG_CFGR3_DAC1_TRIG5_RMP (1 << 17) /* Bit 17: HRTIM1_DAC1_TRIG2 remap */
#endif /* CONFIG_STM32_STM32F33XX */
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_SYSCFG_H */

205
arch/arm/src/stm32/stm32_dac.c
View File

@ -43,6 +43,7 @@
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include <math.h>
#include <semaphore.h>
#include <errno.h>
@ -60,6 +61,7 @@
#include "stm32_dac.h"
#include "stm32_rcc.h"
#include "stm32_dma.h"
#include "stm32_syscfg.h"
#ifdef CONFIG_DAC
@ -331,6 +333,12 @@
# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_SW
#endif
#if defined(NEED_TIM2) || defined(NEED_TIM3) || defined(NEED_TIM4) || \
defined(NEED_TIM5) || defined(NEED_TIM6) || defined(NEED_TIM7) || \
defined(NEED_TIM8)
# define HAVE_TIMER
#endif
#ifdef CONFIG_STM32_DAC1CH2_DMA
# if defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG1)
# ifndef CONFIG_STM32_HRTIM_DAC
@ -467,20 +475,20 @@
#define TIM_INDEX_HRTIM 255
#if defined(DAC1_HRTIM) || defined(DAC2_HRTIM) || defined(DAC3_HRTIM)
#if defined(DAC1CH1_HRTIM) || defined(DAC1CH2_HRTIM) || defined(DAC2CH1_HRTIM)
# define HAVE_HRTIM
#endif
/* DMA buffers default size */
#ifndef CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE
# define CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE 256
# error "DAC1CH1 buffer size must be provided"
#endif
#ifndef CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE
# define CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE 256
# error "DAC1CH2 buffer size must be provided"
#endif
#ifndef CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE
# define CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE 256
# error "DAC2CH1 buffer size must be provided"
#endif
/* Calculate timer divider values based upon DACn_TIMER_PCLK_FREQUENCY and
@ -534,8 +542,10 @@ struct stm32_chan_s
uint16_t dmachan; /* DMA channel needed by this DAC */
uint16_t buffer_len; /* DMA buffer length */
DMA_HANDLE dma; /* Allocated DMA channel */
# ifdef HAVE_TIMER
uint32_t tbase; /* Timer base address */
uint32_t tfrequency; /* Timer frequency */
# endif
uint16_t *dmabuffer; /* DMA transfer buffer */
#endif
};
@ -545,10 +555,12 @@ struct stm32_chan_s
****************************************************************************/
/* DAC Register access */
#ifdef HAVE_DMA
#ifdef HAVE_TIMER
static uint32_t tim_getreg(FAR struct stm32_chan_s *chan, int offset);
static void tim_putreg(FAR struct stm32_chan_s *chan, int offset,
uint32_t value);
static void tim_modifyreg(FAR struct stm32_chan_s *chan, int offset,
uint32_t clearbits, uint32_t setbits);
#endif
/* Interrupt handler */
@ -569,7 +581,12 @@ static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg);
/* Initialization */
#ifdef HAVE_DMA
# ifdef HAVE_TIMER
static int dac_timinit(FAR struct stm32_chan_s *chan);
# endif
static int dma_remap(FAR struct stm32_chan_s *chan);
static void dma_bufferinit(FAR struct stm32_chan_s *chan, uint16_t* buffer,
uint16_t len);
#endif
static int dac_chaninit(FAR struct stm32_chan_s *chan);
static int dac_blockinit(void);
@ -613,14 +630,11 @@ static struct stm32_chan_s g_dac1ch1priv =
.dmachan = DAC1CH1_DMA_CHAN,
.buffer_len = CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE,
.dmabuffer = dac1ch1_buffer,
.tsel = DAC1CH1_TSEL_VALUE,
# ifdef DAC1CH1_HRTIM
.timer = TIM_INDEX_HRTIM,
.tsel = 0,
.tbase = 0,
.tfrequency = 0,
# else
.timer = CONFIG_STM32_DAC1CH1_TIMER,
.tsel = DAC1CH1_TSEL_VALUE,
.tbase = DAC1CH1_TIMER_BASE,
.tfrequency = CONFIG_STM32_DAC1CH1_TIMER_FREQUENCY,
# endif
@ -634,7 +648,6 @@ static struct dac_dev_s g_dac1ch1dev =
};
#endif /* CONFIG_STM32_DAC1CH1 */
#if STM32_NDAC > 1
#ifdef CONFIG_STM32_DAC1CH2
/* Channel 2: DAC1 channel 2 */
@ -653,14 +666,11 @@ static struct stm32_chan_s g_dac1ch2priv =
.dmachan = DAC1CH2_DMA_CHAN,
.buffer_len = CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE,
.dmabuffer = dac1ch2_buffer,
.tsel = DAC1CH2_TSEL_VALUE,
# ifdef DAC1CH2_HRTIM
.timer = TIM_INDEX_HRTIM,
.tsel = 0,
.tbase = 0,
.tfrequency = 0,
# else
.timer = CONFIG_STM32_DAC1CH2_TIMER,
.tsel = DAC1CH2_TSEL_VALUE,
.tbase = DAC1CH2_TIMER_BASE,
.tfrequency = CONFIG_STM32_DAC1CH2_TIMER_FREQUENCY,
# endif
@ -673,7 +683,6 @@ static struct dac_dev_s g_dac1ch2dev =
.ad_priv = &g_dac1ch2priv,
};
#endif /* CONFIG_STM32_DAC1CH2 */
#endif /* STM32_NDAC > 1 */
#endif /* CONFIG_STM32_DAC1 */
@ -696,14 +705,11 @@ static struct stm32_chan_s g_dac2ch1priv =
.dmachan = DAC2CH1_DMA_CHAN,
.buffer_len = CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE,
.dmabuffer = dac2ch1_buffer,
.tsel = DAC2CH1_TSEL_VALUE,
# ifdef DAC2CH1_HRTIM
.timer = TIM_INDEX_HRTIM,
.tsel = 0,
.tbase = 0,
.tfrequency = 0,
# else
.timer = CONFIG_STM32_DAC2CH1_TIMER,
.tsel = DAC2CH1_TSEL_VALUE,
.tbase = DAC2CH1_TIMER_BASE,
.tfrequency = CONFIG_STM32_DAC2CH1_TIMER_FREQUENCY,
# endif
@ -758,6 +764,8 @@ static inline void stm32_dac_modify_cr(FAR struct stm32_chan_s *chan,
modifyreg32(chan->cr, clearbits << shift, setbits << shift);
}
#ifdef HAVE_TIMER
/****************************************************************************
* Name: tim_getreg
*
@ -773,12 +781,10 @@ static inline void stm32_dac_modify_cr(FAR struct stm32_chan_s *chan,
*
****************************************************************************/
#ifdef HAVE_DMA
static uint32_t tim_getreg(FAR struct stm32_chan_s *chan, int offset)
{
return getreg32(chan->tbase + offset);
}
#endif
/****************************************************************************
* Name: tim_putreg
@ -795,13 +801,11 @@ static uint32_t tim_getreg(FAR struct stm32_chan_s *chan, int offset)
*
****************************************************************************/
#ifdef HAVE_DMA
static void tim_putreg(FAR struct stm32_chan_s *chan, int offset,
uint32_t value)
{
putreg32(value, chan->tbase + offset);
}
#endif
/****************************************************************************
* Name: tim_modifyreg
@ -820,13 +824,12 @@ static void tim_putreg(FAR struct stm32_chan_s *chan, int offset,
*
****************************************************************************/
#ifdef HAVE_DMA
static void tim_modifyreg(FAR struct stm32_chan_s *chan, int offset,
uint32_t clearbits, uint32_t setbits)
{
modifyreg32(chan->tbase + offset, clearbits, setbits);
}
#endif
#endif /* HAVE_TIMER */
/****************************************************************************
* Name: dac_interrupt
@ -1019,7 +1022,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
/* Reset counters (generate an update). Only when timer is not HRTIM */
#ifdef HAVE_DMA
#ifdef HAVE_TIMER
if (chan->timer != TIM_INDEX_HRTIM)
{
tim_modifyreg(chan, STM32_BTIM_EGR_OFFSET, 0, ATIM_EGR_UG);
@ -1043,7 +1046,115 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg)
{
return -ENOTTY;
FAR struct stm32_chan_s *chan = dev->ad_priv;
int ret = OK;
switch (cmd)
{
#ifdef HAVE_DMA
case IO_DMABUFFER_INIT:
{
uint16_t *buffer = (uint16_t *)arg;
/* The caller is responsible for providing buffer with
* suitable length equal to CONFIG_STM32_DACxCHy_DMA_BUFFER_SIZE
*/
dma_bufferinit(chan, buffer, chan->buffer_len * sizeof(buffer));
break;
}
#endif
default:
{
aerr("ERROR: Unknown cmd: %d\n", cmd);
ret = -ENOTTY;
break;
}
}
return ret;
}
#ifdef HAVE_DMA
/****************************************************************************
* Name: dma_bufferinit
****************************************************************************/
static void dma_bufferinit(FAR struct stm32_chan_s *chan, uint16_t* buffer,
uint16_t len)
{
memcpy(chan->dmabuffer, buffer, len);
}
/****************************************************************************
* Name: dma_remap
****************************************************************************/
static int dma_remap(FAR struct stm32_chan_s *chan)
{
#if defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX)
uint32_t regval = 0;
switch (chan->intf)
{
case 0:
{
/* Remap DMA1CH3 to DAC1CH1 */
regval |= SYSCFG_CFGR1_DAC1CH1_DMARMP;
/* Remap DAC trigger for STM32F33XX if needed */
# ifdef CONFIG_STM32_STM32F33XX
# if defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG1)
modifyreg32(STM32_SYSCFG_CFGR3, 0, SYSCFG_CFGR3_DAC1_TRIG3_RMP);
# elif defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG2)
modifyreg32(STM32_SYSCFG_CFGR3, 0, SYSCFG_CFGR3_DAC1_TRIG5_RMP);
# endif
# endif
break;
}
case 1:
{
/* Remap DMA1CH4 to DAC1CH2 */
regval |= SYSCFG_CFGR1_DAC1CH2_DMARMP;
/* Remap DAC trigger for STM32F33XX if needed */
# ifdef CONFIG_STM32_STM32F33XX
# if defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG1)
modifyreg32(STM32_SYSCFG_CFGR3, 0, SYSCFG_CFGR3_DAC1_TRIG3_RMP);
# elif defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG2)
modifyreg32(STM32_SYSCFG_CFGR3, 0, SYSCFG_CFGR3_DAC1_TRIG5_RMP);
# endif
# endif
break;
}
case 2:
{
/* Remap DMA1CH5 to DAC2CH1 */
regval |= SYSCFG_CFGR1_DAC2CH1_DMARMP;
break;
}
default:
{
return -EINVAL;
}
}
modifyreg32(STM32_SYSCFG_BASE, 0, regval);
#endif
return OK;
}
/****************************************************************************
@ -1061,7 +1172,7 @@ static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg)
*
****************************************************************************/
#ifdef HAVE_DMA
#ifdef HAVE_TIMER
static int dac_timinit(FAR struct stm32_chan_s *chan)
{
uint32_t pclk;
@ -1071,17 +1182,6 @@ static int dac_timinit(FAR struct stm32_chan_s *chan)
uint32_t regaddr;
uint32_t setbits;
/* Do nothing if HRTIM is selected as trigger.
* All necessary configuration is done in the HRTIM driver.
*/
#ifdef HAVE_HRTIM
if (chan->timer == TIM_INDEX_HRTIM)
{
return OK;
}
#endif
/* Configure the time base: Timer period, prescaler, clock division,
* counter mode (up).
*/
@ -1226,6 +1326,7 @@ static int dac_timinit(FAR struct stm32_chan_s *chan)
return OK;
}
#endif
#endif /* HAVE_DMA */
/****************************************************************************
* Name: dac_chaninit
@ -1293,6 +1394,10 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan)
if (chan->hasdma)
{
/* Remap DMA request if necessary*/
dma_remap(chan);
/* Yes.. DAC trigger enable */
stm32_dac_modify_cr(chan, 0, DAC_CR_TEN);
@ -1306,14 +1411,22 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan)
return -EBUSY;
}
/* Configure the timer that supports the DMA operation */
/* Configure the timer that supports the DMA operation
* Do nothing if HRTIM is selected as trigger.
* All necessary configuration is done in the HRTIM driver.
*/
ret = dac_timinit(chan);
if (ret < 0)
#ifdef HAVE_TIMER
if (chan->timer != TIM_INDEX_HRTIM)
{
aerr("ERROR: Failed to initialize the DMA timer: %d\n", ret);
return ret;
ret = dac_timinit(chan);
if (ret < 0)
{
aerr("ERROR: Failed to initialize the DMA timer: %d\n", ret);
return ret;
}
}
#endif
}
#endif

11
arch/arm/src/stm32/stm32_dac.h
View File

@ -100,6 +100,17 @@
# undef CONFIG_STM32_TIM14_DAC
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/* IOCTL commands specific to this driver */
enum dac_io_cmds
{
IO_DMABUFFER_INIT = 0,
};
/************************************************************************************
* Public Function Prototypes
************************************************************************************/

144
arch/arm/src/stm32/stm32_hrtim.c
View File

@ -59,12 +59,54 @@
#warning "HRTIM UNDER DEVELOPMENT !"
#if defined(CONFIG_STM32_HRTIM_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMA_DAC) || \
defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMA_IRQ)
# ifndef CONFIG_STM32_HRTIM_TIMA
# error "CONFIG_STM32_HRTIM_TIMA must be set"
# endif
#endif
#if defined(CONFIG_STM32_HRTIM_TIMB_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_DAC) || \
defined(CONFIG_STM32_HRTIM_TIMB_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_IRQ)
# ifndef CONFIG_STM32_HRTIM_TIMB
# error "CONFIG_STM32_HRTIM_TIMB must be set"
# endif
#endif
#if defined(CONFIG_STM32_HRTIM_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMC_DAC) || \
defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ)
# ifndef CONFIG_STM32_HRTIM_TIMC
# error "CONFIG_STM32_HRTIM_TIMC must be set"
# endif
#endif
#if defined(CONFIG_STM32_HRTIM_TIMD_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_DAC) || \
defined(CONFIG_STM32_HRTIM_TIMD_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_IRQ)
# ifndef CONFIG_STM32_HRTIM_TIMD
# error "CONFIG_STM32_HRTIM_TIMD must be set"
# endif
#endif
#if defined(CONFIG_STM32_HRTIM_TIME_PWM) || defined(CONFIG_STM32_HRTIM_TIME_DAC) || \
defined(CONFIG_STM32_HRTIM_TIME_CAP) || defined(CONFIG_STM32_HRTIM_TIME_IRQ)
# ifndef CONFIG_STM32_HRTIM_TIME
# error "CONFIG_STM32_HRTIM_TIME must be set"
# endif
#endif
#ifdef HRTIM_HAVE_ADC
# error HRTIM ADC Triggering not supported yet
#endif
#ifdef CONFIG_STM32_HRTIM_DAC
# error HRTIM DAC Triggering not supported yet
#if defined(CONFIG_STM32_HRTIM_DAC)
#if !defined(CONFIG_STM32_HRTIM_MASTER_DAC) && !defined(CONFIG_STM32_HRTIM_TIMA_DAC) && \
!defined(CONFIG_STM32_HRTIM_TIMB_DAC) && !defined(CONFIG_STM32_HRTIM_TIMC_DAC) && \
!defined(CONFIG_STM32_HRTIM_TIMD_DAC) && !defined(CONFIG_STM32_HRTIM_TIME_DAC)
# warning "CONFIG_STM32_HRTIM_DAC enabled but no timer selected"
# endif
#endif
#if defined(CONFIG_STM32_HRTIM_MASTER_DAC) || defined(CONFIG_STM32_HRTIM_TIMA_DAC) || \
defined(CONFIG_STM32_HRTIM_TIMB_DAC) || defined(CONFIG_STM32_HRTIM_TIMC_DAC) || \
defined(CONFIG_STM32_HRTIM_TIMD_DAC) || defined(CONFIG_STM32_HRTIM_TIME_DAC)
# ifndef CONFIG_STM32_HRTIM_DAC
# error "CONFIG_STM32_HRTIM_DAC must be set"
# endif
#endif
#ifdef HRTIM_HAVE_CAPTURE
@ -98,57 +140,74 @@
/* HRTIM default configuration **********************************************/
#ifndef HRTIM_TIMER_MASTER
# warning "HRTIM_MASTER_PRESCALER is not set. Set the default value HRTIM_PRESCALER_2"
# define HRTIM_MASTER_PRESCALER HRTIM_PRESCALER_2
#endif
#ifndef HRTIM_MASTER_MODE
#if defined(CONFIG_STM32_HRTIM_MASTER) && !defined(HRTIM_MASTER_MODE)
# warning "HRTIM_MASTER_MODE is not set. Set the default value 0"
# define HRTIM_MASTER_MODE 0
#endif
#ifndef HRTIM_TIMA_MODE
#if defined(CONFIG_STM32_HRTIM_TIMA) && !defined( HRTIM_TIMA_MODE)
# warning "HRTIM_TIMA_MODE is not set. Set the default value 0"
# define HRTIM_TIMA_MODE 0
#endif
#ifndef HRTIM_TIMB_MODE
#if defined(CONFIG_STM32_HRTIM_TIMB) && !defined(HRTIM_TIMB_MODE)
# warning "HRTIM_TIMB_MODE is not set. Set the default value 0"
# define HRTIM_TIMB_MODE 0
#endif
#ifndef HRTIM_TIMC_MODE
#if defined(CONFIG_STM32_HRTIM_TIMC) && !defined(HRTIM_TIMC_MODE)
# warning "HRTIM_TIMC_MODE is not set. Set the default value 0"
# define HRTIM_TIMC_MODE 0
#endif
#ifndef HRTIM_TIMD_MODE
#if defined(CONFIG_STM32_HRTIM_TIMD) && !defined(HRTIM_TIMD_MODE)
# warning "HRTIM_TIMD_MODE is not set. Set the default value 0"
# define HRTIM_TIMD_MODE 0
#endif
#ifndef HRTIM_TIME_MODE
#if defined(CONFIG_STM32_HRTIM_TIME) && !defined(HRTIM_TIME_MODE)
# warning "HRTIM_TIME_MODE is not set. Set the default value 0"
# define HRTIM_TIME_MODE 0
#endif
#ifndef HRTIM_TIMA_UPDATE
#if defined(CONFIG_STM32_HRTIM_TIMA) && !defined( HRTIM_TIMA_UPDATE)
# warning "HRTIM_TIMA_UPDATE is not set. Set the default value 0"
# define HRTIM_TIMA_UPDATE 0
#endif
#ifndef HRTIM_TIMB_UPDATE
#if defined(CONFIG_STM32_HRTIM_TIMB) && !defined(HRTIM_TIMB_UPDATE)
# warning "HRTIM_TIMB_UPDATE is not set. Set the default value 0"
# define HRTIM_TIMB_UPDATE 0
#endif
#ifndef HRTIM_TIMC_UPDATE
#if defined(CONFIG_STM32_HRTIM_TIMC) && !defined(HRTIM_TIMC_UPDATE)
# warning "HRTIM_TIMC_UPDATE is not set. Set the default value 0"
# define HRTIM_TIMC_UPDATE 0
#endif
#ifndef HRTIM_TIMD_UPDATE
#if defined(CONFIG_STM32_HRTIM_TIMD) && !defined(HRTIM_TIMD_UPDATE)
# warning "HRTIM_TIMD_UPDATE is not set. Set the default value 0"
# define HRTIM_TIMD_UPDATE 0
#endif
#ifndef HRTIM_TIME_UPDATE
#if defined(CONFIG_STM32_HRTIM_TIME) && !defined(HRTIM_TIME_UPDATE)
# warning "HRTIM_TIME_UPDATE is not set. Set the default value 0"
# define HRTIM_TIME_UPDATE 0
#endif
#ifndef HRTIM_TIMA_RESET
#if defined(CONFIG_STM32_HRTIM_TIMA) && !defined( HRTIM_TIMA_RESET)
# warning "HRTIM_TIMA_RESET is not set. Set the default value 0"
# define HRTIM_TIMA_RESET 0
#endif
#ifndef HRTIM_TIMB_RESET
#if defined(CONFIG_STM32_HRTIM_TIMB) && !defined(HRTIM_TIMB_RESET)
# warning "HRTIM_TIMB_RESET is not set. Set the default value 0"
# define HRTIM_TIMB_RESET 0
#endif
#ifndef HRTIM_TIMC_RESET
#if defined(CONFIG_STM32_HRTIM_TIMC) && !defined(HRTIM_TIMC_RESET)
# warning "HRTIM_TIMC_RESET is not set. Set the default value 0"
# define HRTIM_TIMC_RESET 0
#endif
#ifndef HRTIM_TIMD_RESET
#if defined(CONFIG_STM32_HRTIM_TIMD) && !defined(HRTIM_TIMD_RESET)
# warning "HRTIM_TIMD_RESET is not set. Set the default value 0"
# define HRTIM_TIMD_RESET 0
#endif
#ifndef HRTIM_TIME_RESET
#if defined(CONFIG_STM32_HRTIM_TIME) && !defined(HRTIM_TIME_RESET)
# warning "HRTIM_TIME_RESET is not set. Set the default value 0"
# define HRTIM_TIME_RESET 0
#endif
@ -508,7 +567,7 @@ static int hrtim_outputs_enable(FAR struct hrtim_dev_s *dev, uint16_t outputs,
#ifdef HRTIM_HAVE_ADC
static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv);
#endif
#ifdef HRTIM_HAVE_DAC
#ifdef CONFIG_STM32_HRTIM_DAC
static int hrtim_dac_config(FAR struct stm32_hrtim_s *priv);
#endif
#ifdef HRTIM_HAVE_FAULTS
@ -573,13 +632,18 @@ static struct stm32_hrtim_tim_s g_master =
.tim =
{
.base = STM32_HRTIM1_MASTER_BASE,
/* If MASTER is disabled, we need only MASTER base */
#ifdef CONFIG_STM32_HRTIM_MASTER
.pclk = HRTIM_CLOCK/HRTIM_MASTER_PRESCALER,
.mode = HRTIM_MASTER_MODE,
#ifdef CONFIG_STM32_HRTIM_MASTER_DAC
# ifdef CONFIG_STM32_HRTIM_MASTER_DAC
.dac = HRTIM_MASTER_DAC,
#endif
#ifdef CONFIG_STM32_HRTIM_MASTER_IRQ
# endif
# ifdef CONFIG_STM32_HRTIM_MASTER_IRQ
.irq = HRTIM_IRQ_MASTER
# endif
#endif
},
.priv = NULL,
@ -1688,11 +1752,13 @@ static int hrtim_tim_clocks_config(FAR struct stm32_hrtim_s *priv)
/* Configure Master Timer clock */
#ifdef CONFIG_STM32_HRTIM_MASTER
ret = hrtim_tim_clock_config(priv, HRTIM_TIMER_MASTER, HRTIM_MASTER_PRESCALER);
if (ret < 0)
{
goto errout;
}
#endif
/* Configure Timer A clock */
@ -2213,7 +2279,7 @@ static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv)
}
#endif
#ifdef HRTIM_HAVE_DAC
#ifdef CONFIG_STM32_HRTIM_DAC
/****************************************************************************
* Name: hrtim_tim_dac_cfg
@ -2231,7 +2297,7 @@ static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv)
*
****************************************************************************/
static int hrtim_tim_dac_cfg(FAS struct stm32_hrtim_s *priv, uint8_t timer,
static int hrtim_tim_dac_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer,
uint8_t dac)
{
FAR struct stm32_hrtim_tim_s *tim;
@ -2264,36 +2330,36 @@ static int hrtim_tim_dac_cfg(FAS struct stm32_hrtim_s *priv, uint8_t timer,
static int hrtim_dac_config(FAR struct stm32_hrtim_s *priv)
{
FAR struct stm32_hrtim_slave_priv_s *slave_priv;
FAR struct stm32_hrtim_timcmn_s *tim;
#ifdef CONFIG_STM32_HRTIM_MASTER_DAC
slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->master->priv;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_MASTER, dac);
tim = (struct stm32_hrtim_timcmn_s*)priv->master;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_MASTER, tim->dac);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMA_DAC
slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->tima->priv;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMA, dac);
tim = (struct stm32_hrtim_timcmn_s*)priv->tima;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMA, tim->dac);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMB_DAC
slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timb->priv;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMB, dac);
tim = (struct stm32_hrtim_timcmn_s*)priv->timb;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMB, tim->dac);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMC_DAC
slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timc->priv;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMC, dac);
tim = (struct stm32_hrtim_timcmn_s*)priv->timc;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMC, tim->dac);
#endif
#ifdef CONFIG_STM32_HRTIM_TIMD_DAC
slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timd->priv;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMD, dac);
tim = (struct stm32_hrtim_timcmn_s*)priv->timd;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMD, tim->dac);
#endif
#ifdef CONFIG_STM32_HRTIM_TIME_DAC
slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->time->priv;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIME, dac);
tim = (struct stm32_hrtim_timcmn_s*)priv->time;
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIME, tim->dac);
#endif
return OK;
@ -3338,7 +3404,7 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv)
/* Configure DAC synchronization */
#ifdef HRTIM_HAVE_DAC
#ifdef CONFIG_STM32_HRTIM_DAC
ret = hrtim_dac_config(priv);
if (ret != OK)
{
@ -3382,7 +3448,9 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv)
/* Enable Master Timer */
#ifdef CONFIG_STM32_HRTIM_MASTER
regval |= HRTIM_MCR_MCEN;
#endif
/* Enable Slave Timers */

20
arch/arm/src/stm32/stm32_hrtim.h
View File

@ -494,16 +494,6 @@ enum stm32_outputs_e
HRTIM_OUT_TIME_CH2 = (1 << 9)
};
/* DAC synchronization event */
enum stm32_hrtim_dacsync_e
{
HRTIM_DACSYNC_DIS,
HRTIM_DACSYNC_1,
HRTIM_DACSYNC_2,
HRTIM_DACSYNC_3
};
/* HRTIM Deadtime Locks */
enum stm32_hrtim_deadtime_lock_e
@ -665,14 +655,14 @@ enum stm32_hrtim_adc_trq24_e
HRTIM_ADCTRG24_ERST = (1 << 31),
};
/* HRTIM DAC synchronization */
/* HRTIM DAC synchronization events */
enum stm32_hrtim_dac_e
{
HRTIM_DAC_SYNC_DIS = 0,
HRTIM_DAC_SYNC_1 = 1,
HRTIM_DAC_SYNC_2 = 2,
HRTIM_DAC_SYNC_3 = 3
HRTIM_DAC_TRIG_DIS = 0,
HRTIM_DAC_TRIG1 = 1,
HRTIM_DAC_TRIG2 = 2,
HRTIM_DAC_TRIG3 = 3
};
/* HRTIM Master Timer interrupts */

9
arch/arm/src/stm32f0/Kconfig
View File

@ -590,10 +590,6 @@ config STM32F0_HAVE_FSMC
bool
default n
config STM32F0_HAVE_HRTIM1
bool
default n
config STM32F0_HAVE_USART3
bool
default n
@ -950,11 +946,6 @@ config STM32F0_HASH
default n
depends on STM32F0_STM32F207 || STM32F0_STM32F40XX
config STM32F0_HRTIM1
bool "HRTIM1"
default n
depends on STM32F0_HAVE_HRTIM1
config STM32F0_I2C1
bool "I2C1"
default n

17
drivers/analog/comp.c
View File

@ -67,8 +67,8 @@ static int comp_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
#ifndef CONFIG_DISABLE_POLL
static int comp_poll(FAR struct file *filep, FAR struct pollfd *fds,
bool setup);
#endif
static int comp_notify(FAR struct comp_dev_s *dev, uint8_t val);
#endif
/****************************************************************************
* Private Data
@ -90,10 +90,12 @@ static const struct file_operations comp_fops =
#endif
};
#ifndef CONFIG_DISABLE_POLL
static const struct comp_callback_s g_comp_callback =
{
comp_notify /* au_notify */
};
#endif
/****************************************************************************
* Private Functions
@ -141,14 +143,13 @@ static void comp_pollnotify(FAR struct comp_dev_s *dev,
}
}
}
#else
# define comp_pollnotify(dev,event)
#endif
/****************************************************************************
* Name: comp_semtake
****************************************************************************/
#ifndef CONFIG_DISABLE_POLL
static void comp_semtake(FAR sem_t *sem)
{
while (sem_wait(sem) != 0)
@ -160,6 +161,7 @@ static void comp_semtake(FAR sem_t *sem)
ASSERT(get_errno() == EINTR);
}
}
#endif
/****************************************************************************
* Name: comp_poll
@ -241,6 +243,7 @@ static int comp_poll(FAR struct file *filep, FAR struct pollfd *fds,
*
****************************************************************************/
#ifndef CONFIG_DISABLE_POLL
static int comp_notify(FAR struct comp_dev_s *dev, uint8_t val)
{
/* TODO: store values in FIFO? */
@ -252,6 +255,7 @@ static int comp_notify(FAR struct comp_dev_s *dev, uint8_t val)
return 0;
}
#endif
/****************************************************************************
* Name: comp_open
@ -377,13 +381,16 @@ static ssize_t comp_read(FAR struct file *filep, FAR char *buffer, size_t buflen
/* If non-blocking read, read the value immediately and return. */
#ifndef CONFIG_DISABLE_POLL
if (filep->f_oflags & O_NONBLOCK)
#endif
{
ret = dev->ad_ops->ao_read(dev);
buffer[0] = (uint8_t)ret;
return 1;
}
#ifndef CONFIG_DISABLE_POLL
ret = sem_wait(&dev->ad_readsem);
if (ret < 0)
{
@ -392,7 +399,9 @@ static ssize_t comp_read(FAR struct file *filep, FAR char *buffer, size_t buflen
}
buffer[0] = dev->val;
return 1;
#endif
}
/****************************************************************************
@ -437,6 +446,7 @@ int comp_register(FAR const char *path, FAR struct comp_dev_s *dev)
DEBUGASSERT(dev->ad_ops != NULL);
#ifndef CONFIG_DISABLE_POLL
if (dev->ad_ops->ao_bind != NULL)
{
ret = dev->ad_ops->ao_bind(dev, &g_comp_callback);
@ -446,6 +456,7 @@ int comp_register(FAR const char *path, FAR struct comp_dev_s *dev)
return ret;
}
}
#endif
/* Register the COMP character driver */