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arch/arm64: add initial support for ZYNQ MPSOC

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arch/arm64: add initial support for ZYNQ MPSOC

arch/arm64: add initial support for ZYNQ MPSOC
This commit is contained in:
zouboan 2024-07-12 22:42:29 +08:00 committed by Alan Carvalho de Assis
parent c86ef1cbc4
commit ea532cb11a
12 changed files with 2200 additions and 0 deletions
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16
arch/arm64/Kconfig
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@ -100,6 +100,17 @@ config ARCH_CHIP_IMX9
---help---
NXP i.MX9 (ARMv8.2a) applications processors
config ARCH_CHIP_ZYNQ_MPSOC
bool "XilinX Zynq UltraScale+ MPSoC"
select ARCH_CORTEX_A53
select ARCH_HAVE_ADDRENV
select ARCH_HAVE_RESET
select ARCH_HAVE_IRQTRIGGER
select ARCH_NEED_ADDRENV_MAPPING
select ARM64_HAVE_PSCI
---help---
XilinX ZYNQ MPSOC
config ARCH_CHIP_ARM64_CUSTOM
bool "Custom ARM64 chip"
select ARCH_CHIP_CUSTOM
@ -245,6 +256,7 @@ config ARCH_CHIP
string
default "a64" if ARCH_CHIP_A64
default "rk3399" if ARCH_CHIP_RK3399
default "zynq-mpsoc" if ARCH_CHIP_ZYNQ_MPSOC
default "qemu" if ARCH_CHIP_QEMU
default "goldfish" if ARCH_CHIP_GOLDFISH
default "fvp-v8r" if ARCH_CHIP_FVP_ARMV8R
@ -362,4 +374,8 @@ if ARCH_CHIP_GOLDFISH
source "arch/arm64/src/goldfish/Kconfig"
endif
if ARCH_CHIP_ZYNQ_MPSOC
source "arch/arm64/src/zynq-mpsoc/Kconfig"
endif
endif # ARCH_ARM64

71
arch/arm64/include/zynq-mpsoc/chip.h Normal file
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@ -0,0 +1,71 @@
/****************************************************************************
* arch/arm64/include/zynq-mpsoc/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM64_INCLUDE_ZYNQ_MPSOC_CHIP_H
#define __ARCH_ARM64_INCLUDE_ZYNQ_MPSOC_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Number of bytes in x kibibytes/mebibytes/gibibytes */
#define KB(x) ((x) << 10)
#define MB(x) (KB(x) << 10)
#define GB(x) (MB(UINT64_C(x)) << 10)
/* XilinX ZYNQ_MPSOC Generic Interrupt Controller v2: Distributor & Redist */
#define CONFIG_GICD_BASE 0xf9010000
#define CONFIG_GICR_BASE 0xf9020000
#define CONFIG_GICR_OFFSET 0x20000
/* XilinX ZYNQ_MPSOC Memory Map: RAM and Device I/O */
#define CONFIG_RAMBANK1_ADDR 0x00000000
#define CONFIG_RAMBANK1_SIZE MB(2047)
#define CONFIG_DEVICEIO_BASEADDR 0xE0000000
#define CONFIG_DEVICEIO_SIZE MB(512)
/* U-Boot loads NuttX at this address (kernel_addr_r) */
#define CONFIG_LOAD_BASE 0x02080000
#define MPID_TO_CLUSTER_ID(mpid) ((mpid) & ~0xff)
/****************************************************************************
* Assembly Macros
****************************************************************************/
#ifdef __ASSEMBLY__
.macro get_cpu_id xreg0
mrs \xreg0, mpidr_el1
ubfx \xreg0, \xreg0, #0, #8
.endm
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM64_INCLUDE_ZYNQ_MPSOC_CHIP_H */

110
arch/arm64/include/zynq-mpsoc/irq.h Normal file
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@ -0,0 +1,110 @@
/****************************************************************************
* arch/arm64/include/zynq-mpsoc/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM64_INCLUDE_ZYNQ_MPSOC_IRQ_H
#define __ARCH_ARM64_INCLUDE_ZYNQ_MPSOC_IRQ_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Rockchip ZYNQ_MPSOC Interrupts */
#define NR_IRQS 166 /* Total number of interrupts */
#define ZYNQ_MPSOC_IRQ_RPU0_PERF_MON 40 /* RPU0 performance monitor IRQ */
#define ZYNQ_MPSOC_IRQ_RPU1_PERF_MON 41 /* RPU1 performance monitorIRQ */
#define ZYNQ_MPSOC_IRQ_OCM_ECC_ERROR 42 /* OCM CE or UE ECC error IRQ */
#define ZYNQ_MPSOC_IRQ_LPD_APB_ERROR 43 /* APB slave port error IRQ */
#define ZYNQ_MPSOC_IRQ_RPU0_ECC_ERROR 44 /* RPU0 ECC error IRQ */
#define ZYNQ_MPSOC_IRQ_RPU1_ECC_ERROR 45 /* RPU0 ECC error IRQ */
#define ZYNQ_MPSOC_IRQ_NAND 46 /* NAND controller IRQ */
#define ZYNQ_MPSOC_IRQ_QSPI 47 /* QSPI controller IRQ */
#define ZYNQ_MPSOC_IRQ_GPIO 48 /* GPIO controller IRQ */
#define ZYNQ_MPSOC_IRQ_I2C0 49 /* I2C0 controller IRQ */
#define ZYNQ_MPSOC_IRQ_I2C1 50 /* I2C1 controller IRQ */
#define ZYNQ_MPSOC_IRQ_SPI0 51 /* SPI0 controller IRQ */
#define ZYNQ_MPSOC_IRQ_SPI1 52 /* SPI1 controller IRQ */
#define ZYNQ_MPSOC_IRQ_UART0 53 /* UART0 controller IRQ */
#define ZYNQ_MPSOC_IRQ_UART1 54 /* UART1 controller IRQ */
#define ZYNQ_MPSOC_IRQ_CAN0 55 /* CAN0 controller IRQ */
#define ZYNQ_MPSOC_IRQ_CAN1 56 /* CAN1 controller IRQ */
#define ZYNQ_MPSOC_IRQ_LPD_APM 57 /* LPD and OCM APM IRQ */
#define ZYNQ_MPSOC_IRQ_RTC_ALARM 58 /* RTC alarm IRQ */
#define ZYNQ_MPSOC_IRQ_RTC_SECONDS 59 /* RTC sceond IRQ */
#define ZYNQ_MPSOC_IRQ_CLKMON 60 /* LPD clock test IRQ */
#define ZYNQ_MPSOC_IRQ_IPI_CH7 61 /* IPI channel 7 IRQ */
#define ZYNQ_MPSOC_IRQ_IPI_CH8 62 /* IPI channel 8 IRQ */
#define ZYNQ_MPSOC_IRQ_IPI_CH9 63 /* IPI channel 9 IRQ */
#define ZYNQ_MPSOC_IRQ_IPI_CH10 64 /* IPI channel 10 IRQ */
#define ZYNQ_MPSOC_IRQ_IPI_CH2 65 /* IPI channel 2 IRQ */
#define ZYNQ_MPSOC_IRQ_IPI_CH1 66 /* IPI channel 1 IRQ */
#define ZYNQ_MPSOC_IRQ_IPI_CH0 67 /* IPI channel 0 IRQ */
#define ZYNQ_MPSOC_IRQ_TTC0 68 /* TTC0 timer IRQ */
#define ZYNQ_MPSOC_IRQ_TTC1 71 /* TTC1 timer IRQ */
#define ZYNQ_MPSOC_IRQ_TTC2 74 /* TTC2 timer IRQ */
#define ZYNQ_MPSOC_IRQ_TTC3 77 /* TTC3 timer IRQ */
#define ZYNQ_MPSOC_IRQ_SDIO0 80 /* SDIO0 controller IRQ */
#define ZYNQ_MPSOC_IRQ_SDIO1 81 /* SDIO1 controller IRQ */
#define ZYNQ_MPSOC_IRQ_SDIO0_WAKEUP 82 /* SDIO0 controller wakeup IRQ */
#define ZYNQ_MPSOC_IRQ_SDIO1_WAKEUP 83 /* SDIO1 controller wakeup IRQ */
#define ZYNQ_MPSOC_IRQ_LPD_SWDT 84 /* LPD watch dog IRQ */
#define ZYNQ_MPSOC_IRQ_CSU_SWDT 85 /* CSU watch dog IRQ */
#define ZYNQ_MPSOC_IRQ_LPD_ATB 86 /* LPD ATB IRQ */
#define ZYNQ_MPSOC_IRQ_AIB 87 /* AIB IRQ */
#define ZYNQ_MPSOC_IRQ_SYSMON 88 /* interrupt monitor IRQ */
#define ZYNQ_MPSOC_IRQ_GEM0 89 /* GEM0 controller IRQ */
#define ZYNQ_MPSOC_IRQ_GEM0_WAKEUP 90 /* GEM0 controller wakeup IRQ */
#define ZYNQ_MPSOC_IRQ_GEM1 91 /* GEM1 controller IRQ */
#define ZYNQ_MPSOC_IRQ_GEM1_WAKEUP 92 /* GEM1 controller wakeup IRQ */
#define ZYNQ_MPSOC_IRQ_GEM2 93 /* GEM2 controller IRQ */
#define ZYNQ_MPSOC_IRQ_GEM2_WAKEUP 94 /* GEM2 controller wakeup IRQ */
#define ZYNQ_MPSOC_IRQ_GEM3 95 /* GEM3 controller IRQ */
#define ZYNQ_MPSOC_IRQ_GEM3_WAKEUP 96 /* GEM3 controller wakeup IRQ */
#define ZYNQ_MPSOC_IRQ_USB0_ENDPOINT 97 /* USB0 controller IRQ */
#define ZYNQ_MPSOC_IRQ_USB0_OTG 101 /* USB0 OTG controller IRQ */
#define ZYNQ_MPSOC_IRQ_USB1_ENDPOINT 102 /* USB1 controller IRQ */
#define ZYNQ_MPSOC_IRQ_USB1_OTG 106 /* USB1 OTG controller IRQ */
#define ZYNQ_MPSOC_IRQ_USB0_WAKEUP 107 /* USB0 controller wakeup IRQ */
#define ZYNQ_MPSOC_IRQ_USB1_WAKEUP 108 /* USB1 controller wakeup IRQ */
#define ZYNQ_MPSOC_IRQ_LPD_DMA 109 /* LPD DMA controller IRQ */
#define ZYNQ_MPSOC_IRQ_CSU 117 /* config and security IRQ */
#define ZYNQ_MPSOC_IRQ_CSU_DMA 118 /* CSU DMA controller IRQ */
#define ZYNQ_MPSOC_IRQ_EFUSE 119 /* eFuse controller IRQ */
#define ZYNQ_MPSOC_IRQ_PCIE_MSI0 146 /* PCIe MSI interrupt 0-31 */
#define ZYNQ_MPSOC_IRQ_PCIE_MSI1 147 /* PCIe MSI interrupt 32-63 */
#define ZYNQ_MPSOC_IRQ_PCIE_INTX 148 /* PCIe INTxIRQ */
#define ZYNQ_MPSOC_IRQ_PCIE_DMA 149 /* PCIe DMA controller IRQ */
#define ZYNQ_MPSOC_IRQ_PCIE_MSC 150 /* PCIe MSC controller IRQ */
#define ZYNQ_MPSOC_IRQ_DISPLAY 151 /* display controller IRQ */
#define ZYNQ_MPSOC_IRQ_FPD_APB 152
#define ZYNQ_MPSOC_IRQ_FPD_ATB 153
#define ZYNQ_MPSOC_IRQ_DPDMA 154 /* display DMA controller IRQ */
#define ZYNQ_MPSOC_IRQ_FPD_APM 155
#define ZYNQ_MPSOC_IRQ_FPD_DMA 156
#define ZYNQ_MPSOC_IRQ_GPU 164 /* GPU controller IRQ */
#define ZYNQ_MPSOC_IRQ_SATA 165 /* SATA controller IRQ */
#endif /* __ARCH_ARM64_INCLUDE_ZYNQ_MPSOC_IRQ_H */

46
arch/arm64/src/zynq-mpsoc/Kconfig Normal file
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@ -0,0 +1,46 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_CHIP_ZYNQ_MPSOC
config XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
int "Zynq Mpsoc cpu clock"
default 1199988037
---help---
Canonical definitions for cpu PSU_CORTEXA53_0.
config XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
int "Zynq Mpsoc peripheral clock"
default 99999001
---help---
Canonical definitions for peripheral PSU_CORTEXA53_0.
config XPAR_PSU_UART_0_UART_CLK_FREQ_HZ
int "Zynq Mpsoc uart0 clock"
default 99999001
---help---
Clock definitions for uart0.
menu "XILINX ZYNQ_MPSOC Peripheral Selection"
config ZYNQ_MPSOC_UART0
bool "UART 0"
default y
select UART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
---help---
Select to enable support for UART0.
config ZYNQ_MPSOC_UART1
bool "UART 1"
default n
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
---help---
Select to enable support for UART1.
endmenu # XILINX ZYNQ_MPSOC Peripheral Selection
endif # ARCH_CHIP_ZYNQ_MPSOC

28
arch/arm64/src/zynq-mpsoc/Make.defs Normal file
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@ -0,0 +1,28 @@
############################################################################
# arch/arm64/src/zynq-mpsoc/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include common/Make.defs
# Rockchip zynq mpsoc specific C source files
CHIP_CSRCS = zynq_boot.c zynq_serial.c
ifeq ($(CONFIG_ARCH_EARLY_PRINT),y)
CHIP_ASRCS = zynq_lowputc.S
endif

42
arch/arm64/src/zynq-mpsoc/chip.h Normal file
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@ -0,0 +1,42 @@
/****************************************************************************
* arch/arm64/src/zynq-mpsoc/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM64_SRC_ZYNQ_MPSOC_CHIP_H
#define __ARCH_ARM64_SRC_ZYNQ_MPSOC_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <nuttx/arch.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Macro Definitions
****************************************************************************/
#endif /* __ARCH_ARM64_SRC_ZYNQ_MPSOC_CHIP_H */

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arch/arm64/src/zynq-mpsoc/hardware/zynq_memorymap.h Normal file
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@ -0,0 +1,80 @@
/****************************************************************************
* arch/arm64/src/zynq-mpsoc/hardware/zynq_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM64_SRC_ZYNQ_ZYNQ_MPSOC_HARDWARE_ZYNQ_MEMORYMAP_H
#define __ARCH_ARM64_SRC_ZYNQ_ZYNQ_MPSOC_HARDWARE_ZYNQ_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Peripheral Base Addresses */
#define ZYNQ_MPSOC_UART0_ADDR 0xFF000000 /* UART0 reg base address */
#define ZYNQ_MPSOC_UART1_ADDR 0xFF010000 /* UART1 reg base address */
#define ZYNQ_MPSOC_I2C0_ADDR 0xFF020000 /* I2C0 reg base address */
#define ZYNQ_MPSOC_I2C1_ADDR 0xFF030000 /* I2C1 reg base address */
#define ZYNQ_MPSOC_SPI0_ADDR 0xFF040000 /* SPI0 reg base address */
#define ZYNQ_MPSOC_SPI1_ADDR 0xFF050000 /* SPI1 reg base address */
#define ZYNQ_MPSOC_CAN0_ADDR 0xFF060000 /* CAN0 reg base address */
#define ZYNQ_MPSOC_CAN1_ADDR 0xFF070000 /* CAN1 reg base address */
#define ZYNQ_MPSOC_GPIO_ADDR 0xFF0A0000 /* GPIO reg base address */
#define ZYNQ_MPSOC_GEM0_ADDR 0xFF0B0000 /* GEM0 reg base address */
#define ZYNQ_MPSOC_GEM1_ADDR 0xFF0C0000 /* GEM1 reg base address */
#define ZYNQ_MPSOC_GEM2_ADDR 0xFF0D0000 /* GEM2 reg base address */
#define ZYNQ_MPSOC_GEM3_ADDR 0xFF0E0000 /* GEM3 reg base address */
#define ZYNQ_MPSOC_MDIO_ADDR(ch) 0xFF0B0000 /* GEM3 reg base address */
#define ZYNQ_MPSOC_QSPI_ADDR 0xFF0F0000 /* QSPI reg base address */
#define ZYNQ_MPSOC_TTC0_ADDR 0xFF110000 /* NAND reg base address */
#define ZYNQ_MPSOC_TTC1_ADDR 0xFF120000 /* TTC0 reg base address */
#define ZYNQ_MPSOC_TTC2_ADDR 0xFF130000 /* TTC1 reg base address */
#define ZYNQ_MPSOC_TTC3_ADDR 0xFF140000 /* TTC2 reg base address */
#define ZYNQ_MPSOC_SD0_ADDR 0xFF160000 /* SD0 reg base address */
#define ZYNQ_MPSOC_SD1_ADDR 0xFF170000 /* SD1 reg base address */
#define ZYNQ_MPSOC_IOU_SLCR_ADDR 0xFF180000 /* IOU reg base address */
#define ZYNQ_MPSOC_IPIBUF_ADDR 0xFF990000 /* IPI buffer base address */
#define ZYNQ_MPSOC_USB0_ADDR 0xFF9D0000 /* USB0 reg base address */
#define ZYNQ_MPSOC_USB1_ADDR 0xFF9E0000 /* USB1 reg base address */
#define ZYNQ_MPSOC_AMS_ADDR 0xFFA50000 /* AMS reg base address */
#define ZYNQ_MPSOC_PSSYSMON_ADDR 0xFFA50800 /* PS sys monitor reg base */
#define ZYNQ_MPSOC_PLSYSMON_ADDR 0xFFA50C00 /* PL sys monitor reg base */
#define ZYNQ_MPSOC_CSU_SWDT_ADDR 0xFFCB0000 /* CSU wdg mon reg base */
#define ZYNQ_MPSOC_CRF_APB_CLKC_ADDR 0xFD1A0000
#define ZYNQ_MPSOC_CRL_APB_CLKC_ADDR 0xFF5E0000
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM64_SRC_ZYNQ_ZYNQ_MPSOC_HARDWARE_ZYNQ_MEMORYMAP_H */

209
arch/arm64/src/zynq-mpsoc/zynq_boot.c Normal file
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@ -0,0 +1,209 @@
/****************************************************************************
* arch/arm64/src/zynq-mpsoc/zynq_boot.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/cache.h>
#ifdef CONFIG_LEGACY_PAGING
# include <nuttx/page.h>
#endif
#include <arch/chip/chip.h>
#ifdef CONFIG_SMP
#include "arm64_smp.h"
#endif
#include "arm64_arch.h"
#include "arm64_internal.h"
#include "arm64_mmu.h"
#include "zynq_boot.h"
#include "zynq_serial.h"
/****************************************************************************
* Private Data
****************************************************************************/
static const struct arm_mmu_region g_mmu_regions[] =
{
MMU_REGION_FLAT_ENTRY("DEVICE_REGION",
CONFIG_DEVICEIO_BASEADDR, CONFIG_DEVICEIO_SIZE,
MT_DEVICE_NGNRNE | MT_RW | MT_SECURE),
MMU_REGION_FLAT_ENTRY("DRAM0_S0",
CONFIG_RAMBANK1_ADDR, CONFIG_RAMBANK1_SIZE,
MT_NORMAL | MT_RW | MT_SECURE),
};
const struct arm_mmu_config g_mmu_config =
{
.num_regions = nitems(g_mmu_regions),
.mmu_regions = g_mmu_regions,
};
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm64_el_init
*
* Description:
* The function called from arm64_head.S at very early stage for these
* platform, it's use to:
* - Handling special hardware initialize routine which is need to
* run at high ELs
* - Initialize system software such as hypervisor or security firmware
* which is need to run at high ELs
*
****************************************************************************/
void arm64_el_init(void)
{
#if (CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3)
uint64_t reg;
/* Disable alignment fault checking */
reg = read_sysreg(sctlr_el3);
reg &= ~SCTLR_A_BIT;
write_sysreg(reg, sctlr_el3);
/* At EL3, cntfrq_el0 is uninitialized. It must be set. */
write_sysreg(CONFIG_XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ, cntfrq_el0);
ARM64_ISB();
#endif
}
#ifdef CONFIG_SMP
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* If TLS is enabled, then the RTOS can get this information from the TLS
* info structure. Otherwise, the MCU-specific logic must provide some
* mechanism to provide the CPU index.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
int up_cpu_index(void)
{
/* Read the Multiprocessor Affinity Register (MPIDR)
* And return the CPU ID field
*/
return MPID_TO_CORE(GET_MPIDR(), 0);
}
/****************************************************************************
* Name: arm64_get_mpid
*
* Description:
* The function from cpu index to get cpu mpid which is reading
* from mpidr_el1 register. Different ARM64 Core will use different
* Affn define, the mpidr_el1 value is not CPU number, So we need
* to change CPU number to mpid and vice versa
*
****************************************************************************/
uint64_t arm64_get_mpid(int cpu)
{
return CORE_TO_MPID(cpu, 0);
}
/****************************************************************************
* Name: arm64_get_cpuid
*
* Description:
* The function from mpid to get cpu id
*
****************************************************************************/
int arm64_get_cpuid(uint64_t mpid)
{
return MPID_TO_CORE(mpid, 0);
}
#endif /* CONFIG_SMP */
/****************************************************************************
* Name: arm64_chip_boot
*
* Description:
* Complete boot operations started in arm64_head.S
*
****************************************************************************/
void arm64_chip_boot(void)
{
/* MAP IO and DRAM, enable MMU. */
arm64_mmu_init(true);
#if defined(CONFIG_SMP) || defined(CONFIG_ARCH_HAVE_PSCI)
/* arm64_psci_init("smc"); */
#endif
/* Perform board-specific device initialization. This would include
* configuration of board specific resources such as GPIOs, LEDs, etc.
*/
zynq_board_initialize();
#ifdef USE_EARLYSERIALINIT
/* Perform early serial initialization if we are going to use the serial
* driver.
*/
arm64_earlyserialinit();
#endif
}
#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT)
void arm64_netinitialize(void)
{
/* TODO: Support net initialize */
}
#endif

77
arch/arm64/src/zynq-mpsoc/zynq_boot.h Normal file
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@ -0,0 +1,77 @@
/****************************************************************************
* arch/arm64/src/zynq-mpsoc/zynq_boot.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM64_SRC_ZYNQ_MPSOC_ZYNQ_BOOT_H
#define __ARCH_ARM64_SRC_ZYNQ_MPSOC_ZYNQ_BOOT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <arch/chip/chip.h>
#include "arm64_internal.h"
#include "arm64_arch.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: zynq_board_initialize
*
* Description:
* All zynq architectures must provide the following entry point. This
* entry point is called in the initialization phase -- after
* a64_memory_initialize and after all memory has been configured and
* mapped but before any devices have been initialized.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void zynq_board_initialize(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM64_SRC_ZYNQ_MPSOC_ZYNQ_BOOT_H */

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/****************************************************************************
* arch/arm64/src/zynq-mpsoc/zynq_lowputc.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************
*
* DESCRIPTION
* Low-level console output for XilinX Zynq Mpsoc
*
***************************************************************************/
#include <nuttx/config.h>
#include "arm64_macro.inc"
/****************************************************************************
* Public Symbols
****************************************************************************/
.file "zynq_lowputc.S"
/****************************************************************************
* Assembly Macros
****************************************************************************/
/* XilinX Zynq Mpsoc XCZU28DR UART0 Base Address */
#define UART0_BASE_ADDRESS 0xff000000
#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
#define XUARTPS_SR_TXFULL 0x0010U /**< TX FIFO full */
#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/* Initialize Zynq Mpsoc UART
* xb: Register that contains the UART Base Address
* c: Scratch register number
*/
GTEXT(arm64_earlyprintinit)
SECTION_FUNC(text, arm64_earlyprintinit)
ret /* Do nothing because U-Boot has already initialized UART */
/* Wait for XCZU28DR UART to be ready to transmit
* xb: Register that contains the UART Base Address
* wt: Scratch register number
*/
.macro early_uart_ready xb, wt
1:
ldr \wt, [\xb, #XUARTPS_SR_OFFSET] /* UART_LSR (Line Status Register) */
tst \wt, #XUARTPS_SR_TXFULL /* Check THRE (TX Holding Register Empty) */
b.ne 1b /* Wait for the UART to be ready (THRE=1) */
.endm
/* Transmit character to XCZU28DR UART
* xb: Register that contains the UART base address
* wt: Register that contains the character to transmit
*/
.macro early_uart_transmit xb, wt
str \wt, [\xb, #XUARTPS_FIFO_OFFSET] /* -> Data Register */
.endm
/* Print a character on the UART - this function is called by C
* x0: Character to print
*/
GTEXT(arm64_lowputc)
SECTION_FUNC(text, arm64_lowputc)
ldr x15, =UART0_BASE_ADDRESS
early_uart_ready x15, w2
early_uart_transmit x15, w0
ret

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/****************************************************************************
* arch/arm64/src/zynq-mpsoc/zynq_serial.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM64_ZYNQ_MPSOC_ZYNQ_SERIAL_H
#define __ARCH_ARM64_ZYNQ_MPSOC_ZYNQ_SERIAL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm64_internal.h"
#include "arm64_gic.h"
#include "hardware/zynq_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM64_ZYNQ_MPSOC_ZYNQ_SERIAL_H */