diff --git a/arch/mips/src/pic32mz/Kconfig b/arch/mips/src/pic32mz/Kconfig index a451d895c4..437960f386 100644 --- a/arch/mips/src/pic32mz/Kconfig +++ b/arch/mips/src/pic32mz/Kconfig @@ -340,13 +340,14 @@ menu "Device Configuration 0 (DEVCFG0)" config PIC32MZ_DEBUGGER_ENABLE bool "Background debugger enable" - default n + default y if CONFIG_DEBUG + default n if !CONFIG_DEBUG ---help--- Background Debugger Enable config PIC32MZ_JTAG_ENABLE bool "JTAG enable" - default y + default n ---help--- JTAG Enable @@ -358,7 +359,8 @@ config PIC32MZ_ICESEL_CH2 config PIC32MZ_TRACE_ENABLE bool "Trace enable" - default n + default y if CONFIG_DEBUG + default n if !CONFIG_DEBUG ---help--- Trace Enable @@ -368,14 +370,22 @@ menu "Device Configuration 1 (DEVCFG1)" config CONFIG_PIC32MZ_OSCIOFNC int "CLKO Enable" - default 0 + default 1 range 0 1 + ---help--- + Enable CLK0 output on power up. Options: + + 1: CLKO output disabled + 0: CLKO output signal active on the OSC2 pin config PIC32MZ_WDTENABLE bool "Watchdog enable" default 0 ---help--- - Enabled watchdog on power up. Default 0 (watchdog can be enabled later by software). + Enabled watchdog on power up. + + 1: Watchdog enabled, cannot be disabled + 0: Watchdog disabled, can be enabled endmenu diff --git a/arch/mips/src/pic32mz/chip/pic32mzec-features.h b/arch/mips/src/pic32mz/chip/pic32mzec-features.h index 0ec30b3d66..7ff4100443 100644 --- a/arch/mips/src/pic32mz/chip/pic32mzec-features.h +++ b/arch/mips/src/pic32mz/chip/pic32mzec-features.h @@ -359,6 +359,8 @@ # define DEVCFG2_FPLLODIV_16 (4 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 16 */ # define DEVCFG2_FPLLODIV_32 (5 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 32 */ #define DEVCFG2_UPLLFSEL (1 << 30) /* Bit 30: USB PLL Input Frequency Select bit */ +# define DEVCFG2_UPLLFSEL_24MHZ (1 << 30) /* Bit 30=1: UPLL input clock is 24 MHz */ +# define DEVCFG2_UPLLFSEL_12MHZ (0 << 30) /* Bit 30=0: UPLL input clock is 12 MHz */ #define DEVCFG2_RWO 0xbff88008 /* Bits 3, 15, 19-29, 31: Reserved, write as one */ @@ -419,9 +421,15 @@ # define DEVCFG1_WDTPS_262144 (18 << DEVCFG1_WDTPS_SHIFT) /* 1:262144 */ # define DEVCFG1_WDTPS_524288 (19 << DEVCFG1_WDTPS_SHIFT) /* 1:524288 */ # define DEVCFG1_WDTPS_1048576 (20 << DEVCFG1_WDTPS_SHIFT) /* 1:1048576 */ -#define DEVCFG1_WDTSPGM (1 << 21) /* Bit 21: Watchdog Timer Stop During Flash Programming bit */ +#define DEVCFG1_WDTSPGM (1 << 21) /* Bit 21: WDT stop/run during flash programming bit */ +# define DEVCFG1_WDTSPGM_STOP (1 << 21) /* Bit 21=1: WDT stops during flash programming */ +# define DEVCFG1_WDTSPGM_RUN (0 << 21) /* Bit 21=0: WDT runs during flash programming */ #define DEVCFG1_WINDIS (1 << 22) /* Bit 22: Watchdog Timer Window Enable bit */ +# define DEVCFG1_WDT_NORMAL (1 << 22) /* Bit 22=1: Watchdog normal mode */ +# define DEVCFG1_WDT_WINDOW (0 << 22) /* Bit 22=0: Watchdog window mode */ #define DEVCFG1_FWDTEN (1 << 23) /* Bit 23: Watchdog Timer Enable bit */ +# define DEVCFG1_FWDT_ENABLED (1 << 23) /* Bit 23=1: Watchdog enabled, cannot be disabled */ +# define DEVCFG1_FWDT_DISABLED (0 << 23) /* Bit 23=0: Watchdog disabled, can be enabled */ #define DEVCFG1_FWDTWINSZ_SHIFT (24) /* Bits 24-25: Watchdog Timer Window Size bits */ #define DEVCFG1_FWDTWINSZ_MASK (3 << DEVCFG1_FWDTWINSZ_SHIFT) # define DEVCFG1_FWDTWINSZ_75 (0 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 75% */ @@ -448,6 +456,8 @@ # define DEVCFG0_ICESEL_2 (2 << DEVCFG0_ICESEL_SHIFT) /* PGEC2/PGED2 pair is used */ #define DEVCFG0_TRCEN (1 << 5) /* Bit 5: Trace Enable bit */ #define DEVCFG0_BOOTISA (1 << 6) /* Bit 6: Boot ISA Selection bit */ +# define DEVCFG0_BOOT_MIPS32 (1 << 6) /* Bit 6=1: Boot code and Exception code is MIPS32 */ +# define DEVCFG0_BOOT_MICROMIPS (0 << 6) /* Bit 6=0: Boot code and Exception code is microMIPS */ #define DEVCFG0_FECCCON_SHIFT (8) /* Bit 8-9: Dynamic Flash ECC Configuration bits */ #define DEVCFG0_FECCCON_MASK (3 << DEVCFG0_FECCCON_SHIFT) # define DEVCFG0_FECCCON_ECC (0 << DEVCFG0_FECCCON_SHIFT) /* Flash ECC enabled (locked) */ @@ -455,12 +465,17 @@ # define DEVCFG0_FECCCON_DISLCK (2 << DEVCFG0_FECCCON_SHIFT) /* ECC / dynamic ECC disabled (locked) */ # define DEVCFG0_FECCCON_DISWR (3 << DEVCFG0_FECCCON_SHIFT) /* ECC / dynamic ECC disabled (writable) */ #define DEVCFG0_FSLEEP (1 << 10) /* Bit 10: Flash Sleep Mode bit */ +# define DEVCFG0_FSLEEP_OFF (1 << 10) /* Bit 10=1: Flash powered down in sleep mode */ +# define DEVCFG0_FSLEEP_ON (0 << 10) /* Bit 10=0: Flash powerdown controlled by VREGS bit */ #define DEVCFG0_DBGPER_SHIFT (12) /* Bits 12-14: Debug Mode CPU Access Permission bits */ #define DEVCFG0_DBGPER_MASK (7 << DEVCFG0_DBGPER_SHIFT) # define DEVCFG0_DBGPER_GROUP0 (1 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 0 regions */ # define DEVCFG0_DBGPER_GROUP1 (2 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 1 regions */ # define DEVCFG0_DBGPER_GROUP2 (4 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 2 regions */ +# define DEVCFG0_DBGPER_ALL (7 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to all regions */ #define DEVCFG0_EJTAGBEN (1 << 30) /* Bit 30: EJTAG Boot Enable bit */ +# define DEVCFG0_EJTAG_NORMAL (1 << 30) /* Bit 30=1: Normal EJTAG functionality */ +# define DEVCFG0_EJTAG_REDUCED (0 << 30) /* Bit 30=0: Reduced EJTAG functionality */ #define DEVCFG0_RW0 0xbfff8880 /* Bits 7, 11, 15-29, 31: Reserved, write as one */ diff --git a/arch/mips/src/pic32mz/pic32mz-config.h b/arch/mips/src/pic32mz/pic32mz-config.h index bbbc383817..ab6c9ce746 100644 --- a/arch/mips/src/pic32mz/pic32mz-config.h +++ b/arch/mips/src/pic32mz/pic32mz-config.h @@ -152,6 +152,7 @@ #ifndef CONFIG_PIC32MZ_USERID /* User ID */ # define CONFIG_PIC32MZ_USERID 0x584e /* "NX" */ #endif +#define ADEVCFG3_USERID 0x1234 #ifndef CONFIG_PIC32MZ_FMIIEN /* Ethernet MII enable: 0=RMII 1=MII */ # define CONFIG_PIC32MZ_FMIIEN 1 /* MII enabled */ @@ -251,12 +252,17 @@ # error "Unsupported BOARD_PLL_ODIV" #endif +#if BOARD_POSC_FREQ == 12000000 +# define CONFIG_PIC32MZ_UPLLFSEL DEVCFG2_UPLLFSEL_12MHZ +#else +# define CONFIG_PIC32MZ_UPLLFSEL DEVCFG2_UPLLFSEL_24MHZ +#endif + /* Not yet configurable settings (REVISIT) */ /* System PLL Input Clock Select bit */ #define CONFIG_PIC32MZ_FPLLICLK 0 /* POSC is selected as input to the System PLL */ /* USB PLL Input Frequency Select bit */ -#define CONFIG_PIC32MZ_UPLLFSEL DEVCFG2_UPLLFSEL /* DEVCFG1 */ /* Configurable settings */ @@ -375,16 +381,17 @@ #undef CONFIG_PIC32MZ_FWDTEN #if CONFIG_PIC32MZ_WDTENABLE -# define CONFIG_PIC32MZ_FWDTEN DEVCFG1_FWDTEN +# define CONFIG_PIC32MZ_FWDTEN DEVCFG1_FWDT_ENSABLED #else -# define CONFIG_PIC32MZ_FWDTEN 0 +# define CONFIG_PIC32MZ_FWDTEN DEVCFG1_FWDT_DISABLED #endif +#define ADEVCFG1_FWDTEN DEVCFG1_FWDT_DISABLED /* Not yet configurable settings */ -#define CONFIG_PIC32MZ_DMTINV DEVCFG1_FNOSC_FRCDIV -#define CONFIG_PIC32MZ_WDTSPGM DEVCFG1_WDTSPGM -#define CONFIG_PIC32MZ_WINDIS DEVCFG1_WINDIS +#define CONFIG_PIC32MZ_DMTINV DEVCFG1_DMTINV_127_128 +#define CONFIG_PIC32MZ_WDTSPGM DEVCFG1_WDTSPGM_STOP +#define CONFIG_PIC32MZ_WINDIS DEVCFG1_WDT_NORMAL #define CONFIG_PIC32MZ_FWDTWINSZ DEVCFG1_FWDTWINSZ_25 #define CONFIG_PIC32MZ_DMTCNT DEVCFG1_DMTCNT_MASK #define CONFIG_PIC32MZ_FDMTEN 0 @@ -422,11 +429,11 @@ /* Not yet configurable settings */ -#define CONFIG_PIC32MZ_BOOTISA 0 /* microMIPS always */ +#define CONFIG_PIC32MZ_BOOTISA DEVCFG0_BOOT_MICROMIPS #define CONFIG_PIC32MZ_FECCCON DEVCFG0_FECCCON_DISWR -#define CONFIG_PIC32MZ_FSLEEP DEVCFG0_FSLEEP -#define CONFIG_PIC32MZ_DBGPER DEVCFG0_DBGPER_MASK -#define CONFIG_PIC32MZ_EJTAGBEN DEVCFG0_EJTAGBEN +#define CONFIG_PIC32MZ_FSLEEP DEVCFG0_FSLEEP_OFF +#define CONFIG_PIC32MZ_DBGPER DEVCFG0_DBGPER_ALL +#define CONFIG_PIC32MZ_EJTAGBEN DEVCFG0_EJTAG_NORMAL /************************************************************************************ * Public Types diff --git a/arch/mips/src/pic32mz/pic32mz-head.S b/arch/mips/src/pic32mz/pic32mz-head.S index 03418c6c6b..a7b04e1f9a 100644 --- a/arch/mips/src/pic32mz/pic32mz-head.S +++ b/arch/mips/src/pic32mz/pic32mz-head.S @@ -699,7 +699,7 @@ devcfg0: .type adevcfg, object adevcfg: adevcfg3: - .long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \ + .long ADEVCFG3_USERID << DEVCFG3_USERID_SHIFT | \ CONFIG_PIC32MZ_FMIIEN << DEVCFG3_FMIIEN_SHIFT | \ CONFIG_PIC32MZ_FETHIO << DEVCFG3_FETHIO_SHIFT | \ CONFIG_PIC32MZ_PGL1WAY << DEVCFG3_PGL1WAY_SHIFT | \ @@ -720,7 +720,7 @@ adevcfg1: CONFIG_PIC32MZ_POSCMOD | CONFIG_PIC32MZ_OSCIOFNC | \ CONFIG_PIC32MZ_FCKSM | CONFIG_PIC32MZ_WDTPS | \ CONFIG_PIC32MZ_WDTSPGM | CONFIG_PIC32MZ_WINDIS | \ - CONFIG_PIC32MZ_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \ + ADEVCFG1_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \ CONFIG_PIC32MZ_DMTCNT | CONFIG_PIC32MZ_FSOSCEN | \ CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_FDMTEN | \ DEVCFG1_RWO diff --git a/configs/pic32mz-starterkit/include/board.h b/configs/pic32mz-starterkit/include/board.h index eced370902..b5567ed7f5 100644 --- a/configs/pic32mz-starterkit/include/board.h +++ b/configs/pic32mz-starterkit/include/board.h @@ -61,6 +61,8 @@ #define BOARD_FNOSC_SPLL 1 /* Use system PLL */ #define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */ +#define BOARD_POSC_SWITCH 1 /* Enable clock switching */ +#undef BOARD_POSC_FSCM /* Disable clock monitoring */ /* PLL configuration and resulting CPU clock. * CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV @@ -143,7 +145,7 @@ /* Watchdog pre-scaler (re-visit) */ -#define BOARD_WD_PRESCALER 8 /* Watchdog pre-scaler */ +#define BOARD_WD_PRESCALER 1048576 /* Watchdog pre-scaler */ /* LED definitions **********************************************************/ /* LED Configuration ********************************************************/ diff --git a/configs/pic32mz-starterkit/nsh/defconfig b/configs/pic32mz-starterkit/nsh/defconfig index 4de30b1709..37ce95473c 100644 --- a/configs/pic32mz-starterkit/nsh/defconfig +++ b/configs/pic32mz-starterkit/nsh/defconfig @@ -152,14 +152,14 @@ CONFIG_PIC32MZ_UART1=y # Device Configuration 0 (DEVCFG0) # # CONFIG_PIC32MZ_DEBUGGER_ENABLE is not set -CONFIG_PIC32MZ_JTAG_ENABLE=y -# CONFIG_PIC32MZ_ICESEL_CH2 is not set +# CONFIG_PIC32MZ_JTAG_ENABLE is not set +CONFIG_PIC32MZ_ICESEL_CH2=y # CONFIG_PIC32MZ_TRACE_ENABLE is not set # # Device Configuration 1 (DEVCFG1) # -CONFIG_CONFIG_PIC32MZ_OSCIOFNC=0 +CONFIG_CONFIG_PIC32MZ_OSCIOFNC=1 # CONFIG_PIC32MZ_WDTENABLE is not set # @@ -683,7 +683,6 @@ CONFIG_EXAMPLES_NSH=y # # CONFIG_NETUTILS_CODECS is not set # CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_FTPD is not set # CONFIG_NETUTILS_JSON is not set # CONFIG_NETUTILS_SMTP is not set # CONFIG_NETUTILS_TFTPC is not set