Finishes the PWM driver for the STM32
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4206 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -1237,7 +1237,8 @@ configs/ez80f0910200zco
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tools. The development environment is Cygwin under WinXP.
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configs/hymini-stm32v
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A configuration for the HY-Mini STM32v board.
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A configuration for the HY-Mini STM32v board. This board is based on the
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STM32F103VCT chip.
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configs/kwikstik-k40.
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Kinetis K40 Cortex-M4 MCU. This port uses the FreeScale KwikStik-K40
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@ -1249,7 +1250,7 @@ configs/lm3s6965-ek
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arm-elf toolchain*. STATUS: This port is complete and mature.
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configs/lm3s8962-ek
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Stellaris LMS38962 Evaluation Kit
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Stellaris LMS38962 Evaluation Kit.
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configs/lpcxpresso-lpc1768
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Embedded Artists base board with NXP LPCExpresso LPC1768. This board
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@ -1380,6 +1381,11 @@ configs/stm3210e-evel
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microcontroller (ARM Cortex-M3). This port uses the GNU Cortex-M3
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toolchain.
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configs/stm32140g-eval
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STMicro STM3210G-EVAL development board based on the STMicro STM32F103ZET6
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microcontroller (ARM Cortex-M4 with FPU). This port uses a GNU Cortex-M4
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toolchain (such as CodeSourcery).
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configs/sure-pic32mx
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The "Advanced USB Storage Demo Board," Model DB-DP11215, from Sure
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Electronics (http://www.sureelectronics.net/). This board features
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@ -88,11 +88,25 @@
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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/* APB2 timers 1 and 8 will receive PCLK2. */
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#define STM32_APB1_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB1 timers 2-4 will be twice PCLK1 (I presume the remaining will receive PCLK1) */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
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/* USB divider -- Divide PLL clock by 1.5 */
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#define STM32_CFGR_USBPRE 0
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@ -82,12 +82,27 @@
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */
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/* APB2 timers 1 and 8 will receive PCLK2. */
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#define STM32_APB1_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB1 timers 2-4 will be twice PCLK1 (I presume the remaining will receive PCLK1) */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
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/* USB divider -- Divide PLL clock by 1.5 */
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#define STM32_CFGR_USBPRE 0
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@ -14,6 +14,7 @@ Contents
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- STM3240G-EVAL-specific Configuration Options
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- LEDs
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- Ethernet
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- PWM
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- Configurations
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Development Environment
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@ -203,6 +204,21 @@ events as follows:
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on a small proportion of the time.
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*** LED2 may also flicker normally if signals are processed.
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PWM
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===
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The STM3240G-Eval has no real on-board PWM devices, but the board can be configured to output
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a pulse train using TIM4 CH2. This pin is used by FSMC is connect to CN5 just for this
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purpose:
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PD13 FSMC_A18 / MC_TIM4_CH2 pin 33 (EnB)
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FSMC must be disabled in this case! PD13 is available at:
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Daughterboard Extension Connector, CN3, pin 32 - available
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TFT LCD Connector, CN19, pin 17 -- not available without removing the LCD.
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Motor Control Connector CN15, pin 33 -- no available unless to connect SB14.
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STM3240G-EVAL-specific Configuration Options
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============================================
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@ -126,14 +126,34 @@
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/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB12will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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@ -97,11 +97,25 @@
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_BOARD_HCLK
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/* APB2 timers 1 and 8 will receive PCLK2. */
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#define STM32_APB1_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB1 clock (PCLK1) is HCLK (36MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
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#define STM32_PCLK1_FREQUENCY STM32_BOARD_HCLK
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/* APB1 timers 2-4 will receive PCLK1. */
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#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
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/* Timer 1..8 Frequencies */
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#define STM32_TIM27_FREQUENCY (STM32_BOARD_HCLK)
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