Fix wrong comment style
This commit is contained in:
Peter van der Perk
Xiang Xiao
parent
b3590f00b3
commit
eae3f77673
@ -107,139 +107,139 @@
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/** edma_mux0 **/
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#define DMA_REQ_DISABLED0 (0) ///< Channel disabled (default)
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#define DMA_REQ_SIUL_0 (1) ///< SIUL DMA request 0
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#define DMA_REQ_SIUL_1 (2) ///< SIUL DMA request 1
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#define DMA_REQ_SIUL_2 (3) ///< SIUL DMA request 2
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#define DMA_REQ_SIUL_3 (4) ///< SIUL DMA request 3
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#define DMA_REQ_SIUL_4 (5) ///< SIUL DMA request 4
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#define DMA_REQ_SIUL_5 (6) ///< SIUL DMA request 5
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#define DMA_REQ_SIUL_6 (7) ///< SIUL DMA request 6
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#define DMA_REQ_SIUL_7 (8) ///< SIUL DMA request 7
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#define DMA_REQ_BCTU_FIFO1 (10) ///< BCTU DMA FIFO1 request
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#define DMA_REQ_BCTU_0 (10) ///< BCTU DMA request 0
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#define DMA_REQ_BCTU_1 (11) ///< BCTU DMA request 1
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#define DMA_REQ_EMIOS0_0 (12) ///< eMIOS0 DMA request ch0
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#define DMA_REQ_EMIOS0_1 (13) ///< eMIOS0 DMA request ch1
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#define DMA_REQ_EMIOS0_9 (14) ///< eMIOS0 DMA request ch9
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#define DMA_REQ_EMIOS0_10 (15) ///< eMIOS0 DMA request ch10
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#define DMA_REQ_EMIOS1_0 (16) ///< eMIOS1 DMA request ch0
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#define DMA_REQ_EMIOS1_1 (17) ///< eMIOS1 DMA request ch1
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#define DMA_REQ_EMIOS1_9 (18) ///< eMIOS1 DMA request ch9
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#define DMA_REQ_EMIOS1_10 (19) ///< eMIOS1 DMA request ch10
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#define DMA_REQ_EMIOS2_0 (20) ///< eMIOS2 DMA request ch0
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#define DMA_REQ_EMIOS2_1 (21) ///< eMIOS2 DMA request ch1
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#define DMA_REQ_EMIOS2_9 (22) ///< eMIOS2 DMA request ch9
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#define DMA_REQ_EMIOS2_10 (23) ///< eMIOS2 DMA request ch10
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#define DMA_REQ_LCU0_0 (24) ///< LCU0 DMA request 0
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#define DMA_REQ_LCU1_0 (25) ///< LCU1 DMA request 0
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#define DMA_REQ_RESERVED1 (26) ///< RESERVED
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#define DMA_REQ_RESERVED2 (27) ///< RESERVED
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#define DMA_REQ_RESERVED3 (28) ///< RESERVED
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#define DMA_REQ_FLEXCAN0 (29) ///< FLEXCAN0 DMA request
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#define DMA_REQ_FLEXCAN1 (30) ///< FLEXCAN1 DMA request
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#define DMA_REQ_FLEXCAN2 (31) ///< FLEXCAN2 DMA request
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#define DMA_REQ_FLEXCAN3 (32) ///< FLEXCAN3 DMA request
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#define DMA_REQ_FLEXIO_0 (33) ///< FLEXIO DMA shifter0 | timer0 request
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#define DMA_REQ_FLEXIO_1 (34) ///< FLEXIO DMA shifter1 | timer1 request
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#define DMA_REQ_FLEXIO_2 (35) ///< FLEXIO DMA shifter2 | timer2 request
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#define DMA_REQ_FLEXIO_3 (36) ///< FLEXIO DMA shifter3 | timer3 request
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#define DMA_REQ_LPUART08_TX (37) ///< LPUART0 | LPUART8 DMA transmit request
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#define DMA_REQ_LPUART08_RX (38) ///< LPUART0 | LPUART8 DMA receive request
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#define DMA_REQ_LPUART19_TX (39) ///< LPUART1 | LPUART9 DMA transmit request
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#define DMA_REQ_LPUART19_RX (40) ///< LPUART1 | LPUART9 DMA receive request
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#define DMA_REQ_LPI2C0_RX (41) ///< LPI2C0 DMA receive | receive slave request
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#define DMA_REQ_LPI2C0_TX (42) ///< LPI2C0 DMA transmit | transmit slave request
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#define DMA_REQ_LPSPI0_TX (43) ///< LPSPI0 DMA transmit request
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#define DMA_REQ_LPSPI0_RX (44) ///< LPSPI0 DMA receive request
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#define DMA_REQ_LPSPI1_TX (45) ///< LPSPI1 DMA transmit request
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#define DMA_REQ_LPSPI1_RX (46) ///< LPSPI1 DMA receive request
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#define DMA_REQ_LPSPI2_TX (47) ///< LPSPI2 DMA transmit request
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#define DMA_REQ_LPSPI2_RX (48) ///< LPSPI2 DMA receive request
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#define DMA_REQ_LPSPI3_TX (49) ///< LPSPI3 DMA transmit request
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#define DMA_REQ_LPSPI3_RX (50) ///< LPSPI3 DMA receive request
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#define DMA_REQ_I3C0_RX (51) ///< I3C0 DMA receive request
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#define DMA_REQ_I3C0_TX (52) ///< I3C0 DMA transmit request
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#define DMA_REQ_QSPI_RX (53) ///< QSPI DMA receive buffer drain request
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#define DMA_REQ_QSPI_TX (54) ///< QSPI DMA transmit buffer fill request
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#define DMA_REQ_SAI0_RX (55) ///< SAI0 DMA receive request
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#define DMA_REQ_SAI0_TX (56) ///< SAI0 DMA transmit request
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#define DMA_REQ_RESERVED4 (57) ///< RESERVED
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#define DMA_REQ_ADC0 (58) ///< ADC0 DMA request
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#define DMA_REQ_ADC1 (59) ///< ADC1 DMA request
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#define DMA_REQ_ADC2 (60) ///< ADC2 DMA request
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#define DMA_REQ_LPCMP0 (61) ///< LPCMP0 DMA request
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#define DMA_REQ_ENABLED0 (62) ///< Always enabled
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#define DMA_REQ_ENABLED1 (63) ///< Always enabled */
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#define DMA_REQ_DISABLED0 (0) /* Channel disabled (default) */
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#define DMA_REQ_SIUL_0 (1) /* SIUL DMA request 0 */
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#define DMA_REQ_SIUL_1 (2) /* SIUL DMA request 1 */
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#define DMA_REQ_SIUL_2 (3) /* SIUL DMA request 2 */
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#define DMA_REQ_SIUL_3 (4) /* SIUL DMA request 3 */
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#define DMA_REQ_SIUL_4 (5) /* SIUL DMA request 4 */
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#define DMA_REQ_SIUL_5 (6) /* SIUL DMA request 5 */
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#define DMA_REQ_SIUL_6 (7) /* SIUL DMA request 6 */
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#define DMA_REQ_SIUL_7 (8) /* SIUL DMA request 7 */
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#define DMA_REQ_BCTU_FIFO1 (10) /* BCTU DMA FIFO1 request */
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#define DMA_REQ_BCTU_0 (10) /* BCTU DMA request 0 */
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#define DMA_REQ_BCTU_1 (11) /* BCTU DMA request 1 */
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#define DMA_REQ_EMIOS0_0 (12) /* eMIOS0 DMA request ch0 */
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#define DMA_REQ_EMIOS0_1 (13) /* eMIOS0 DMA request ch1 */
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#define DMA_REQ_EMIOS0_9 (14) /* eMIOS0 DMA request ch9 */
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#define DMA_REQ_EMIOS0_10 (15) /* eMIOS0 DMA request ch10 */
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#define DMA_REQ_EMIOS1_0 (16) /* eMIOS1 DMA request ch0 */
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#define DMA_REQ_EMIOS1_1 (17) /* eMIOS1 DMA request ch1 */
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#define DMA_REQ_EMIOS1_9 (18) /* eMIOS1 DMA request ch9 */
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#define DMA_REQ_EMIOS1_10 (19) /* eMIOS1 DMA request ch10 */
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#define DMA_REQ_EMIOS2_0 (20) /* eMIOS2 DMA request ch0 */
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#define DMA_REQ_EMIOS2_1 (21) /* eMIOS2 DMA request ch1 */
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#define DMA_REQ_EMIOS2_9 (22) /* eMIOS2 DMA request ch9 */
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#define DMA_REQ_EMIOS2_10 (23) /* eMIOS2 DMA request ch10 */
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#define DMA_REQ_LCU0_0 (24) /* LCU0 DMA request 0 */
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#define DMA_REQ_LCU1_0 (25) /* LCU1 DMA request 0 */
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#define DMA_REQ_RESERVED1 (26) /* RESERVED */
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#define DMA_REQ_RESERVED2 (27) /* RESERVED */
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#define DMA_REQ_RESERVED3 (28) /* RESERVED */
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#define DMA_REQ_FLEXCAN0 (29) /* FLEXCAN0 DMA request */
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#define DMA_REQ_FLEXCAN1 (30) /* FLEXCAN1 DMA request */
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#define DMA_REQ_FLEXCAN2 (31) /* FLEXCAN2 DMA request */
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#define DMA_REQ_FLEXCAN3 (32) /* FLEXCAN3 DMA request */
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#define DMA_REQ_FLEXIO_0 (33) /* FLEXIO DMA shifter0 | timer0 request */
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#define DMA_REQ_FLEXIO_1 (34) /* FLEXIO DMA shifter1 | timer1 request */
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#define DMA_REQ_FLEXIO_2 (35) /* FLEXIO DMA shifter2 | timer2 request */
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#define DMA_REQ_FLEXIO_3 (36) /* FLEXIO DMA shifter3 | timer3 request */
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#define DMA_REQ_LPUART08_TX (37) /* LPUART0 | LPUART8 DMA transmit request */
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#define DMA_REQ_LPUART08_RX (38) /* LPUART0 | LPUART8 DMA receive request */
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#define DMA_REQ_LPUART19_TX (39) /* LPUART1 | LPUART9 DMA transmit request */
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#define DMA_REQ_LPUART19_RX (40) /* LPUART1 | LPUART9 DMA receive request */
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#define DMA_REQ_LPI2C0_RX (41) /* LPI2C0 DMA receive | receive slave request */
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#define DMA_REQ_LPI2C0_TX (42) /* LPI2C0 DMA transmit | transmit slave request */
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#define DMA_REQ_LPSPI0_TX (43) /* LPSPI0 DMA transmit request */
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#define DMA_REQ_LPSPI0_RX (44) /* LPSPI0 DMA receive request */
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#define DMA_REQ_LPSPI1_TX (45) /* LPSPI1 DMA transmit request */
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#define DMA_REQ_LPSPI1_RX (46) /* LPSPI1 DMA receive request */
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#define DMA_REQ_LPSPI2_TX (47) /* LPSPI2 DMA transmit request */
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#define DMA_REQ_LPSPI2_RX (48) /* LPSPI2 DMA receive request */
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#define DMA_REQ_LPSPI3_TX (49) /* LPSPI3 DMA transmit request */
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#define DMA_REQ_LPSPI3_RX (50) /* LPSPI3 DMA receive request */
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#define DMA_REQ_I3C0_RX (51) /* I3C0 DMA receive request */
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#define DMA_REQ_I3C0_TX (52) /* I3C0 DMA transmit request */
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#define DMA_REQ_QSPI_RX (53) /* QSPI DMA receive buffer drain request */
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#define DMA_REQ_QSPI_TX (54) /* QSPI DMA transmit buffer fill request */
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#define DMA_REQ_SAI0_RX (55) /* SAI0 DMA receive request */
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#define DMA_REQ_SAI0_TX (56) /* SAI0 DMA transmit request */
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#define DMA_REQ_RESERVED4 (57) /* RESERVED */
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#define DMA_REQ_ADC0 (58) /* ADC0 DMA request */
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#define DMA_REQ_ADC1 (59) /* ADC1 DMA request */
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#define DMA_REQ_ADC2 (60) /* ADC2 DMA request */
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#define DMA_REQ_LPCMP0 (61) /* LPCMP0 DMA request */
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#define DMA_REQ_ENABLED0 (62) /* Always enabled */
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#define DMA_REQ_ENABLED1 (63) /* Always enabled */
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/** edma_mux1 **/
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#define DMA_REQ_DISABLED1 (DMAMUX_CHCFG_DMAMUX1 | 0) ///< Channel disabled (default)
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#define DMA_REQ_SIUL_8 (DMAMUX_CHCFG_DMAMUX1 | 1) ///< SIUL DMA request 8
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#define DMA_REQ_SIUL_9 (DMAMUX_CHCFG_DMAMUX1 | 2) ///< SIUL DMA request 9
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#define DMA_REQ_SIUL_10 (DMAMUX_CHCFG_DMAMUX1 | 3) ///< SIUL DMA request 10
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#define DMA_REQ_SIUL_11 (DMAMUX_CHCFG_DMAMUX1 | 4) ///< SIUL DMA request 11
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#define DMA_REQ_SIUL_12 (DMAMUX_CHCFG_DMAMUX1 | 5) ///< SIUL DMA request 12
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#define DMA_REQ_SIUL_13 (DMAMUX_CHCFG_DMAMUX1 | 6) ///< SIUL DMA request 13
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#define DMA_REQ_SIUL_14 (DMAMUX_CHCFG_DMAMUX1 | 7) ///< SIUL DMA request 14
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#define DMA_REQ_SIUL_15 (DMAMUX_CHCFG_DMAMUX1 | 8) ///< SIUL DMA request 15
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#define DMA_REQ_BCTU_FIFO2 (DMAMUX_CHCFG_DMAMUX1 | 9) ///< BCTU DMA FIFO2 request
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#define DMA_REQ_BCTU_2 (DMAMUX_CHCFG_DMAMUX1 | 10) ///< BCTU DMA request 2
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#define DMA_REQ_EMIOS0_16 (DMAMUX_CHCFG_DMAMUX1 | 11) ///< eMIOS0 DMA request ch16
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#define DMA_REQ_EMIOS0_17 (DMAMUX_CHCFG_DMAMUX1 | 12) ///< eMIOS0 DMA request ch17
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#define DMA_REQ_EMIOS0_18 (DMAMUX_CHCFG_DMAMUX1 | 13) ///< eMIOS0 DMA request ch18
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#define DMA_REQ_EMIOS0_19 (DMAMUX_CHCFG_DMAMUX1 | 14) ///< eMIOS0 DMA request ch19
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#define DMA_REQ_EMIOS1_16 (DMAMUX_CHCFG_DMAMUX1 | 15) ///< eMIOS1 DMA request ch16
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#define DMA_REQ_EMIOS1_17 (DMAMUX_CHCFG_DMAMUX1 | 16) ///< eMIOS1 DMA request ch17
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#define DMA_REQ_EMIOS1_18 (DMAMUX_CHCFG_DMAMUX1 | 17) ///< eMIOS1 DMA request ch18
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#define DMA_REQ_EMIOS1_19 (DMAMUX_CHCFG_DMAMUX1 | 18) ///< eMIOS1 DMA request ch19
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#define DMA_REQ_EMIOS2_16 (DMAMUX_CHCFG_DMAMUX1 | 19) ///< eMIOS2 DMA request ch16
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#define DMA_REQ_EMIOS2_17 (DMAMUX_CHCFG_DMAMUX1 | 20) ///< eMIOS2 DMA request ch17
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#define DMA_REQ_EMIOS2_18 (DMAMUX_CHCFG_DMAMUX1 | 21) ///< eMIOS2 DMA request ch18
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#define DMA_REQ_EMIOS2_19 (DMAMUX_CHCFG_DMAMUX1 | 22) ///< eMIOS2 DMA request ch19
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#define DMA_REQ_LCU0_1 (DMAMUX_CHCFG_DMAMUX1 | 23) ///< LCU0 DMA request 1
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#define DMA_REQ_LCU0_2 (DMAMUX_CHCFG_DMAMUX1 | 24) ///< LCU1 DMA request 2
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#define DMA_REQ_LCU1_1 (DMAMUX_CHCFG_DMAMUX1 | 25) ///< LCU1 DMA request 1
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#define DMA_REQ_LCU1_2 (DMAMUX_CHCFG_DMAMUX1 | 26) ///< LCU1 DMA request 2
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#define DMA_REQ_ENET_0 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[0] DMA request
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#define DMA_REQ_ENET_1 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[1] DMA request
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#define DMA_REQ_ENET_2 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[2] DMA request
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#define DMA_REQ_ENET_3 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[3] DMA request
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#define DMA_REQ_RESERVED5 (DMAMUX_CHCFG_DMAMUX1 | 28) ///< RESERVED
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#define DMA_REQ_RESERVED6 (DMAMUX_CHCFG_DMAMUX1 | 29) ///< RESERVED
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#define DMA_REQ_FLECAN4 (DMAMUX_CHCFG_DMAMUX1 | 30) ///< FLEXCAN4 DMA request
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#define DMA_REQ_FLECAN5 (DMAMUX_CHCFG_DMAMUX1 | 31) ///< FLEXCAN5 DMA request
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#define DMA_REQ_RESERVED7 (DMAMUX_CHCFG_DMAMUX1 | 32) ///< RESERVED
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#define DMA_REQ_RESERVED8 (DMAMUX_CHCFG_DMAMUX1 | 33) ///< RESERVED
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#define DMA_REQ_FLEXIO_4 (DMAMUX_CHCFG_DMAMUX1 | 34) ///< FLEXIO DMA shifter4 | timer4 request
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#define DMA_REQ_FLEXIO_5 (DMAMUX_CHCFG_DMAMUX1 | 35) ///< FLEXIO DMA shifter5 | timer5 request
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#define DMA_REQ_FLEXIO_6 (DMAMUX_CHCFG_DMAMUX1 | 36) ///< FLEXIO DMA shifter6 | timer6 request
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#define DMA_REQ_FLEXIO_7 (DMAMUX_CHCFG_DMAMUX1 | 37) ///< FLEXIO DMA shifter7 | timer7 request
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#define DMA_REQ_LPUART210_TX (DMAMUX_CHCFG_DMAMUX1 | 38) ///< LPUART2 | LPUART10 DMA transmit request
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#define DMA_REQ_LPUART210_RX (DMAMUX_CHCFG_DMAMUX1 | 39) ///< LPUART2 | LPUART10 DMA receive request
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#define DMA_REQ_LPUART311_TX (DMAMUX_CHCFG_DMAMUX1 | 40) ///< LPUART3 | LPUART11 DMA transmit request
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#define DMA_REQ_LPUART311_RX (DMAMUX_CHCFG_DMAMUX1 | 41) ///< LPUART3 | LPUART11 DMA receive request
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#define DMA_REQ_LPUART412_TX (DMAMUX_CHCFG_DMAMUX1 | 42) ///< LPUART4 | LPUART12 DMA transmit request
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#define DMA_REQ_LPUART412_RX (DMAMUX_CHCFG_DMAMUX1 | 43) ///< LPUART4 | LPUART12 DMA receive request
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#define DMA_REQ_LPUART513_TX (DMAMUX_CHCFG_DMAMUX1 | 44) ///< LPUART5 | LPUART13 DMA transmit request
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#define DMA_REQ_LPUART513_RX (DMAMUX_CHCFG_DMAMUX1 | 45) ///< LPUART5 | LPUART13 DMA receive request
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#define DMA_REQ_LPUART614_TX (DMAMUX_CHCFG_DMAMUX1 | 46) ///< LPUART6 | LPUART14 DMA transmit request
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#define DMA_REQ_LPUART614_RX (DMAMUX_CHCFG_DMAMUX1 | 47) ///< LPUART6 | LPUART14 DMA receive request
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#define DMA_REQ_LPUART715_TX (DMAMUX_CHCFG_DMAMUX1 | 48) ///< LPUART7 | LPUART15 DMA transmit request
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#define DMA_REQ_LPUART715_RX (DMAMUX_CHCFG_DMAMUX1 | 49) ///< LPUART7 | LPUART15 DMA receive request
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#define DMA_REQ_LPI2C1_RX (DMAMUX_CHCFG_DMAMUX1 | 50) ///< LPI2C1 DMA receive | receive slave request
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#define DMA_REQ_LPI2C1_TX (DMAMUX_CHCFG_DMAMUX1 | 51) ///< LPI2C1 DMA transmit | transmit slave request
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#define DMA_REQ_LPSPI4_TX (DMAMUX_CHCFG_DMAMUX1 | 52) ///< LPSPI4 DMA transmit request
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#define DMA_REQ_LPSPI4_RX (DMAMUX_CHCFG_DMAMUX1 | 53) ///< LPSPI4 DMA receive request
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#define DMA_REQ_LPSPI5_TX (DMAMUX_CHCFG_DMAMUX1 | 54) ///< LPSPI5 DMA transmit request
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#define DMA_REQ_LPSPI5_RX (DMAMUX_CHCFG_DMAMUX1 | 55) ///< LPSPI5 DMA receive request
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#define DMA_REQ_SAI1_RX (DMAMUX_CHCFG_DMAMUX1 | 56) ///< SAI1 DMA RX request
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#define DMA_REQ_SAI1_TX (DMAMUX_CHCFG_DMAMUX1 | 57) ///< SAI1 DMA TX request
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#define DMA_REQ_RESERVED9 (DMAMUX_CHCFG_DMAMUX1 | 58) ///< RESERVED
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#define DMA_REQ_RESERVED10 (DMAMUX_CHCFG_DMAMUX1 | 59) ///< RESERVED
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#define DMA_REQ_LPCMP1 (DMAMUX_CHCFG_DMAMUX1 | 60) ///< LPCMP1 DMA request
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#define DMA_REQ_LPCMP2 (DMAMUX_CHCFG_DMAMUX1 | 61) ///< LPCMP2 DMA request
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#define DMA_REQ_ENABLED2 (DMAMUX_CHCFG_DMAMUX1 | 62) ///< Always enabled
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#define DMA_REQ_ENABLED3 (DMAMUX_CHCFG_DMAMUX1 | 63) ///< Always enabled
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#define DMA_REQ_DISABLED1 (DMAMUX_CHCFG_DMAMUX1 | 0) /* Channel disabled (default) */
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#define DMA_REQ_SIUL_8 (DMAMUX_CHCFG_DMAMUX1 | 1) /* SIUL DMA request 8 */
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#define DMA_REQ_SIUL_9 (DMAMUX_CHCFG_DMAMUX1 | 2) /* SIUL DMA request 9 */
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#define DMA_REQ_SIUL_10 (DMAMUX_CHCFG_DMAMUX1 | 3) /* SIUL DMA request 10 */
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#define DMA_REQ_SIUL_11 (DMAMUX_CHCFG_DMAMUX1 | 4) /* SIUL DMA request 11 */
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#define DMA_REQ_SIUL_12 (DMAMUX_CHCFG_DMAMUX1 | 5) /* SIUL DMA request 12 */
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#define DMA_REQ_SIUL_13 (DMAMUX_CHCFG_DMAMUX1 | 6) /* SIUL DMA request 13 */
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#define DMA_REQ_SIUL_14 (DMAMUX_CHCFG_DMAMUX1 | 7) /* SIUL DMA request 14 */
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#define DMA_REQ_SIUL_15 (DMAMUX_CHCFG_DMAMUX1 | 8) /* SIUL DMA request 15 */
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#define DMA_REQ_BCTU_FIFO2 (DMAMUX_CHCFG_DMAMUX1 | 9) /* BCTU DMA FIFO2 request */
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#define DMA_REQ_BCTU_2 (DMAMUX_CHCFG_DMAMUX1 | 10) /* BCTU DMA request 2 */
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#define DMA_REQ_EMIOS0_16 (DMAMUX_CHCFG_DMAMUX1 | 11) /* eMIOS0 DMA request ch16 */
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#define DMA_REQ_EMIOS0_17 (DMAMUX_CHCFG_DMAMUX1 | 12) /* eMIOS0 DMA request ch17 */
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#define DMA_REQ_EMIOS0_18 (DMAMUX_CHCFG_DMAMUX1 | 13) /* eMIOS0 DMA request ch18 */
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#define DMA_REQ_EMIOS0_19 (DMAMUX_CHCFG_DMAMUX1 | 14) /* eMIOS0 DMA request ch19 */
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#define DMA_REQ_EMIOS1_16 (DMAMUX_CHCFG_DMAMUX1 | 15) /* eMIOS1 DMA request ch16 */
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#define DMA_REQ_EMIOS1_17 (DMAMUX_CHCFG_DMAMUX1 | 16) /* eMIOS1 DMA request ch17 */
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#define DMA_REQ_EMIOS1_18 (DMAMUX_CHCFG_DMAMUX1 | 17) /* eMIOS1 DMA request ch18 */
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#define DMA_REQ_EMIOS1_19 (DMAMUX_CHCFG_DMAMUX1 | 18) /* eMIOS1 DMA request ch19 */
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#define DMA_REQ_EMIOS2_16 (DMAMUX_CHCFG_DMAMUX1 | 19) /* eMIOS2 DMA request ch16 */
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#define DMA_REQ_EMIOS2_17 (DMAMUX_CHCFG_DMAMUX1 | 20) /* eMIOS2 DMA request ch17 */
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#define DMA_REQ_EMIOS2_18 (DMAMUX_CHCFG_DMAMUX1 | 21) /* eMIOS2 DMA request ch18 */
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#define DMA_REQ_EMIOS2_19 (DMAMUX_CHCFG_DMAMUX1 | 22) /* eMIOS2 DMA request ch19 */
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#define DMA_REQ_LCU0_1 (DMAMUX_CHCFG_DMAMUX1 | 23) /* LCU0 DMA request 1 */
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#define DMA_REQ_LCU0_2 (DMAMUX_CHCFG_DMAMUX1 | 24) /* LCU1 DMA request 2 */
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#define DMA_REQ_LCU1_1 (DMAMUX_CHCFG_DMAMUX1 | 25) /* LCU1 DMA request 1 */
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#define DMA_REQ_LCU1_2 (DMAMUX_CHCFG_DMAMUX1 | 26) /* LCU1 DMA request 2 */
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#define DMA_REQ_ENET_0 (DMAMUX_CHCFG_DMAMUX1 | 27) /* ENET IEEE 1588 PTP timer ch[0] DMA request */
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#define DMA_REQ_ENET_1 (DMAMUX_CHCFG_DMAMUX1 | 27) /* ENET IEEE 1588 PTP timer ch[1] DMA request */
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#define DMA_REQ_ENET_2 (DMAMUX_CHCFG_DMAMUX1 | 27) /* ENET IEEE 1588 PTP timer ch[2] DMA request */
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#define DMA_REQ_ENET_3 (DMAMUX_CHCFG_DMAMUX1 | 27) /* ENET IEEE 1588 PTP timer ch[3] DMA request */
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#define DMA_REQ_RESERVED5 (DMAMUX_CHCFG_DMAMUX1 | 28) /* RESERVED */
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#define DMA_REQ_RESERVED6 (DMAMUX_CHCFG_DMAMUX1 | 29) /* RESERVED */
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#define DMA_REQ_FLECAN4 (DMAMUX_CHCFG_DMAMUX1 | 30) /* FLEXCAN4 DMA request */
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#define DMA_REQ_FLECAN5 (DMAMUX_CHCFG_DMAMUX1 | 31) /* FLEXCAN5 DMA request */
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#define DMA_REQ_RESERVED7 (DMAMUX_CHCFG_DMAMUX1 | 32) /* RESERVED */
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#define DMA_REQ_RESERVED8 (DMAMUX_CHCFG_DMAMUX1 | 33) /* RESERVED */
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#define DMA_REQ_FLEXIO_4 (DMAMUX_CHCFG_DMAMUX1 | 34) /* FLEXIO DMA shifter4 | timer4 request */
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||||
#define DMA_REQ_FLEXIO_5 (DMAMUX_CHCFG_DMAMUX1 | 35) /* FLEXIO DMA shifter5 | timer5 request */
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||||
#define DMA_REQ_FLEXIO_6 (DMAMUX_CHCFG_DMAMUX1 | 36) /* FLEXIO DMA shifter6 | timer6 request */
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||||
#define DMA_REQ_FLEXIO_7 (DMAMUX_CHCFG_DMAMUX1 | 37) /* FLEXIO DMA shifter7 | timer7 request */
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||||
#define DMA_REQ_LPUART210_TX (DMAMUX_CHCFG_DMAMUX1 | 38) /* LPUART2 | LPUART10 DMA transmit request */
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#define DMA_REQ_LPUART210_RX (DMAMUX_CHCFG_DMAMUX1 | 39) /* LPUART2 | LPUART10 DMA receive request */
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||||
#define DMA_REQ_LPUART311_TX (DMAMUX_CHCFG_DMAMUX1 | 40) /* LPUART3 | LPUART11 DMA transmit request */
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||||
#define DMA_REQ_LPUART311_RX (DMAMUX_CHCFG_DMAMUX1 | 41) /* LPUART3 | LPUART11 DMA receive request */
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||||
#define DMA_REQ_LPUART412_TX (DMAMUX_CHCFG_DMAMUX1 | 42) /* LPUART4 | LPUART12 DMA transmit request */
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||||
#define DMA_REQ_LPUART412_RX (DMAMUX_CHCFG_DMAMUX1 | 43) /* LPUART4 | LPUART12 DMA receive request */
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||||
#define DMA_REQ_LPUART513_TX (DMAMUX_CHCFG_DMAMUX1 | 44) /* LPUART5 | LPUART13 DMA transmit request */
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||||
#define DMA_REQ_LPUART513_RX (DMAMUX_CHCFG_DMAMUX1 | 45) /* LPUART5 | LPUART13 DMA receive request */
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||||
#define DMA_REQ_LPUART614_TX (DMAMUX_CHCFG_DMAMUX1 | 46) /* LPUART6 | LPUART14 DMA transmit request */
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||||
#define DMA_REQ_LPUART614_RX (DMAMUX_CHCFG_DMAMUX1 | 47) /* LPUART6 | LPUART14 DMA receive request */
|
||||
#define DMA_REQ_LPUART715_TX (DMAMUX_CHCFG_DMAMUX1 | 48) /* LPUART7 | LPUART15 DMA transmit request */
|
||||
#define DMA_REQ_LPUART715_RX (DMAMUX_CHCFG_DMAMUX1 | 49) /* LPUART7 | LPUART15 DMA receive request */
|
||||
#define DMA_REQ_LPI2C1_RX (DMAMUX_CHCFG_DMAMUX1 | 50) /* LPI2C1 DMA receive | receive slave request */
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||||
#define DMA_REQ_LPI2C1_TX (DMAMUX_CHCFG_DMAMUX1 | 51) /* LPI2C1 DMA transmit | transmit slave request */
|
||||
#define DMA_REQ_LPSPI4_TX (DMAMUX_CHCFG_DMAMUX1 | 52) /* LPSPI4 DMA transmit request */
|
||||
#define DMA_REQ_LPSPI4_RX (DMAMUX_CHCFG_DMAMUX1 | 53) /* LPSPI4 DMA receive request */
|
||||
#define DMA_REQ_LPSPI5_TX (DMAMUX_CHCFG_DMAMUX1 | 54) /* LPSPI5 DMA transmit request */
|
||||
#define DMA_REQ_LPSPI5_RX (DMAMUX_CHCFG_DMAMUX1 | 55) /* LPSPI5 DMA receive request */
|
||||
#define DMA_REQ_SAI1_RX (DMAMUX_CHCFG_DMAMUX1 | 56) /* SAI1 DMA RX request */
|
||||
#define DMA_REQ_SAI1_TX (DMAMUX_CHCFG_DMAMUX1 | 57) /* SAI1 DMA TX request */
|
||||
#define DMA_REQ_RESERVED9 (DMAMUX_CHCFG_DMAMUX1 | 58) /* RESERVED */
|
||||
#define DMA_REQ_RESERVED10 (DMAMUX_CHCFG_DMAMUX1 | 59) /* RESERVED */
|
||||
#define DMA_REQ_LPCMP1 (DMAMUX_CHCFG_DMAMUX1 | 60) /* LPCMP1 DMA request */
|
||||
#define DMA_REQ_LPCMP2 (DMAMUX_CHCFG_DMAMUX1 | 61) /* LPCMP2 DMA request */
|
||||
#define DMA_REQ_ENABLED2 (DMAMUX_CHCFG_DMAMUX1 | 62) /* Always enabled */
|
||||
#define DMA_REQ_ENABLED3 (DMAMUX_CHCFG_DMAMUX1 | 63) /* Always enabled */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DMAMUX_H */
|
||||
|
||||
@ -83,20 +83,20 @@
|
||||
#define QSPI_LUT_SHARE_TYPE1 2U /* Shared Lut */
|
||||
#define QSPI_LUT_SHARE_TYPE2 3U /* Shared Lut */
|
||||
|
||||
#define QSPI_LUT_CMD_STOP 0U ///< End of sequence
|
||||
#define QSPI_LUT_CMD_CMD 1U ///< Command
|
||||
#define QSPI_LUT_CMD_ADDR 2U ///< Address
|
||||
#define QSPI_LUT_CMD_DUMMY 3U ///< Dummy cycles
|
||||
#define QSPI_LUT_CMD_MODE 4U ///< 8-bit mode
|
||||
#define QSPI_LUT_CMD_MODE2 5U ///< 2-bit mode
|
||||
#define QSPI_LUT_CMD_MODE4 6U ///< 4-bit mode
|
||||
#define QSPI_LUT_CMD_READ 7U ///< Read data
|
||||
#define QSPI_LUT_CMD_WRITE 8U ///< Write data
|
||||
#define QSPI_LUT_CMD_JMP_ON_CS 9U ///< Jump on chip select deassert
|
||||
#define QSPI_LUT_CMD_STOP 0U /* End of sequence */
|
||||
#define QSPI_LUT_CMD_CMD 1U /* Command */
|
||||
#define QSPI_LUT_CMD_ADDR 2U /* Address */
|
||||
#define QSPI_LUT_CMD_DUMMY 3U /* Dummy cycles */
|
||||
#define QSPI_LUT_CMD_MODE 4U /* 8-bit mode */
|
||||
#define QSPI_LUT_CMD_MODE2 5U /* 2-bit mode */
|
||||
#define QSPI_LUT_CMD_MODE4 6U /* 4-bit mode */
|
||||
#define QSPI_LUT_CMD_READ 7U /* Read data */
|
||||
#define QSPI_LUT_CMD_WRITE 8U /* Write data */
|
||||
#define QSPI_LUT_CMD_JMP_ON_CS 9U /* Jump on chip select deassert */
|
||||
|
||||
#define QSPI_TRANSFER_TYPE_SYNC 0U ///< Synchronous transfer using polling
|
||||
#define QSPI_TRANSFER_TYPE_ASYNC_INT 1U ///< Interrupt-based asynchronous transfer
|
||||
#define QSPI_TRANSFER_TYPE_ASYNC_DMA 2U ///< DMA-based asynchronous transfer
|
||||
#define QSPI_TRANSFER_TYPE_SYNC 0U /* Synchronous transfer using polling */
|
||||
#define QSPI_TRANSFER_TYPE_ASYNC_INT 1U /* Interrupt-based asynchronous transfer */
|
||||
#define QSPI_TRANSFER_TYPE_ASYNC_DMA 2U /* DMA-based asynchronous transfer */
|
||||
|
||||
#define QSPI_RX_BUF_SIZE 128U
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user