Squashed commit of the following:
arch/arm/src/tiva: Add GPIO IRQ stubs for clean compile
arch/arm/src/tiva/cc13xx: Add build framework for CC13xx GPIO interrupts. Change prototypes of some GPIO IRQ interfaces so that the function prototype is common between LM3S, LM4F, TM4C, and CC13xx.
This commit is contained in:
Gregory Nutt
parent
b3b53a6dd4
commit
eaf62096ee
@ -49,37 +49,38 @@ CMN_CSRCS += up_svcall.c up_trigger_irq.c up_unblocktask.c up_udelay.c
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CMN_CSRCS += up_usestack.c up_vfork.c
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ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
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CMN_CSRCS += up_idle.c
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CMN_CSRCS += up_idle.c
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endif
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ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
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CMN_ASRCS += up_lazyexception.S
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CMN_ASRCS += up_lazyexception.S
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else
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CMN_ASRCS += up_exception.S
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CMN_ASRCS += up_exception.S
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endif
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CMN_CSRCS += up_vectors.c
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ifeq ($(CONFIG_ARCH_FPU),y)
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CMN_ASRCS += up_fpu.S
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CMN_CSRCS += up_copyarmstate.c
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CMN_ASRCS += up_fpu.S
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CMN_CSRCS += up_copyarmstate.c
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endif
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ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
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CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
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CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
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endif
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ifeq ($(CONFIG_STACK_COLORATION),y)
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CMN_CSRCS += up_checkstack.c
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CMN_CSRCS += up_checkstack.c
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endif
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ifeq ($(CONFIG_BUILD_PROTECTED),y)
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CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
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CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
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ifneq ($(CONFIG_DISABLE_SIGNALS),y)
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CMN_CSRCS += up_signal_dispatch.c
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CMN_UASRCS += up_signal_handler.S
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CMN_CSRCS += up_signal_dispatch.c
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CMN_UASRCS += up_signal_handler.S
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endif
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else
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CMN_CSRCS += up_allocateheap.c
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CMN_CSRCS += up_allocateheap.c
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endif
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CHIP_ASRCS =
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@ -87,76 +88,77 @@ CHIP_CSRCS = tiva_allocateheap.c tiva_irq.c tiva_lowputc.c tiva_serial.c
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CHIP_CSRCS += tiva_ssi.c
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ifeq ($(CONFIG_ARCH_CHIP_LM3S),y)
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CHIP_CSRCS += lmxx_tm4c_start.c lm3s_gpio.c tiva_gpioirq.c
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CHIP_CSRCS += lmxx_tm4c_start.c lm3s_gpio.c lmxx_tm4c_gpioirq.c
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CHIP_CSRCS += lm4xx_tm3c_sysctrl.c
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else ifeq ($(CONFIG_ARCH_CHIP_LM4F),y)
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CHIP_CSRCS += lmxx_tm4c_start.c lm4f_gpio.c tiva_gpioirq.c
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CHIP_CSRCS += lmxx_tm4c_start.c lm4f_gpio.c lmxx_tm4c_gpioirq.c
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CHIP_CSRCS += lm4xx_tm3c_sysctrl.c
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else ifeq ($(CONFIG_ARCH_CHIP_TM4C),y)
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CHIP_CSRCS += lmxx_tm4c_start.c tm4c_gpio.c tiva_gpioirq.c
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CHIP_CSRCS += lmxx_tm4c_start.c tm4c_gpio.c lmxx_tm4c_gpioirq.c
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ifeq ($(CONFIG_ARCH_CHIP_TM4C129),y)
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CHIP_CSRCS += tm4c129_sysctrl.c
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else
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CHIP_CSRCS += lm4xx_tm3c_sysctrl.c
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endif
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else ifeq ($(CONFIG_ARCH_CHIP_CC13X0),y)
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CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_gpio.c cc13xx_gpioirq.c
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CHIP_CSRCS += cc13xx_enableclks.c cc13xx_enablepwr.c
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CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_gpio.c cc13xx_gpioirq.c
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CHIP_CSRCS += cc13xx_enableclks.c cc13xx_enablepwr.c
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else ifeq ($(CONFIG_ARCH_CHIP_CC13X2),y)
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CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_gpio.c cc13xx_gpioirq.c
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CHIP_CSRCS += cc13xx_enableclks.c cc13xx_enablepwr.c
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CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_gpio.c cc13xx_gpioirq.c
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CHIP_CSRCS += cc13xx_enableclks.c cc13xx_enablepwr.c
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endif
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ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)
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CHIP_CSRCS += tiva_dumpgpio.c
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endif
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ifeq ($(CONFIG_ARCH_CHIP_TM4C129),y)
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CHIP_CSRCS += tm4c129_sysctrl.c
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else
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CHIP_CSRCS += tiva_sysctrl.c
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CHIP_CSRCS += tiva_dumpgpio.c
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endif
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ifneq ($(CONFIG_SCHED_TICKLESS),y)
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CHIP_CSRCS += tiva_timerisr.c
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CHIP_CSRCS += tiva_timerisr.c
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endif
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ifeq ($(CONFIG_BUILD_PROTECTED),y)
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CHIP_CSRCS += tiva_userspace.c tiva_mpuinit.c
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CHIP_CSRCS += tiva_userspace.c tiva_mpuinit.c
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endif
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ifeq ($(CONFIG_TIVA_I2C),y)
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CHIP_CSRCS += tiva_i2c.c
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CHIP_CSRCS += tiva_i2c.c
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endif
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ifeq ($(CONFIG_TIVA_PWM),y)
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CHIP_CSRCS += tiva_pwm.c
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CHIP_CSRCS += tiva_pwm.c
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endif
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ifeq ($(CONFIG_TIVA_QEI),y)
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CHIP_CSRCS += tiva_qencoder.c
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CHIP_CSRCS += tiva_qencoder.c
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endif
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ifeq ($(CONFIG_TIVA_TIMER),y)
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CHIP_CSRCS += tiva_timerlib.c
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CHIP_CSRCS += tiva_timerlib.c
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ifeq ($(CONFIG_TIVA_TIMER32_PERIODIC),y)
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CHIP_CSRCS += tiva_timerlow32.c
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CHIP_CSRCS += tiva_timerlow32.c
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endif
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endif
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ifeq ($(CONFIG_TIVA_ADC),y)
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CHIP_CSRCS += tiva_adclow.c
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CHIP_CSRCS += tiva_adclib.c
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CHIP_CSRCS += tiva_adclow.c
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CHIP_CSRCS += tiva_adclib.c
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endif
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ifeq ($(CONFIG_TIVA_ETHERNET),y)
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ifeq ($(CONFIG_ARCH_CHIP_LM3S),y)
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CHIP_CSRCS += lm3s_ethernet.c
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CHIP_CSRCS += lm3s_ethernet.c
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endif
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ifeq ($(CONFIG_ARCH_CHIP_TM4C),y)
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CHIP_CSRCS += tm4c_ethernet.c
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CHIP_CSRCS += tm4c_ethernet.c
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endif
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endif
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ifeq ($(CONFIG_TIVA_FLASH),y)
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CHIP_CSRCS += tiva_flash.c
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CHIP_CSRCS += tiva_flash.c
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endif
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ifeq ($(CONFIG_TIVA_EEPROM),y)
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CHIP_CSRCS += tiva_eeprom.c
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CHIP_CSRCS += tiva_eeprom.c
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endif
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# Paths to source files
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@ -45,7 +45,7 @@
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#include <nuttx/irq.h>
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#include "hardware/tiva_prcm"
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#include "hardware/tiva_prcm.h"
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#include "tiva_enableclks.h"
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/****************************************************************************
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@ -45,7 +45,7 @@
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#include <nuttx/irq.h>
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#include "hardware/tiva_prcm"
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#include "hardware/tiva_prcm.h"
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#include "tiva_enablepwr.h"
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/****************************************************************************
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@ -68,14 +68,14 @@ static uint16_t g_domain_usage[2];
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void cc13xx_periph_enablepwr(uint32_t peripheral)
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{
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irgstate_t flags;
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irqstate_t flags;
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uint32_t domain;
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int dndx;
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int pndx;
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dndx = PRCM_DOMAIN_INDEX(peripheral);
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pndx = PRCM_PERIPH_ID(peripheral);
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domain = (pndx == 0 ? PRCM_DOMAIN_SERIAL : PRCM_DOMAIN_PERIPH)
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domain = (pndx == 0 ? PRCM_DOMAIN_SERIAL : PRCM_DOMAIN_PERIPH);
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/* Remember that this peripheral needs power in this domain */
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@ -109,7 +109,7 @@ void cc13xx_periph_disablepwr(uint32_t peripheral)
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{
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int dndx = PRCM_DOMAIN_INDEX(peripheral);
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int pndx = PRCM_PERIPH_ID(peripheral);
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irgstate_t flags;
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irqstate_t flags;
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/* This peripheral no longer needs power in this domain */
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@ -122,7 +122,7 @@ void cc13xx_periph_disablepwr(uint32_t peripheral)
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if (g_domain_usage[dndx] == 0)
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{
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prcm_powerdomain_off(pndx == ? PRCM_DOMAIN_SERIAL : PRCM_DOMAIN_PERIPH);
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prcm_powerdomain_off(pndx == 0 ? PRCM_DOMAIN_SERIAL : PRCM_DOMAIN_PERIPH);
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}
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spin_unlock_irqrestore(flags);
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@ -52,32 +52,12 @@
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#include "tiva_enableclks.h"
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#include "tiva_gpio.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static bool g_gpio_powered;
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -113,6 +93,13 @@ int tiva_configgpio(pinconfig_t pinconfig)
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g_gpio_powered = true;
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}
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#ifdef CONFIG_TIVA_GPIO_IRQS
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/* Mask and clear any pending GPIO interrupt */
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tiva_gpioirqdisable(pinconfig);
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tiva_gpioirqclear(pinconfig);
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#endif
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/* Configure the GPIO as an input. We don't even know if the pin is a
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* a GPIO yet, but may prevent glitches when configure GPIO output pins.
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*/
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250
arch/arm/src/tiva/cc13xx/cc13xx_gpioirq.c
Normal file
250
arch/arm/src/tiva/cc13xx/cc13xx_gpioirq.c
Normal file
@ -0,0 +1,250 @@
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/****************************************************************************
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* arch/arm/src/tiva/common/cc13xx_gpioirq.c
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <nuttx/irq.h>
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#include <stdint.h>
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#include <string.h>
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#include <assert.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "up_internal.h"
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#include "up_arch.h"
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#include "irq/irq.h"
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#include "tiva_gpio.h"
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#ifdef CONFIG_TIVA_GPIO_IRQS
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/****************************************************************************
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* Private types
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****************************************************************************/
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struct gpio_handler_s
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{
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xcpt_t isr; /* Interrupt service routine entry point */
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void *arg; /* The argument that accompanies the interrupt */
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* A table of handlers for each GPIO port interrupt */
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static struct gpio_handler_s g_gpio_inthandler[TIVA_NIRQ_PINS];
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: cc13xx_gpio_interrupt
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*
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* Description:
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* Handle interrupts on each enabled GPIO port
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*
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****************************************************************************/
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static int cc13xx_gpio_interrupt)(int irq, FAR void *context, FAR void *arg)
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{
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unsigned int dio;
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#warning Missing logic
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/* Clear pending interrupts */
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/* Now process each pending interrupt */
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/* Call any handler registered for each pending DIO interrupt */
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FAR struct gpio_handler_s *handler = &g_gpio_inthandler[dio];
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gpioinfo("dio=%d isr=%p arg=%p\n", dio, handler->isr, handler->arg);
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handler->isr(irq, context, handler->arg);
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: tiva_gpioirqinitialize
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*
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* Description:
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* Initialize all vectors to the unexpected interrupt handler
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*
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****************************************************************************/
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int tiva_gpioirqinitialize(void)
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{
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unsigned int dio;
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/* Point all interrupt vectors to the unexpected interrupt */
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for (dio = 0; dio < TIVA_NDIO; dio++)
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{
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g_gpio_inthandler[dio].isr = irq_unexpected_isr;
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g_gpio_inthandler[dio].arg = NULL;
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}
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/* Then attach the GPIO interrupt handler and enable corresponding GPIO
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* interrupts at the NVIC.
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*/
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irq_attach(TIVA_IRQ_AON_GPIO_EDGE, cc13xx_gpio_interrupt, NULL);
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up_enable_irq(TIVA_IRQ_AON_GPIO_EDGE);
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return OK;
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}
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/****************************************************************************
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* Name: tiva_gpioirqattach
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*
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* Description:
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* Attach in GPIO interrupt to the provided 'isr'. If isr==NULL, then the
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* irq_unexpected_isr handler is assigned and the pin's interrupt mask is
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* disabled to stop further interrupts. Otherwise, the new isr is linked
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* and the pin's interrupt mask is set.
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*
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* Returned Value:
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* Zero (OK) is returned on success. Otherwise a negated errno value is
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* return to indicate the nature of the failure.
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*
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****************************************************************************/
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int tiva_gpioirqattach(pinconfig_t pinconfig, xcpt_t isr, void *arg)
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{
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FAR struct gpio_handler_s *handler;
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unsigned int dio;
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irqstate_t flags;
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/* Assign per-pin interrupt handlers */
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dio = (pinconfig->gpio & GPIO_DIO_MASK) >> GPIO_DIO_SHIFT;
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DEBUGASSERT(dio < TIVA_NDIO);
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if (dio < TIVA_NDIO)
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{
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flags = enter_critical_section();
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/* If the new ISR is NULL, then the ISR is being detached.
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* In this case, disable the ISR and direct any interrupts
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* to the unexpected interrupt handler.
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*/
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gpioinfo("Attach dio=%d isr=%p arg=%p\n", dio, isr, arg);
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handler = &g_gpio_inthandler[dio];
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if (isr == NULL)
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{
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tiva_gpioirqdisable(pinconfig);
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handler->isr = irq_unexpected_isr;
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handler->arg = NULL;
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}
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else
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{
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handler->isr = isr;
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handler->arg = arg;
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tiva_gpioirqenable(pinconfig);
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}
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leave_critical_section(flags);
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}
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return OK;
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}
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/****************************************************************************
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* Name: tiva_gpioirqenable
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*
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* Description:
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* Enable the GPIO port IRQ
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*
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||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioirqenable(pinconfig_t pinconfig)
|
||||
{
|
||||
unsigned int dio;
|
||||
dio = (pinconfig->gpio & GPIO_DIO_MASK) >> GPIO_DIO_SHIFT;
|
||||
DEBUGASSERT(dio < TIVA_NDIO);
|
||||
#warning Missing logic
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioirqdisable
|
||||
*
|
||||
* Description:
|
||||
* Disable the GPIO port IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioirqdisable(pinconfig_t pinconfig)
|
||||
{
|
||||
unsigned int dio;
|
||||
dio = (pinconfig->gpio & GPIO_DIO_MASK) >> GPIO_DIO_SHIFT;
|
||||
DEBUGASSERT(dio < TIVA_NDIO);
|
||||
#warning Missing logic
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioirqclear
|
||||
*
|
||||
* Description:
|
||||
* Clears the interrupt status of the input base
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioirqclear(pinconfig_t pinconfig)
|
||||
{
|
||||
unsigned int dio;
|
||||
dio = (pinconfig->gpio & GPIO_DIO_MASK) >> GPIO_DIO_SHIFT;
|
||||
DEBUGASSERT(dio < TIVA_NDIO);
|
||||
#warning Missing logic
|
||||
}
|
||||
|
||||
#endif /* CONFIG_TIVA_GPIO_IRQS */
|
||||
@ -1,5 +1,5 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/tiva/common/tiva_sysctrl.c
|
||||
* arch/arm/src/tiva/common/lmxx_tm4c_sysctrl.c
|
||||
*
|
||||
* Copyright (C) 2009-2014, 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
@ -1,7 +1,8 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/tiva/common/tiva_gpioirq.c
|
||||
* arch/arm/src/tiva/common/lmxx_tm4c_gpioirq.c
|
||||
*
|
||||
* Copyright (C) 2009-2010, 2012, 2014-2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009-2010, 2012, 2014-2016, 2018 Gregory Nutt. All
|
||||
* rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -241,26 +242,6 @@ static int gpioport2irq(uint8_t port)
|
||||
return irq;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioirqclear
|
||||
*
|
||||
* Description:
|
||||
* Clears the interrupt status of the input base
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioirqclear(uint8_t port, uint32_t pinmask)
|
||||
{
|
||||
uintptr_t base = tiva_gpiobaseaddress(port);
|
||||
|
||||
/* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit
|
||||
* in this register clears the corresponding interrupt edge detection logic
|
||||
* register. Writing a 0 has no effect."
|
||||
*/
|
||||
|
||||
modifyreg32(base + TIVA_GPIO_ICR_OFFSET, 0, pinmask);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioporthandler
|
||||
*
|
||||
@ -280,10 +261,12 @@ static int tiva_gpioporthandler(uint8_t port, void *context)
|
||||
irq = gpioport2irq(port);
|
||||
mis = getreg32(base + TIVA_GPIO_MIS_OFFSET);
|
||||
|
||||
tiva_gpioirqclear(port, 0xff);
|
||||
|
||||
gpioinfo("irq=%d mis=0b%08b\n", irq, mis & 0xff);
|
||||
|
||||
/* Clear all pending interrupts */
|
||||
|
||||
putreg32(0xff, base + TIVA_GPIO_ICR_OFFSET);
|
||||
|
||||
/* Now process each IRQ pending in the MIS */
|
||||
|
||||
if (mis != 0)
|
||||
@ -551,9 +534,6 @@ int tiva_gpioirqinitialize(void)
|
||||
g_gpioportirqvector[i].arg = NULL;
|
||||
}
|
||||
|
||||
gpioinfo("tiva_gpioirqinitialize isr=%d/%d irq_unexpected_isr=%p\n",
|
||||
i, TIVA_NIRQ_PINS, irq_unexpected_isr);
|
||||
|
||||
/* Then attach each GPIO interrupt handlers and enable corresponding GPIO
|
||||
* interrupts
|
||||
*/
|
||||
@ -661,12 +641,12 @@ int tiva_gpioirqinitialize(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int tiva_gpioirqattach(uint32_t pinset, xcpt_t isr, void *arg)
|
||||
int tiva_gpioirqattach(pinconfig_t pinconfig, xcpt_t isr, void *arg)
|
||||
{
|
||||
FAR struct gpio_handler_s *handler;
|
||||
irqstate_t flags;
|
||||
uint8_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
uint8_t pinno = (pinset & GPIO_PIN_MASK);
|
||||
uint8_t port = (pinconfig & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
uint8_t pinno = (pinconfig & GPIO_PIN_MASK);
|
||||
uint8_t pin = 1 << pinno;
|
||||
|
||||
/* Assign per-pin interrupt handlers */
|
||||
@ -686,7 +666,7 @@ int tiva_gpioirqattach(uint32_t pinset, xcpt_t isr, void *arg)
|
||||
handler = &g_gpioportirqvector[TIVA_GPIO_IRQ_IDX(port, pinno)];
|
||||
if (isr == NULL)
|
||||
{
|
||||
tiva_gpioirqdisable(port, pin);
|
||||
tiva_gpioirqdisable(pinconfig);
|
||||
handler->isr = irq_unexpected_isr;
|
||||
handler->arg = NULL;
|
||||
}
|
||||
@ -694,7 +674,7 @@ int tiva_gpioirqattach(uint32_t pinset, xcpt_t isr, void *arg)
|
||||
{
|
||||
handler->isr = isr;
|
||||
handler->arg = arg;
|
||||
tiva_gpioirqenable(port, pin);
|
||||
tiva_gpioirqenable(pinconfig);
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
@ -703,48 +683,6 @@ int tiva_gpioirqattach(uint32_t pinset, xcpt_t isr, void *arg)
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioportirqattach
|
||||
*
|
||||
* Description:
|
||||
* Attach 'isr' to the GPIO port. Only use this if you want to handle
|
||||
* the entire ports interrupts explicitly.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioportirqattach(uint8_t port, xcpt_t isr)
|
||||
{
|
||||
irqstate_t flags;
|
||||
int irq = gpioport2irq(port);
|
||||
|
||||
/* assign port interrupt handler */
|
||||
|
||||
if (port < TIVA_NPORTS)
|
||||
{
|
||||
flags = enter_critical_section();
|
||||
|
||||
/* If the new ISR is NULL, then the ISR is being detached.
|
||||
* In this case, disable the ISR and direct any interrupts
|
||||
* to the unexpected interrupt handler.
|
||||
*/
|
||||
|
||||
gpioinfo("assign function=%p to port=%d\n", isr, port);
|
||||
|
||||
if (isr == NULL)
|
||||
{
|
||||
tiva_gpioirqdisable(port, 0xff);
|
||||
irq_attach(irq, irq_unexpected_isr, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
irq_attach(irq, isr, NULL);
|
||||
tiva_gpioirqenable(port, 0xff);
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioirqenable
|
||||
*
|
||||
@ -753,8 +691,10 @@ void tiva_gpioportirqattach(uint8_t port, xcpt_t isr)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioirqenable(uint8_t port, uint8_t pin)
|
||||
void tiva_gpioirqenable(pinconfig_t pinconfig)
|
||||
{
|
||||
uint8_t port = (pinconfig & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
uint8_t pin = (pinconfig & GPIO_PIN_MASK);
|
||||
uintptr_t base = tiva_gpiobaseaddress(port);
|
||||
|
||||
/* Enable the GPIO interrupt. "The GPIO IM register is the interrupt
|
||||
@ -775,8 +715,10 @@ void tiva_gpioirqenable(uint8_t port, uint8_t pin)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioirqdisable(uint8_t port, uint8_t pin)
|
||||
void tiva_gpioirqdisable(pinconfig_t pinconfig)
|
||||
{
|
||||
uint8_t port = (pinconfig & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
uint8_t pin = (pinconfig & GPIO_PIN_MASK);
|
||||
uintptr_t base = tiva_gpiobaseaddress(port);
|
||||
|
||||
/* Disable the GPIO interrupt. "The GPIO IM register is the interrupt
|
||||
@ -789,4 +731,26 @@ void tiva_gpioirqdisable(uint8_t port, uint8_t pin)
|
||||
modifyreg32(base + TIVA_GPIO_IM_OFFSET, pin, 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioirqclear
|
||||
*
|
||||
* Description:
|
||||
* Clears the interrupt status of the input base
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioirqclear(pinconfig)
|
||||
{
|
||||
uint8_t port = (pinconfig & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
uint8_t pin = (pinconfig & GPIO_PIN_MASK);
|
||||
uintptr_t base = tiva_gpiobaseaddress(port);
|
||||
|
||||
/* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit
|
||||
* in this register clears the corresponding interrupt edge detection logic
|
||||
* register. Writing a 0 has no effect."
|
||||
*/
|
||||
|
||||
putreg32((1 << pin), base + TIVA_GPIO_ICR_OFFSET);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_TIVA_GPIO_IRQS */
|
||||
@ -50,6 +50,8 @@
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define TIVA_NDIO 32 /* DIO0-31 */
|
||||
|
||||
/* IOC register offsets ************************************************************/
|
||||
|
||||
#define TIVA_IOC_IOCFG_OFFSET(n) ((n) << 2)
|
||||
@ -126,9 +128,9 @@
|
||||
|
||||
/* Common bitfield for all DIO configuration registers */
|
||||
|
||||
#define IOC_IOCFG_PORTID_MASK (0) /* Bits 0-5: Selects DIO usage */
|
||||
#define IOC_IOCFG_PORTID_SHIFT (0x3f << IOC_IOCFG_PORTID_MASK)
|
||||
# define IOC_IOCFG_PORTID(n) ((uint32_t)(n) << IOC_IOCFG_PORTID_MASK) /* See PORT ID definitions */
|
||||
#define IOC_IOCFG_PORTID_SHIFT (0) /* Bits 0-5: Selects DIO usage */
|
||||
#define IOC_IOCFG_PORTID_MASK (0x3f << IOC_IOCFG_PORTID_SHIFT)
|
||||
# define IOC_IOCFG_PORTID(n) ((uint32_t)(n) << IOC_IOCFG_PORTID_SHIFT) /* See PORT ID definitions */
|
||||
#define IOC_IOCFG_IOSTR_SHIFT (8) /* Bits 8-9: I/O drive strength */
|
||||
#define IOC_IOCFG_IOSTR_MASK (3 << IOC_IOCFG_IOSTR_SHIFT)
|
||||
# define IOC_IOCFG_IOSTR_AUTO (0 << IOC_IOCFG_IOSTR_SHIFT) /* Automatic drive strength */
|
||||
@ -154,13 +156,13 @@
|
||||
# define IOC_IOCFG_EDGEDET_BOTH (3 << IOC_IOCFG_EDGEDET_SHIFT) /* Both edge detection */
|
||||
#define IOC_IOCFG_EDGE_IRQEN (1 << 18) /* Bit 18: Enable interrupt generation */
|
||||
#define IOC_IOCFG_IOMODE_SHIFT (24) /* Bits 24-26: I/O Mode */
|
||||
#define IOC_IOCFG_IOMODE_MASK (7 << IOC_IOCFG1_IOMODE_SHIFT)
|
||||
# define IOC_IOCFG_IOMODE_NORMAL (0 << IOC_IOCFG1_IOMODE_SHIFT) /* Normal I/O */
|
||||
# define IOC_IOCFG_IOMODE_INV (1 << IOC_IOCFG1_IOMODE_SHIFT) /* Inverted I/O */
|
||||
# define IOC_IOCFG_IOMODE_OPENDR (4 << IOC_IOCFG1_IOMODE_SHIFT) /* Open drain */
|
||||
# define IOC_IOCFG_IOMODE_OPENDRINV (5 << IOC_IOCFG1_IOMODE_SHIFT) /* Open drain, inverted I/O */
|
||||
# define IOC_IOCFG_IOMODE_OPENSRC (6 << IOC_IOCFG1_IOMODE_SHIFT) /* Open source */
|
||||
# define IOC_IOCFG_IOMODE_OPENSRCINV (7 << IOC_IOCFG1_IOMODE_SHIFT) /* Open source, inverted I/O */
|
||||
#define IOC_IOCFG_IOMODE_MASK (7 << IOC_IOCFG_IOMODE_SHIFT)
|
||||
# define IOC_IOCFG_IOMODE_NORMAL (0 << IOC_IOCFG_IOMODE_SHIFT) /* Normal I/O */
|
||||
# define IOC_IOCFG_IOMODE_INV (1 << IOC_IOCFG_IOMODE_SHIFT) /* Inverted I/O */
|
||||
# define IOC_IOCFG_IOMODE_OPENDR (4 << IOC_IOCFG_IOMODE_SHIFT) /* Open drain */
|
||||
# define IOC_IOCFG_IOMODE_OPENDRINV (5 << IOC_IOCFG_IOMODE_SHIFT) /* Open drain, inverted I/O */
|
||||
# define IOC_IOCFG_IOMODE_OPENSRC (6 << IOC_IOCFG_IOMODE_SHIFT) /* Open source */
|
||||
# define IOC_IOCFG_IOMODE_OPENSRCINV (7 << IOC_IOCFG_IOMODE_SHIFT) /* Open source, inverted I/O */
|
||||
#define IOC_IOCFG_WUCFG_SHIFT (27) /* Bits 27-28: Wakeup Configuration */
|
||||
#define IOC_IOCFG_WUCFG_MASK (3 << IOC_IOCFG_WUCFG_SHIFT)
|
||||
# define IOC_IOCFG_WUCFG_NONE (0 << IOC_IOCFG_WUCFG_SHIFT) /* 0, 1: Wakeup disabled */
|
||||
|
||||
@ -50,6 +50,8 @@
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define TIVA_NDIO 32 /* DIO0-31 */
|
||||
|
||||
/* IOC register offsets ************************************************************/
|
||||
|
||||
#define TIVA_IOC_IOCFG_OFFSET(n) ((n) << 2)
|
||||
@ -126,7 +128,7 @@
|
||||
|
||||
#define IOC_IOCFG_PORTID_SHIFT (0) /* Bits 0-5: Selects DIO usage */
|
||||
#define IOC_IOCFG_PORTID_MASK (0x3f << IOC_IOCFG_PORTID_SHIFT)
|
||||
# define IOC_IOCFG_PORTID(n) ((uint32_t)(n) << IOC_IOCFG_PORTID_MASK) /* See PORT ID definitions */
|
||||
# define IOC_IOCFG_PORTID(n) ((uint32_t)(n) << IOC_IOCFG_PORTID_SHIFT) /* See PORT ID definitions */
|
||||
#define IOC_IOCFG_IOEV_MCU_WUEN (1 << 6) /* Bit 6: Input edge asserts MCU_WU event */
|
||||
#define IOC_IOCFG_IOEV_RTCEN (1 << 7) /* Bit 7: Input edge asserts RTC event */
|
||||
#define IOC_IOCFG_IOSTR_SHIFT (8) /* Bits 8-9: I/O drive strength */
|
||||
@ -157,13 +159,13 @@
|
||||
#define IOC_IOCFG_IOEV_AON_PROG1 (1 << 22) /* Bit 22: Input edge asserts AON_PROG1 */
|
||||
#define IOC_IOCFG_IOEV_AON_PROG2 (1 << 23) /* Bit 23: Input edge assert AON_PROG2 */
|
||||
#define IOC_IOCFG_IOMODE_SHIFT (24) /* Bits 24-26: I/O Mode */
|
||||
#define IOC_IOCFG_IOMODE_MASK (7 << IOC_IOCFG1_IOMODE_SHIFT)
|
||||
# define IOC_IOCFG_IOMODE_NORMAL (0 << IOC_IOCFG1_IOMODE_SHIFT) /* Normal I/O */
|
||||
# define IOC_IOCFG_IOMODE_INV (1 << IOC_IOCFG1_IOMODE_SHIFT) /* Inverted I/O */
|
||||
# define IOC_IOCFG_IOMODE_OPENDR (4 << IOC_IOCFG1_IOMODE_SHIFT) /* Open drain */
|
||||
# define IOC_IOCFG_IOMODE_OPENDRINV (5 << IOC_IOCFG1_IOMODE_SHIFT) /* Open drain, inverted I/O */
|
||||
# define IOC_IOCFG_IOMODE_OPENSRC (6 << IOC_IOCFG1_IOMODE_SHIFT) /* Open source */
|
||||
# define IOC_IOCFG_IOMODE_OPENSRCINV (7 << IOC_IOCFG1_IOMODE_SHIFT) /* Open source, inverted I/O */
|
||||
#define IOC_IOCFG_IOMODE_MASK (7 << IOC_IOCFG_IOMODE_SHIFT)
|
||||
# define IOC_IOCFG_IOMODE_NORMAL (0 << IOC_IOCFG_IOMODE_SHIFT) /* Normal I/O */
|
||||
# define IOC_IOCFG_IOMODE_INV (1 << IOC_IOCFG_IOMODE_SHIFT) /* Inverted I/O */
|
||||
# define IOC_IOCFG_IOMODE_OPENDR (4 << IOC_IOCFG_IOMODE_SHIFT) /* Open drain */
|
||||
# define IOC_IOCFG_IOMODE_OPENDRINV (5 << IOC_IOCFG_IOMODE_SHIFT) /* Open drain, inverted I/O */
|
||||
# define IOC_IOCFG_IOMODE_OPENSRC (6 << IOC_IOCFG_IOMODE_SHIFT) /* Open source */
|
||||
# define IOC_IOCFG_IOMODE_OPENSRCINV (7 << IOC_IOCFG_IOMODE_SHIFT) /* Open source, inverted I/O */
|
||||
#define IOC_IOCFG_WUCFG_SHIFT (27) /* Bits 27-28: Wakeup Configuration */
|
||||
#define IOC_IOCFG_WUCFG_MASK (3 << IOC_IOCFG_WUCFG_SHIFT)
|
||||
# define IOC_IOCFG_WUCFG_NONE (0 << IOC_IOCFG_WUCFG_SHIFT) /* 0, 1: Wakeup disabled */
|
||||
|
||||
@ -559,8 +559,8 @@ static inline void tiva_interrupt(pinconfig_t pinconfig)
|
||||
|
||||
/* Mask and clear the GPIO interrupt */
|
||||
|
||||
tiva_gpioirqdisable(port, pin);
|
||||
tiva_gpioirqclear(port, pin);
|
||||
tiva_gpioirqdisable(pinconfig);
|
||||
tiva_gpioirqclear(pinconfig);
|
||||
|
||||
/* handle according to the selected interrupt type */
|
||||
|
||||
|
||||
@ -585,8 +585,8 @@ static inline void tiva_interrupt(pinconfig_t pinconfig)
|
||||
|
||||
/* Mask and clear the GPIO interrupt */
|
||||
|
||||
tiva_gpioirqdisable(port, pin);
|
||||
tiva_gpioirqclear(port, pin);
|
||||
tiva_gpioirqdisable(pinconfig);
|
||||
tiva_gpioirqclear(pinconfig);
|
||||
|
||||
/* handle according to the selected interrupt type */
|
||||
|
||||
|
||||
@ -173,18 +173,6 @@ int weak_function tiva_gpioirqinitialize(void);
|
||||
int tiva_gpioirqattach(pinconfig_t pinconfig, xcpt_t isr, void *arg);
|
||||
# define tiva_gpioirqdetach(p) tiva_gpioirqattach((p),NULL,NULL)
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioportirqattach
|
||||
*
|
||||
* Description:
|
||||
* Attach 'isr' to the GPIO port. Only use this if you want to handle
|
||||
* the entire ports interrupts explicitly.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioportirqattach(uint8_t port, xcpt_t isr);
|
||||
# define tiva_gpioportirqdetach(port) tiva_gpioportirqattach(port, NULL)
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioirqenable
|
||||
*
|
||||
@ -193,7 +181,7 @@ void tiva_gpioportirqattach(uint8_t port, xcpt_t isr);
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioirqenable(uint8_t port, uint8_t pin);
|
||||
void tiva_gpioirqenable(pinconfig_t pinconfig);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioirqdisable
|
||||
@ -203,7 +191,7 @@ void tiva_gpioirqenable(uint8_t port, uint8_t pin);
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioirqdisable(uint8_t port, uint8_t pin);
|
||||
void tiva_gpioirqdisable(pinconfig_t pinconfig);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_gpioirqclear
|
||||
@ -213,7 +201,7 @@ void tiva_gpioirqdisable(uint8_t port, uint8_t pin);
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void tiva_gpioirqclear(uint8_t port, uint32_t pinmask);
|
||||
void tiva_gpioirqclear(pinconfig_t pinconfig);
|
||||
|
||||
#endif /* CONFIG_TIVA_GPIO_IRQS */
|
||||
|
||||
|
||||
@ -632,8 +632,8 @@ static inline void tiva_interrupt(pinconfig_t pinconfig)
|
||||
|
||||
/* Mask and clear the GPIO interrupt */
|
||||
|
||||
tiva_gpioirqdisable(port, pin);
|
||||
tiva_gpioirqclear(port, pin);
|
||||
tiva_gpioirqdisable(pinconfig);
|
||||
tiva_gpioirqclear(pinconfig);
|
||||
|
||||
/* handle according to the selected interrupt type */
|
||||
|
||||
|
||||
@ -89,6 +89,7 @@ void board_button_initialize(void)
|
||||
uint32_t board_buttons(void)
|
||||
{
|
||||
#warning Missing logic
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
@ -56,25 +56,13 @@
|
||||
|
||||
const struct cc134xx_pinconfig_s g_gpio_uart0_rx =
|
||||
{
|
||||
.gpio =
|
||||
{
|
||||
GPIO_DIO(0)
|
||||
},
|
||||
.ioc =
|
||||
{
|
||||
GPIO_PORTID(IOC_IOCFG_PORTID_UART0_RX) | IOC_STD_INPUT
|
||||
}
|
||||
.gpio = GPIO_DIO(0),
|
||||
.ioc = IOC_IOCFG_PORTID(IOC_IOCFG_PORTID_UART0_RX) | IOC_STD_INPUT
|
||||
};
|
||||
|
||||
const struct cc134xx_pinconfig_s g_gpio_uart0_tx =
|
||||
{
|
||||
.gpio =
|
||||
{
|
||||
GPIO_DIO(1)
|
||||
},
|
||||
.ioc =
|
||||
{
|
||||
GPIO_PORTID(IOC_IOCFG_PORTID_UART0_TX) | IOC_STD_OUTPUT
|
||||
}
|
||||
.gpio = GPIO_DIO(1),
|
||||
.ioc = IOC_IOCFG_PORTID(IOC_IOCFG_PORTID_UART0_TX) | IOC_STD_OUTPUT
|
||||
};
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user