Fix device configuration... now Mikroelektronika PIC32MX7 MMB board works.
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4794 42af7a65-404d-4744-a932-0658087f49c3
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@ -2,7 +2,7 @@
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* configs/pcblogic-pic32mx/include/board.h
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* include/arch/board/board.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -53,6 +53,7 @@
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#define BOARD_POSC_FREQ 8000000 /* Primary OSC XTAL frequency (8MHz) */
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#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */
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#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */
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/* PLL configuration and resulting CPU clock.
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* CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV
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@ -57,6 +57,7 @@
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#define BOARD_POSC_FREQ 8000000 /* Primary OSC XTAL frequency (8MHz) */
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#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */
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#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */
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/* PLL configuration and resulting CPU clock.
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* CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV
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@ -58,6 +58,14 @@
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#define BOARD_POSC_FREQ 8000000 /* Primary OSC XTAL frequency (8MHz) */
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#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */
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/* Clock modes */
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#define BOARD_POSC_XTMODE 1 /* Resonator, crystal or resonator (XT) mode */
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#undef BOARD_POSC_SWITCH /* Use FRC until POSC stabilizes, then switch */
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#undef BOARD_POSC_FSCM /* Switch to FRC if POSC fails */
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#define BOARD_SOSC_ENABLE 1 /* Enable Secondary Oscillator */
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#define BOARD_SOSC_IESO 1 /* Internal External Switchover mode is enabled */
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/* PLL configuration and resulting CPU clock.
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* CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV
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*/
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@ -79,8 +87,8 @@
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* PBCLOCK = CPU_CLOCK / PBDIV
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*/
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#define BOARD_PBDIV 2 /* Peripheral clock divisor (PBDIV) */
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#define BOARD_PBCLOCK 40000000 /* Peripheral clock (PBCLK = 80MHz/2) */
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#define BOARD_PBDIV 1 /* Peripheral clock divisor (PBDIV) */
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#define BOARD_PBCLOCK 80000000 /* Peripheral clock (PBCLK = 80MHz/1) */
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/* Watchdog pre-scaler (re-visit) */
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@ -53,6 +53,7 @@
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#define BOARD_POSC_FREQ 20000000 /* Primary OSC XTAL frequency (20MHz) */
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#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */
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#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */
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/* PLL configuration and resulting CPU clock.
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* CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV
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@ -54,6 +54,7 @@
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#define BOARD_POSC_FREQ 8000000 /* Primary OSC XTAL frequency (8MHz) */
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#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz)
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* (Not present on my board) */
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#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */
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/* PLL configuration and resulting CPU clock.
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* CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV
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