Incorporate i.MX1 SPI driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1741 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
9b5d310885
commit
ebb8d236aa
@ -47,7 +47,7 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
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CHIP_ASRCS = imx_lowputc.S
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CHIP_CSRCS = imx_boot.c imx_gpio.c imx_allocateheap.c imx_irq.c \
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imx_serial.c imx_timerisr.c imx_decodeirq.c #imx_framebuffer.c
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imx_serial.c imx_timerisr.c imx_decodeirq.c imx_spi.c
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ifeq ($(CONFIG_USBDEV),y)
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CHIP_CSRCS += imx_usbdev.c
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@ -38,17 +38,21 @@
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/spi.h>
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#include <sys/types.h>
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#include <errno.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include <nuttx/arch.h>
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#include <nuttx/spi.h>
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#include <arch/io.h>
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#include <arch/irq.h>
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#include <arch/board/board.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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#include "imx_gpio.h"
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#include "imx_cspi.h"
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/****************************************************************************
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@ -80,6 +84,10 @@
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#if NSPIS > 0
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/* The number of words that will fit in the Tx FIFO */
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#define IMX_TXFIFO_WORDS 8
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/****************************************************************************
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* Private Type Definitions
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****************************************************************************/
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@ -90,11 +98,36 @@ struct imx_spidev_s
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#ifndef CONFIG_SPI_POLLWAIT
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sem_t sem; /* Wait for transfer to complete */
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#endif
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/* These following are the source and destination buffers of the transfer.
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* they are retained in this structure so that they will be accessible
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* from an interrupt handler. The actual type of the buffer is ubyte is
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* nbits <=8 and uint16 is nbits >8.
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*/
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void *txbuffer; /* Source buffer */
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void *rxbuffer; /* Destination buffer */
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/* These are functions pointers that are configured to perform the
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* appropriate transfer for the particular kind of exchange that is
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* occurring. Differnt functions may be selected depending on (1)
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* if the tx or txbuffer is NULL and depending on the number of bits
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* per word.
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*/
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void (*txword)(struct imx_spidev_s *priv);
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void (*rxword)(struct imx_spidev_s *priv);
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uint32 base; /* SPI register base address */
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uint32 frequency; /* Current desired SCLK frequency */
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uint32 actual; /* Current actual SCLK frequency */
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int ntxwords; /* Number of words left to transfer on the Tx FIFO */
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int nrxwords; /* Number of words received on the Rx FIFO */
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int nwords; /* Number of words to be exchanged */
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ubyte mode; /* Current mode */
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ubyte nbytes; /* Current number of bits per word */
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ubyte nbits; /* Current number of bits per word */
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#ifndef CONFIG_SPI_POLLWAIT
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ubyte irq; /* SPI IRQ number */
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#endif
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@ -104,22 +137,36 @@ struct imx_spidev_s
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* Private Function Prototypes
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****************************************************************************/
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/* SPI helpers */
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/* SPI register access */
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static inline uint32 spi_getreg(struct imx_spidev_s *priv, unsigned int offset);
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static inline void spi_putreg(struct imx_spidev_s *priv, unsigned int offset, uint32 value);
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/* SPI data transfer */
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static void spi_txnull(struct imx_spidev_s *priv);
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static void spi_txuint16(struct imx_spidev_s *priv);
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static void spi_txubyte(struct imx_spidev_s *priv);
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static void spi_rxnull(struct imx_spidev_s *priv);
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static void spi_rxuint16(struct imx_spidev_s *priv);
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static void spi_rxubyte(struct imx_spidev_s *priv);
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static int spi_performtx(struct imx_spidev_s *priv);
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static inline void spi_performrx(struct imx_spidev_s *priv);
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static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer,
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void *rxbuffer, unsigned int nwords);
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/* Interrupt handling */
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#ifndef CONFIG_SPI_POLLWAIT
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static inline struct imx_spidev_s *spi_mapirq(int irq);
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static int spi_interrupt(int irq, void *context);
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#endif
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static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer,
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void *rxbuffer, unsigned int nwords);
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/* SPI methods */
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static uint32 spi_setfrequency(FAR struct spi_dev_s *dev, uint32 frequency);
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static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
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static ubyte spi_send(FAR struct spi_dev_s *dev, uint16 wd);
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static uint16 spi_send(FAR struct spi_dev_s *dev, uint16 wd);
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static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t buflen);
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static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t buflen);
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@ -131,13 +178,13 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t
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static const struct spi_ops_s g_spiops =
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{
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.select = imx_spiselect, /* Provided externally by board logic */
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.frequency = spi_setfrequency,
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.setmode = spi_setmode,
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.status = imx_spistatus, /* Provided externally by board logic */
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.send = spi_send,
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.sndblock = spi_sndblock,
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.recvblock = spi_recvblock,
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.select = imx_spiselect, /* Provided externally by board logic */
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.setfrequency = spi_setfrequency,
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.setmode = spi_setmode,
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.status = imx_spistatus, /* Provided externally by board logic */
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.send = spi_send,
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.sndblock = spi_sndblock,
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.recvblock = spi_recvblock,
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};
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/* This supports is up to two SPI busses/ports */
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@ -147,7 +194,7 @@ static struct imx_spidev_s g_spidev[] =
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#ifndef CONFIG_SPI1_DISABLE
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{
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.ops = &g_spiops,
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.base = IMX_CSPI1_VBASE
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.base = IMX_CSPI1_VBASE,
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#ifndef CONFIG_SPI_POLLWAIT
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.irq = IMX_IRQ_CSPI1,
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#endif
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@ -156,7 +203,7 @@ static struct imx_spidev_s g_spidev[] =
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#ifndef CONFIG_SPI2_DISABLE
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{
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.ops = &g_spiops,
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.base = IMX_CSPI2_VBASE
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.base = IMX_CSPI2_VBASE,
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#ifndef CONFIG_SPI_POLLWAIT
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.irq = IMX_IRQ_CSPI2,
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#endif
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@ -213,6 +260,318 @@ static inline void spi_putreg(struct imx_spidev_s *priv, unsigned int offset, ui
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putreg32(value, priv->base + offset);
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}
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/****************************************************************************
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* Name: spi_txnull, spi_txuint16, and spi_txubyte
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*
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* Description:
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* Transfer all ones, a ubyte, or uint16 to Tx FIFO and update the txbuffer
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* pointer appropriately. The selected function dependes on (1) if there
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* is a source txbuffer provided, and (2) if the number of bits per
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* word is <=8 or >8.
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*
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* Input Parameters:
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* priv - Device-specific state data
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void spi_txnull(struct imx_spidev_s *priv)
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{
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spi_putreg(priv, CSPI_TXD_OFFSET, 0xffff);
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}
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static void spi_txuint16(struct imx_spidev_s *priv)
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{
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uint16 *ptr = (uint16*)priv->txbuffer;
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spi_putreg(priv, CSPI_TXD_OFFSET, *ptr++);
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priv->txbuffer = (void*)ptr;
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}
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static void spi_txubyte(struct imx_spidev_s *priv)
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{
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ubyte *ptr = (ubyte*)priv->txbuffer;
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spi_putreg(priv, CSPI_TXD_OFFSET, *ptr++);
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priv->txbuffer = (void*)ptr;
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}
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/****************************************************************************
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* Name: spi_rxnull, spi_rxuint16, and spi_rxubyte
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*
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* Description:
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* Discard input, save a ubyte, or or save a uint16 from Tx FIFO in the
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* user rxvbuffer and update the rxbuffer pointer appropriately. The
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* selected function dependes on (1) if there is a desination rxbuffer
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* provided, and (2) if the number of bits per word is <=8 or >8.
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*
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* Input Parameters:
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* priv - Device-specific state data
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void spi_rxnull(struct imx_spidev_s *priv)
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{
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(void)spi_getreg(priv, CSPI_RXD_OFFSET);
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}
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static void spi_rxuint16(struct imx_spidev_s *priv)
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{
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uint16 *ptr = (uint16*)priv->rxbuffer;
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*ptr++ = (uint16)spi_getreg(priv, CSPI_TXD_OFFSET);
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priv->rxbuffer = (void*)ptr;
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}
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static void spi_rxubyte(struct imx_spidev_s *priv)
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{
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ubyte *ptr = (ubyte*)priv->rxbuffer;
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*ptr++ = (ubyte)spi_getreg(priv, CSPI_TXD_OFFSET);
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priv->rxbuffer = (void*)ptr;
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}
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/****************************************************************************
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* Name: spi_performtx
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*
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* Description:
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* If the Tx FIFO is empty, then transfer as many words as we can to
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* the FIFO.
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*
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* Input Parameters:
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* priv - Device-specific state data
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*
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* Returned Value:
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* The number of words written to the Tx FIFO (a value from 0 to 8,
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* inclusive).
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*
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****************************************************************************/
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static int spi_performtx(struct imx_spidev_s *priv)
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{
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uint32 regval;
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int ntxd = 0; /* Number of words written to Tx FIFO */
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/* Check if the Tx FIFO is empty */
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if ((spi_getreg(priv, CSPI_INTCS_OFFSET) & CSPI_INTCS_TE) != 0)
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{
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/* Check if all of the Tx words have been sent */
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if (priv->ntxwords > 0)
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{
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/* No.. Transfer more words until either the TxFIFO is full or
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* until all of the user provided data has been sent.
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*/
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for (; ntxd < priv->ntxwords && ntxd < IMX_TXFIFO_WORDS; ntxd++)
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{
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priv->txword(priv);
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}
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/* Update the count of words to to transferred */
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priv->ntxwords -= ntxd;
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}
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else
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{
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/* Yes.. The transfer is complete, disable Tx FIFO empty interrupt */
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regval = spi_getreg(priv, CSPI_INTCS_OFFSET);
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regval &= ~CSPI_INTCS_TEEN;
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spi_putreg(priv, CSPI_INTCS_OFFSET, regval);
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}
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}
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return ntxd;
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}
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/****************************************************************************
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* Name: spi_performrx
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*
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* Description:
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* Transfer as many bytes as possible from the Rx FIFO to the user Rx
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* buffer (if one was provided).
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*
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* Input Parameters:
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* priv - Device-specific state data
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void spi_performrx(struct imx_spidev_s *priv)
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{
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/* Loop while data is available in the Rx FIFO */
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while ((spi_getreg(priv, CSPI_INTCS_OFFSET) & CSPI_INTCS_RR) != 0)
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{
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/* Have all of the requested words been transferred from the Rx FIFO? */
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if (priv->nrxwords < priv->nwords)
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{
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/* No.. Read more data from Rx FIFO */
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priv->rxword(priv);
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priv->nrxwords++;
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}
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}
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}
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/****************************************************************************
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* Name: spi_startxfr
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*
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* Description:
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* If data was added to the Tx FIFO, then start the exchange
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*
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* Input Parameters:
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* priv - Device-specific state data
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* ntxd - The number of bytes added to the Tx FIFO by spi_performtx.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void spi_startxfr(struct imx_spidev_s *priv, int ntxd)
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{
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uint32 regval;
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/* The XCH bit initiates an exchange in master mode. It remains set
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* remains set while the exchange is in progress but is automatically
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* clear when all data in the Tx FIFO and shift register are shifted out.
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* So if we have added data to the Tx FIFO on this interrupt, we must
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* set the XCH bit to resume the exchange.
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*/
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if (ntxd > 0)
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{
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regval = spi_getreg(priv, CSPI_CTRL_OFFSET);
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regval |= CSPI_CTRL_XCH;
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spi_putreg(priv, CSPI_CTRL_OFFSET, regval);
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}
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}
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/****************************************************************************
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* Name: spi_transfer
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*
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* Description:
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* Exchange a block data with the SPI device
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*
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* Input Parameters:
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* priv - Device-specific state data
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* txbuffer - The buffer of data to send to the device (may be NULL).
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* rxbuffer - The buffer to receive data from the device (may be NULL).
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* nwords - The total number of words to be exchanged. If the interface
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* uses <= 8 bits per word, then this is the number of ubytes;
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* if the interface uses >8 bits per word, then this is the
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* number of uint16's
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*
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* Returned Value:
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* 0: success, <0:Negated error number on failure
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*
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****************************************************************************/
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static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer,
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void *rxbuffer, unsigned int nwords)
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{
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#ifndef CONFIG_SPI_POLLWAIT
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irqstate_t flags;
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#endif
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uint32 regval;
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int ntxd;
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int ret;
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/* Set up to perform the transfer */
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priv->txbuffer = (ubyte*)txbuffer; /* Source buffer */
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priv->rxbuffer = (ubyte*)rxbuffer; /* Destination buffer */
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priv->ntxwords = nwords; /* Number of words left to send */
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priv->nrxwords = 0; /* Number of words received */
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priv->nwords = nwords; /* Total number of exchanges */
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/* Set up the low-level data transfer function pointers */
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if (priv->nbits > 8)
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{
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priv->txword = spi_txuint16;
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priv->rxword = spi_rxuint16;
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}
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else
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{
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priv->txword = spi_txubyte;
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priv->rxword = spi_rxubyte;
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}
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if (!txbuffer)
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{
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priv->txword = spi_txnull;
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}
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if (!rxbuffer)
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{
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priv->rxword = spi_rxnull;
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}
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/* Prime the Tx FIFO to start the sequence (saves one interrupt) */
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#ifndef CONFIG_SPI_POLLWAIT
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flags = irqsave();
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ntxd = spi_performtx(priv);
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spi_startxfr(priv, ntxd);
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/* Enable transmit empty interrupt */
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regval = spi_getreg(priv, CSPI_INTCS_OFFSET);
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regval |= CSPI_INTCS_TEEN;
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spi_putreg(priv, CSPI_INTCS_OFFSET, regval);
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irqrestore(flags);
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/* Wait for the transfer to complete. Since there is no handshake
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* with SPI, the following should complete even if there are problems
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* with the transfer, so it should be safe with no timeout.
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*/
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do
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{
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/* Wait to be signaled from the interrupt handler */
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ret = sem_wait(&priv->sem);
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}
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while (ret < 0 && errno == EINTR);
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#else
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/* Perform the transfer using polling logic. This will totally
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* dominate the CPU until the transfer is complete. Only recommended
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* if (1) your SPI is very fast, and (2) if you only use very short
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* transfers.
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*/
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do
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{
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/* Handle outgoing Tx FIFO transfers */
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ntxd = spi_performtx(priv);
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/* Handle incoming Rx FIFO transfers */
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spi_performrx(priv);
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/* Resume the transfer */
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spi_startxfr(priv, ntxd);
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/* If there are other threads at this same priority level,
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* the following may help:
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*/
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sched_yield();
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}
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while (priv->nrxwords < priv->nwords);
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#endif
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return OK;
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}
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/****************************************************************************
|
||||
* Name: spi_mapirq
|
||||
*
|
||||
@ -248,7 +607,7 @@ static inline struct imx_spidev_s *spi_mapirq(int irq)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: spi_transfer
|
||||
* Name: spi_interrupt
|
||||
*
|
||||
* Description:
|
||||
* Exchange a block data with the SPI device
|
||||
@ -271,38 +630,34 @@ static inline struct imx_spidev_s *spi_mapirq(int irq)
|
||||
static int spi_interrupt(int irq, void *context)
|
||||
{
|
||||
struct imx_spidev_s *priv = spi_mapirq(irq);
|
||||
DBGASSERT(priv != NULL);
|
||||
# error "Missing logic"
|
||||
int ntxd;
|
||||
|
||||
DEBUGASSERT(priv != NULL);
|
||||
|
||||
/* Handle outgoing Tx FIFO transfers */
|
||||
|
||||
ntxd = spi_performtx(priv);
|
||||
|
||||
/* Handle incoming Rx FIFO transfers */
|
||||
|
||||
spi_performrx(priv);
|
||||
|
||||
/* Resume the transfer */
|
||||
|
||||
spi_startxfr(priv, ntxd);
|
||||
|
||||
/* Check if the transfer is complete */
|
||||
|
||||
if (priv->nrxwords >= priv->nwords)
|
||||
{
|
||||
/* Yes, wake up the waiting thread */
|
||||
|
||||
sem_post(&priv->sem);
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: spi_transfer
|
||||
*
|
||||
* Description:
|
||||
* Exchange a block data with the SPI device
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - Device-specific state data
|
||||
* txbuffer - The buffer of data to send to the device (may be NULL).
|
||||
* rxbuffer - The buffer to receive data from the device (may be NULL).
|
||||
* nwords - The total number of words to be exchanged. If the interface
|
||||
* uses <= 8 bits per word, then this is the number of ubytes;
|
||||
* if the interface uses >8 bits per word, then this is the
|
||||
* number of uint16's
|
||||
*
|
||||
* Returned Value:
|
||||
* 0: success, <0:Negated error number on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer,
|
||||
void *rxbuffer, unsigned int nwords)
|
||||
{
|
||||
#error "Missing logic"
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: spi_setfrequency
|
||||
*
|
||||
@ -323,55 +678,55 @@ static uint32 spi_setfrequency(FAR struct spi_dev_s *dev, uint32 frequency)
|
||||
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
|
||||
uint32 actual = priv->actual;
|
||||
|
||||
if (priv & frequency != priv->frequency)
|
||||
if (priv && frequency != priv->frequency)
|
||||
{
|
||||
uint32 freqbits;
|
||||
uint32 regval;
|
||||
|
||||
if (frequency >= PERCLK2 / 4)
|
||||
if (frequency >= IMX_PERCLK2_FREQ / 4)
|
||||
{
|
||||
freqbits = CSPI_CTRL_DIV4;
|
||||
actual = PERCLK2 / 4;
|
||||
actual = IMX_PERCLK2_FREQ / 4;
|
||||
}
|
||||
else if (frequency >= PERCLK2 / 8)
|
||||
else if (frequency >= IMX_PERCLK2_FREQ / 8)
|
||||
{
|
||||
freqbits = CSPI_CTRL_DIV8;
|
||||
actual = PERCLK2 / 8;
|
||||
actual = IMX_PERCLK2_FREQ / 8;
|
||||
}
|
||||
else if (frequency >= PERCLK2 / 16)
|
||||
else if (frequency >= IMX_PERCLK2_FREQ / 16)
|
||||
{
|
||||
freqbits = CSPI_CTRL_DIV16;
|
||||
actual = PERCLK2 / 16;
|
||||
actual = IMX_PERCLK2_FREQ / 16;
|
||||
}
|
||||
else if (frequency >= PERCLK2 / 32)
|
||||
else if (frequency >= IMX_PERCLK2_FREQ / 32)
|
||||
{
|
||||
freqbits = CSPI_CTRL_DIV32;
|
||||
actual = PERCLK2 / 32;
|
||||
actual = IMX_PERCLK2_FREQ / 32;
|
||||
}
|
||||
else if (frequency >= PERCLK2 / 64)
|
||||
else if (frequency >= IMX_PERCLK2_FREQ / 64)
|
||||
{
|
||||
freqbits = CSPI_CTRL_DIV64;
|
||||
actual = PERCLK2 / 64;
|
||||
actual = IMX_PERCLK2_FREQ / 64;
|
||||
}
|
||||
else if (frequency >= PERCLK2 / 128)
|
||||
else if (frequency >= IMX_PERCLK2_FREQ / 128)
|
||||
{
|
||||
freqbits = CSPI_CTRL_DIV128;
|
||||
actual = PERCLK2 / 128;
|
||||
actual = IMX_PERCLK2_FREQ / 128;
|
||||
}
|
||||
else if (frequency >= PERCLK2 / 256)
|
||||
else if (frequency >= IMX_PERCLK2_FREQ / 256)
|
||||
{
|
||||
freqbits = CSPI_CTRL_DIV256;
|
||||
actual = PERCLK2 / 256;
|
||||
actual = IMX_PERCLK2_FREQ / 256;
|
||||
}
|
||||
else /*if (frequency >= PERCLK2 / 512) */
|
||||
else /*if (frequency >= IMX_PERCLK2_FREQ / 512) */
|
||||
{
|
||||
freqbits = CSPI_CTRL_DIV512;
|
||||
actual = PERCLK2 / 512;
|
||||
actual = IMX_PERCLK2_FREQ / 512;
|
||||
}
|
||||
|
||||
/* Then set the selected frequency */
|
||||
|
||||
regval = spi_regreg(priv, CSPI_CTRL_OFFSET);
|
||||
regval = spi_getreg(priv, CSPI_CTRL_OFFSET);
|
||||
regval &= ~(CSPI_CTRL_DATARATE_MASK);
|
||||
regval |= freqbits;
|
||||
spi_putreg(priv, CSPI_CTRL_OFFSET, regval);
|
||||
@ -401,7 +756,7 @@ static uint32 spi_setfrequency(FAR struct spi_dev_s *dev, uint32 frequency)
|
||||
static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
|
||||
{
|
||||
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
|
||||
if (priv & mode != priv->mode)
|
||||
if (priv && mode != priv->mode)
|
||||
{
|
||||
uint32 modebits;
|
||||
uint32 regval;
|
||||
@ -432,7 +787,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
|
||||
|
||||
/* Then set the selected mode */
|
||||
|
||||
regval = spi_regreg(priv, CSPI_CTRL_OFFSET);
|
||||
regval = spi_getreg(priv, CSPI_CTRL_OFFSET);
|
||||
regval &= ~(CSPI_CTRL_PHA|CSPI_CTRL_POL);
|
||||
regval |= modebits;
|
||||
spi_putreg(priv, CSPI_CTRL_OFFSET, regval);
|
||||
@ -564,7 +919,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
|
||||
imxgpio_configpfinput(GPIOC, 16); /* Port C, pin 16: MISO */
|
||||
imxgpio_configpfoutput(GPIOC, 17); /* Port C, pin 17: MOSI */
|
||||
break;
|
||||
#endif
|
||||
#endif /* CONFIG_SPI1_DISABLE */
|
||||
|
||||
#ifndef CONFIG_SPI2_DISABLE
|
||||
case 2:
|
||||
@ -616,24 +971,21 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
|
||||
imxgpio_configoutput(GPIOD, 10);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
#endif /* CONFIG_SPI2_DISABLE */
|
||||
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Disable SPI */
|
||||
#error "Missing logic"
|
||||
|
||||
/* Initialize the state structure */
|
||||
|
||||
ifndef CONFIG_SPI_POLLWAIT
|
||||
#ifndef CONFIG_SPI_POLLWAIT
|
||||
sem_init(&priv->sem, 0, 0);
|
||||
#endif
|
||||
|
||||
/* Initialize control register: min frequency, ignore ready, master mode, mode=0, 8-bit */
|
||||
|
||||
spi_putreg(priv, IMX_CSPI_CTRL_OFFSET,
|
||||
spi_putreg(priv, CSPI_CTRL_OFFSET,
|
||||
CSPI_CTRL_DIV512 | /* Lowest frequency */
|
||||
CSPI_CTRL_DRCTL_IGNRDY | /* Ignore ready */
|
||||
CSPI_CTRL_MODE | /* Master mode */
|
||||
@ -650,7 +1002,7 @@ ifndef CONFIG_SPI_POLLWAIT
|
||||
|
||||
/* Enable interrupts on data ready (and certain error conditions */
|
||||
|
||||
ifndef CONFIG_SPI_POLLWAIT
|
||||
#ifndef CONFIG_SPI_POLLWAIT
|
||||
spi_putreg(priv, CSPI_INTCS_OFFSET,
|
||||
CSPI_INTCS_RREN | /* RXFIFO Data Ready Interrupt Enable */
|
||||
CSPI_INTCS_ROEN | /* RXFIFO Overflow Interrupt Enable */
|
||||
@ -671,22 +1023,22 @@ ifndef CONFIG_SPI_POLLWAIT
|
||||
|
||||
/* Attach the interrupt */
|
||||
|
||||
ifndef CONFIG_SPI_POLLWAIT
|
||||
#ifndef CONFIG_SPI_POLLWAIT
|
||||
irq_attach(priv->irq, (xcpt_t)spi_interrupt);
|
||||
#endif
|
||||
|
||||
/* Enable SPI */
|
||||
|
||||
regval = spi_getreg(priv, IMX_CSPI_CTRL_OFFSET);
|
||||
regval = spi_getreg(priv, CSPI_CTRL_OFFSET);
|
||||
regval |= CSPI_CTRL_SPIEN;
|
||||
spi_putreg(priv, IMX_CSPI_CTRL_OFFSET, regval);
|
||||
spi_putreg(priv, CSPI_CTRL_OFFSET, regval);
|
||||
|
||||
/* Enable SPI interrupts */
|
||||
|
||||
ifndef CONFIG_SPI_POLLWAIT
|
||||
#ifndef CONFIG_SPI_POLLWAIT
|
||||
up_enable_irq(priv->irq);
|
||||
#endif
|
||||
return (FAR struct spi_dev_s *)priv;
|
||||
}
|
||||
|
||||
#endife /* NSPIS > 0 */
|
||||
#endif /* NSPIS > 0 */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user