arch/arm/src/lpc54xx: Continuing with Ethernet initializatino logic. Added MTL initialization and partial MAC initialization.
This commit is contained in:
Gregory Nutt
parent
d46a7beef9
commit
ebdc3b9b58
@ -683,6 +683,51 @@ config LPC54_MII
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---help---
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Support Ethernet MII interface. Default: Use RMII interface.
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config LPC54_MULTIQUEUE
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bool "Use multiple queues"
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default n
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depends on EXPERIMENTAL
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---help---
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Support not yet implemented.
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config LPC54_TX_STRFWD
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bool "Tx store and forward"
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default n
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---help---
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Transmission starts when a full packet resides in the MTL Tx Queue.
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This disables the default Tx threshold controls.
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config LPC54_RX_STRFWD
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bool "Rx store and forward"
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default n
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---help---
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Read packets from the Rx Queue only after the complete packet has
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been written to it. By default, the Rx Queue operates in the
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threshold (cut-through) mode.
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config LPC54_RX_PROMISCUOUS
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bool "Enable Rx promiscuous mode"
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default n
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---help---
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If selected, the address filter module accepts all incoming frames
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regardless of its destination or source address.
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config LPC54_RX_BROADCAST
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bool "Enable Rx broadcast"
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default y
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---help---
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If selected, all received frames with a broadcast destination
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address are accepted.
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config LPC54_RX_ALLMULTICAST
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bool "Accept all multicast packets"
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default y if NET_BROADCAST
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default n if !NET_BROADCAST
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---help---
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If selected, all received frames with a multicast destination
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address (first bit in the destination address field is '1') are
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accepted.
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endmenu # Ethernet configuration
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menu "SD/MMC Configuration"
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@ -99,30 +99,22 @@
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#define LPC54_ETH_MTL_INTR_STAT_OFFSET 0x0c20 /* MTL interrupt status */
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#define LPC54_ETH_MTL_RXQ_DMA_MAP_OFFSET 0x0c30 /* MTL Rx Queue and DMA channel mapping */
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#define LPC54_ETH_MTL_TXQ0_OP_MODE_OFFSET 0x0d00 /* MTL TxQ0 operation mode */
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#define LPC54_ETH_MTL_TXQ0_UNDRFLW_OFFSET 0x0d04 /* MTL TxQ0 underflow */
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#define LPC54_ETH_MTL_TXQ0_DBG_OFFSET 0x0d08 /* MTL TxQ0 debug */
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#define LPC54_ETH_MTL_TXQ0_ETS_STAT_OFFSET 0x0d14 /* MTL TxQ0 ETS status */
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#define LPC54_ETH_MTL_TXQ0_QNTM_WGHT_OFFSET 0x0d18 /* Queue 0 quantum or weights */
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#define LPC54_ETH_MTL_TXQ0_INTCTRL_STAT_OFFSET 0x0d2c /* MTL TxQ0 interrupt control status */
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#define LPC54_ETH_MTL_RXQ0_OP_MODE_OFFSET 0x0d30 /* MTL RxQ0 operation mode */
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#define LPC54_ETH_MTL_RXQ0_MISSPKT_OVRFLW_CNT_OFFSET 0x0d34 /* MTL RxQ0 missed packet overflow counter */
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#define LPC54_ETH_MTL_RXQ0_DBG_OFFSET 0x0d38 /* MTL RxQ0 debug */
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#define LPC54_ETH_MTL_RXQ0_CTRL_OFFSET 0x0d3c /* MTL RxQ0 control */
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#define LPC54_ETH_MTL_TXQ1_OP_MODE_OFFSET 0x0d40 /* MTL TxQ1 operation mode */
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#define LPC54_ETH_MTL_TXQ1_UNDRFLW_OFFSET 0x0d44 /* MTL TxQ1 underflow */
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#define LPC54_ETH_MTL_TXQ1_DBG_OFFSET 0x0d48 /* MTL TxQ1 debug */
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#define LPC54_ETH_MTL_TXQ1_ETS_CTRL_OFFSET 0x0d50 /* MTL TxQ1 ETS control */
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#define LPC54_ETH_MTL_TXQ1_ETS_STAT_OFFSET 0x0d54 /* MTL TxQ1 ETS status */
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#define LPC54_ETH_MTL_TXQ1_QNTM_WGHT_OFFSET 0x0d58 /* MTL TxQ1 quantum Weight */
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#define LPC54_ETH_MTL_TXQ1_SNDSLP_CRDT_OFFSET 0x0d5c /* MTL TxQ1 SendSlopCredit */
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#define LPC54_ETH_MTL_TXQ1_HI_CRDT_OFFSET 0x0d60 /* MTL TxQ1 hiCredit */
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#define LPC54_ETH_MTL_TXQ1_LO_CRDT_OFFSET 0x0d64 /* MTL TxQ1 loCredit */
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#define LPC54_ETH_MTL_TXQ1_INTCTRL_STAT_OFFSET 0x0d6c /* MTL TxQ1 interrupt control status */
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#define LPC54_ETH_MTL_RXQ1_OP_MODE_OFFSET 0x0d70 /* MTL RxQ1 operation mode */
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#define LPC54_ETH_MTL_RXQ1_MISSPKT_OVRFLW_CNT_OFFSET 0x0d74 /* MTL RxQ1 missed packet overflow counter */
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#define LPC54_ETH_MTL_RXQ1_DBG_OFFSET 0x0d78 /* MTL RxQ1 debug */
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#define LPC54_ETH_MTL_RXQ1_CTRL_OFFSET 0x0d7c /* MTL RxQ1 control */
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#define LPC54_ETH_MTL_Q_OFFSET(n) (0x0d00 + ((n) << 6))
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#define LPC54_ETH_MTL_TXQ_OP_MODE_OFFSET 0x0000 /* MTL TxQn operation mode */
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#define LPC54_ETH_MTL_TXQ_UNDRFLW_OFFSET 0x0004 /* MTL TxQn underflow */
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#define LPC54_ETH_MTL_TXQ_DBG_OFFSET 0x0008 /* MTL TxQn debug */
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#define LPC54_ETH_MTL_TXQ_ETS_CTRL_OFFSET 0x0010 /* MTL TxQ1 (only) ETS control */
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#define LPC54_ETH_MTL_TXQ_ETS_STAT_OFFSET 0x0014 /* MTL TxQn ETS status */
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#define LPC54_ETH_MTL_TXQ_QNTM_WGHT_OFFSET 0x0018 /* MTL TxQn quantum or weights */
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#define LPC54_ETH_MTL_TXQ_SNDSLP_CRDT_OFFSET 0x001c /* MTL TxQ1 (only) SendSlopCredit */
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#define LPC54_ETH_MTL_TXQ_HI_CRDT_OFFSET 0x0020 /* MTL TxQ1 (only) hiCredit */
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#define LPC54_ETH_MTL_TXQ_LO_CRDT_OFFSET 0x0024 /* MTL TxQ1 (only) loCredit */
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#define LPC54_ETH_MTL_TXQ_INTCTRL_STAT_OFFSET 0x002c /* MTL TxQn interrupt control status */
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#define LPC54_ETH_MTL_RXQ_OP_MODE_OFFSET 0x0030 /* MTL RxQn operation mode */
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#define LPC54_ETH_MTL_RXQ_MISSPKT_OVRFLW_CNT_OFFSET 0x0034 /* MTL RxQn missed packet overflow counter */
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#define LPC54_ETH_MTL_RXQ_DBG_OFFSET 0x0038 /* MTL RxQn debug */
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#define LPC54_ETH_MTL_RXQ_CTRL_OFFSET 0x003c /* MTL RxQn control */
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#define LPC54_ETH_DMA_MODE_OFFSET 0x1000 /* DMA mode */
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#define LPC54_ETH_DMA_SYSBUS_MODE_OFFSET 0x1004 /* DMA system bus mode */
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@ -202,30 +194,22 @@
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#define LPC54_ETH_MTL_INTR_STAT (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_INTR_STAT_OFFSET)
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#define LPC54_ETH_MTL_RXQ_DMA_MAP (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_RXQ_DMA_MAP_OFFSET)
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#define LPC54_ETH_MTL_TXQ0_OP_MODE (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ0_OP_MODE_OFFSET)
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#define LPC54_ETH_MTL_TXQ0_UNDRFLW (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ0_UNDRFLW_OFFSET)
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#define LPC54_ETH_MTL_TXQ0_DBG (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ0_DBG_OFFSET)
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#define LPC54_ETH_MTL_TXQ0_ETS_STAT (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ0_ETS_STAT_OFFSET)
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#define LPC54_ETH_MTL_TXQ0_QNTM_WGHT (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ0_QNTM_WGHT_OFFSET)
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#define LPC54_ETH_MTL_TXQ0_INTCTRL_STAT (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ0_INTCTRL_STAT_OFFSET)
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#define LPC54_ETH_MTL_RXQ0_OP_MODE (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_RXQ0_OP_MODE_OFFSET)
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#define LPC54_ETH_MTL_RXQ0_MISSPKT_OVRFLW_CNT (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_RXQ0_MISSPKT_OVRFLW_CNT_OFFSET)
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#define LPC54_ETH_MTL_RXQ0_DBG (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_RXQ0_DBG_OFFSET)
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#define LPC54_ETH_MTL_RXQ0_CTRL (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_RXQ0_CTRL_OFFSET)
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#define LPC54_ETH_MTL_TXQ1_OP_MODE (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ1_OP_MODE_OFFSET)
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#define LPC54_ETH_MTL_TXQ1_UNDRFLW (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ1_UNDRFLW_OFFSET)
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#define LPC54_ETH_MTL_TXQ1_DBG (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ1_DBG_OFFSET)
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#define LPC54_ETH_MTL_TXQ1_ETS_CTRL (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ1_ETS_CTRL_OFFSET)
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#define LPC54_ETH_MTL_TXQ1_ETS_STAT (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ1_ETS_STAT_OFFSET)
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#define LPC54_ETH_MTL_TXQ1_QNTM_WGHT (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ1_QNTM_WGHT_OFFSET)
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#define LPC54_ETH_MTL_TXQ1_SNDSLP_CRDT (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ1_SNDSLP_CRDT_OFFSET)
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#define LPC54_ETH_MTL_TXQ1_HI_CRDT (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ1_HI_CRDT_OFFSET)
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#define LPC54_ETH_MTL_TXQ1_LO_CRDT (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ1_LO_CRDT_OFFSET)
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#define LPC54_ETH_MTL_TXQ1_INTCTRL_STAT (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_TXQ1_INTCTRL_STAT_OFFSET)
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#define LPC54_ETH_MTL_RXQ1_OP_MODE (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_RXQ1_OP_MODE_OFFSET)
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#define LPC54_ETH_MTL_RXQ1_MISSPKT_OVRFLW_CNT (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_RXQ1_MISSPKT_OVRFLW_CNT_OFFSET)
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#define LPC54_ETH_MTL_RXQ1_DBG (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_RXQ1_DBG_OFFSET)
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#define LPC54_ETH_MTL_RXQ1_CTRL (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_RXQ1_CTRL_OFFSET)
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#define LPC54_ETH_MTL_Q_BASE(n) (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_Q_OFFSET(n))
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#define LPC54_ETH_MTL_TXQ_OP_MODE(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_OP_MODE_OFFSET)
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#define LPC54_ETH_MTL_TXQ_UNDRFLW(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_UNDRFLW_OFFSET)
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#define LPC54_ETH_MTL_TXQ_DBG(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_DBG_OFFSET)
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#define LPC54_ETH_MTL_TXQ_ETS_CTRL(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_ETS_CTRL_OFFSET)
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#define LPC54_ETH_MTL_TXQ_ETS_STAT(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_ETS_STAT_OFFSET)
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#define LPC54_ETH_MTL_TXQ_QNTM_WGHT(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_QNTM_WGHT_OFFSET)
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#define LPC54_ETH_MTL_TXQ_SNDSLP_CRDT(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_SNDSLP_CRDT_OFFSET)
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#define LPC54_ETH_MTL_TXQ_HI_CRDT(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_HI_CRDT_OFFSET)
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#define LPC54_ETH_MTL_TXQ_LO_CRDT(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_LO_CRDT_OFFSET)
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#define LPC54_ETH_MTL_TXQ_INTCTRL_STAT(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_INTCTRL_STAT_OFFSET)
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#define LPC54_ETH_MTL_RXQ_OP_MODE(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_RXQ_OP_MODE_OFFSET)
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#define LPC54_ETH_MTL_RXQ_MISSPKT_OVRFLW_CNT(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_RXQ_MISSPKT_OVRFLW_CNT_OFFSET)
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#define LPC54_ETH_MTL_RXQ_DBG(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_RXQ_DBG_OFFSET)
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#define LPC54_ETH_MTL_RXQ_CTRL(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_RXQ_CTRL_OFFSET)
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#define LPC54_ETH_DMA_MODE (LPC54_ETHERNET_BASE + LPC54_ETH_DMA_MODE_OFFSET)
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#define LPC54_ETH_DMA_SYSBUS_MODE (LPC54_ETHERNET_BASE + LPC54_ETH_DMA_SYSBUS_MODE_OFFSET)
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@ -259,8 +243,23 @@
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#define ETH_MAC_CONFIG_
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/* MAC extended configuration */
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#define ETH_MAC_EXT_CONFIG_
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/* MAC frame filter */
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#define ETH_MAC_FRAME_FILTER_
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#define ETH_MAC_FRAME_FILTER_PR (1 << 0) /* Bit 0: Promiscuous mode */
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#define ETH_MAC_FRAME_FILTER_DAIF (1 << 3) /* Bit 3: DA inverse filtering */
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#define ETH_MAC_FRAME_FILTER_PM (1 << 4) /* Bit 4: Pass all multicast */
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#define ETH_MAC_FRAME_FILTER_DBF (1 << 5) /* Bit 5: Disable broadcast frames */
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#define ETH_MAC_FRAME_FILTER_PCF_SHIFT (6) /* Bits 6-7: Pass control frames */
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#define ETH_MAC_FRAME_FILTER_PCF_MASK (3 << ETH_MAC_FRAME_FILTER_PCF_SHIFT)
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# define ETH_MAC_FRAME_FILTER_PCF_NONE (0 << ETH_MAC_FRAME_FILTER_PCF_SHIFT) /* All control frames filtered */
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# define ETH_MAC_FRAME_FILTER_PCF_PAUSE (1 << ETH_MAC_FRAME_FILTER_PCF_SHIFT) /* All but pause control frames accepted */
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# define ETH_MAC_FRAME_FILTER_PCF_ALL (2 << ETH_MAC_FRAME_FILTER_PCF_SHIFT) /* All control frames accepted */
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# define ETH_MAC_FRAME_FILTER_PCF_FILTERED (3 << ETH_MAC_FRAME_FILTER_PCF_SHIFT) /* Control frames accepted if pass the address filter */
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#define ETH_MAC_FRAME_FILTER_SAIF (1 << 8) /* Bit 8: SA inverse filtering */
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#define ETH_MAC_FRAME_FILTER_SAF (1 << 9) /* Bit 9: Source address filter enable */
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#define ETH_MAC_FRAME_FILTER_RA (1 << 31) /* Bit 31: Receive all */
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/* MAC watchdog timeout */
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#define ETH_MAC_WD_TIMEROUT_
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/* VLAN tag */
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@ -380,54 +379,69 @@
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/* MTL Rx Queue and DMA channel mapping */
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#define ETH_MTL_RXQ_DMA_MAP_
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/* MTL TxQ0 operation mode */
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#define ETH_MTL_TXQ0_OP_MODE_
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/* MTL TxQ0 underflow */
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#define ETH_MTL_TXQ0_UNDRFLW_
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/* MTL TxQ0 debug */
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#define ETH_MTL_TXQ0_DBG_
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/* MTL TxQ0 ETS status */
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#define ETH_MTL_TXQ0_ETS_STAT_
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/* Queue 0 quantum or weights */
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#define ETH_MTL_TXQ0_QNTM_WGHT_
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/* MTL TxQ0 interrupt control status */
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#define ETH_MTL_TXQ0_INTCTRL_STAT_
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/* MTL RxQ0 operation mode */
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#define ETH_MTL_RXQ0_OP_MODE_
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/* MTL RxQ0 missed packet overflow counter */
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#define ETH_MTL_RXQ0_MISSPKT_OVRFLW_CNT_
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/* MTL RxQ0 debug */
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#define ETH_MTL_RXQ0_DBG_
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/* MTL RxQ0 control */
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#define ETH_MTL_RXQ0_CTRL_
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/* MTL TxQ1 operation mode */
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#define ETH_MTL_TXQ1_OP_MODE_
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/* MTL TxQ1 underflow */
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#define ETH_MTL_TXQ1_UNDRFLW_
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/* MTL TxQ1 debug */
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#define ETH_MTL_TXQ1_DBG_
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/* MTL TxQ1 ETS control */
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/* MTL TxQn operation mode */
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#define ETH_MTL_TXQ_OP_MODE_FTQ (1 << 0) /* Bit 0: Flush Tx Queue */
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#define ETH_MTL_TXQ_OP_MODE_TSF (1 << 1) /* Bit 1: Transmit store and forward */
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#define ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT (2) /* Bits 2-3: Tx Queue enable */
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#define ETH_MTL_TXQ_OP_MODE_TXQEN_MASK (3 << ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT)
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# define ETH_MTL_TXQ_OP_MODE_TXQEN_ENABLE (0 << ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT) /* Not enabled */
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# define ETH_MTL_TXQ_OP_MODE_TXQEN_DISABLE (2 << ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT) /* Enabled */
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#define ETH_MTL_TXQ_OP_MODE_TTC_SHIFT (4) /* Bits 4-6: Transmit threshold control */
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#define ETH_MTL_TXQ_OP_MODE_TTC_MASK (7 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
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# define ETH_MTL_TXQ_OP_MODE_TTC_32 (0 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
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# define ETH_MTL_TXQ_OP_MODE_TTC_64 (1 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
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# define ETH_MTL_TXQ_OP_MODE_TTC_96 (2 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
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# define ETH_MTL_TXQ_OP_MODE_TTC_128 (3 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
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# define ETH_MTL_TXQ_OP_MODE_TTC_192 (4 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
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# define ETH_MTL_TXQ_OP_MODE_TTC_256 (5 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
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# define ETH_MTL_TXQ_OP_MODE_TTC_384 (6 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
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# define ETH_MTL_TXQ_OP_MODE_TTC_512 (7 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
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#define ETH_MTL_TXQ_OP_MODE_TQS_SHIFT (16) /* Bits 16-18: Tx Queue size (x256) */
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#define ETH_MTL_TXQ_OP_MODE_TQS_MASK (7 << ETH_MTL_TXQ_OP_MODE_TQS_SHIFT)
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# define ETH_MTL_TXQ_OP_MODE_TQS(n) ((uint32_t)((n)-1) << ETH_MTL_TXQ_OP_MODE_TQS_SHIFT)
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/* MTL TxQn underflow */
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#define ETH_MTL_TXQ_UNDRFLW_
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/* MTL TxQn debug */
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#define ETH_MTL_TXQ_DBG_
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/* MTL TxQ1 (only) ETS control */
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#define ETH_MTL_TXQ1_ETS_CTRL_
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/* MTL TxQ1 ETS status */
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#define ETH_MTL_TXQ1_ETS_STAT_
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/* MTL TxQ1 quantum Weight */
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#define ETH_MTL_TXQ1_QNTM_WGHT_
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/* MTL TxQ1 SendSlopCredit */
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/* MTL TxQn ETS status */
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#define ETH_MTL_TXQ_ETS_STAT_
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/* Queue 0 quantum or weights */
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#define ETH_MTL_TXQ_QNTM_WGHT_
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/* MTL TxQ1 (only) SendSlopCredit */
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#define ETH_MTL_TXQ1_SNDSLP_CRDT_
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/* MTL TxQ1 hiCredit */
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/* MTL TxQ1 (only) hiCredit */
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#define ETH_MTL_TXQ1_HI_CRDT_
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/* MTL TxQ1 loCredit */
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/* MTL TxQ1 (only) loCredit */
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#define ETH_MTL_TXQ1_LO_CRDT_
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/* MTL TxQ1 interrupt control status */
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#define ETH_MTL_TXQ1_INTCTRL_STAT_
|
||||
/* MTL RxQ1 operation mode */
|
||||
#define ETH_MTL_RXQ1_OP_MODE_
|
||||
/* MTL RxQ1 missed packet overflow counter */
|
||||
#define ETH_MTL_RXQ1_MISSPKT_OVRFLW_CNT_
|
||||
/* MTL RxQ1 debug */
|
||||
#define ETH_MTL_RXQ1_DBG_
|
||||
/* MTL RxQ1 control */
|
||||
#define ETH_MTL_RXQ1_CTRL_
|
||||
/* MTL TxQn interrupt control status */
|
||||
#define ETH_MTL_TXQ_INTCTRL_STAT_
|
||||
|
||||
/* MTL RxQn operation mode */
|
||||
|
||||
#define ETH_MTL_RXQ_OP_MODE_RTC_SHIFT (0) /* Bits 0-1: Rx Queue threshold control */
|
||||
#define ETH_MTL_RXQ_OP_MODE_RTC_MASK (3 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT)
|
||||
# define ETH_MTL_RXQ_OP_MODE_RTC_64 (0 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT)
|
||||
# define ETH_MTL_RXQ_OP_MODE_RTC_32 (1 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT)
|
||||
# define ETH_MTL_RXQ_OP_MODE_RTC_96 (2 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT)
|
||||
# define ETH_MTL_RXQ_OP_MODE_RTC_128 (3 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT)
|
||||
#define ETH_MTL_RXQ_OP_MODE_FUP (1 << 3) /* Bit 3 Forward undersized good packets */
|
||||
#define ETH_MTL_RXQ_OP_MODE_FEP (1 << 4) /* Bit 4 Forward error packets */
|
||||
#define ETH_MTL_RXQ_OP_MODE_RSF (1 << 5) /* Bit 5 Rx Queue store and forward */
|
||||
#define ETH_MTL_RXQ_OP_MODE_DIS_TCP_EF (1 << 6) /* Bit 6 Disable dropping of TCP/IP checksum error packets */
|
||||
#define ETH_MTL_RXQ_OP_MODE_RQS_SHIFT (20) /* Bits 20-22: Rx Queue size (x256) */
|
||||
#define ETH_MTL_RXQ_OP_MODE_RQS_MASK (7 << ETH_MTL_RXQ_OP_MODE_RQS_SHIFT)
|
||||
# define ETH_MTL_RXQ_OP_MODE_RQS(n) ((uint32_t)((n)-1) << ETH_MTL_RXQ_OP_MODE_RQS_SHIFT)
|
||||
|
||||
/* MTL RxQn missed packet overflow counter */
|
||||
#define ETH_MTL_RXQ_MISSPKT_OVRFLW_CNT_
|
||||
/* MTL RxQn debug */
|
||||
#define ETH_MTL_RXQ_DBG_
|
||||
/* MTL RxQn control */
|
||||
#define ETH_MTL_RXQ_CTRL_
|
||||
|
||||
/* DMA mode */
|
||||
|
||||
@ -488,8 +502,12 @@
|
||||
|
||||
#define ETH_DMACH_RX_CTRL_SR (1 << 0) /* Bit 0: Start or stop receive command */
|
||||
#define ETH_DMACH_RX_CTRL_RBSZ_SHIFT (3) /* Bits 3-14: Receive buffer size */
|
||||
#define ETH_DMACH_RX_CTRL_MASK (0xfff << ETH_DMACH_RX_CTRL_RBSZ_SHIFT)
|
||||
#define ETH_DMACH_RX_CTRL_RBSZ_MASK (0xfff << ETH_DMACH_RX_CTRL_RBSZ_SHIFT)
|
||||
# define ETH_DMACH_RX_CTRL(n) ((uint32_t)(n) << ETH_DMACH_RX_CTRL_RBSZ_SHIFT)
|
||||
#define ETH_DMACH_RX_CTRL_RxPBL_SHIFT (16) /* Bits 16-21: Receive programmable burst length */
|
||||
#define ETH_DMACH_RX_CTRL_RxPBL_MASK (0x3f << ETH_DMACH_RX_CTRL_RxPBL_SHIFT)
|
||||
# define ETH_DMACH_RX_CTRL_RxPBL(n) ((uint32_t)(n) << ETH_DMACH_RX_CTRL_RxPBL_SHIFT)
|
||||
#define ETH_DMACH_RX_CTRL_RPF (1 << 31) /* Bit 31: DMA Rx channel n packet flush */
|
||||
|
||||
/* DMA channel n Tx descriptor list address */
|
||||
#define ETH_DMACH_TXDESC_LIST_ADDR_
|
||||
|
||||
@ -110,6 +110,12 @@
|
||||
# error Unrecognized PHY selection
|
||||
#endif
|
||||
|
||||
/* MTL-related definitions */
|
||||
|
||||
#define LPC54_MTL_QUEUE_UNIT 256
|
||||
#define LPC54_MTL_RXQUEUE_UNITS 8 /* Rx queue size = 2048 bytes */
|
||||
#define LPC54_MTL_TXQUEUE_UNITS 8 /* Tx queue size = 2048 bytes */
|
||||
|
||||
/* This is a helper pointer for accessing the contents of the Ethernet header */
|
||||
|
||||
#define BUF ((struct eth_hdr_s *)priv->eth_dev.d_buf)
|
||||
@ -826,6 +832,7 @@ static void lpc54_eth_poll_expiry(int argc, wdparm_t arg, ...)
|
||||
static int lpc54_eth_ifup(FAR struct net_driver_s *dev)
|
||||
{
|
||||
FAR struct lpc54_ethdriver_s *priv = (FAR struct lpc54_ethdriver_s *)dev->d_private;
|
||||
FAR uint8_t *mptr;
|
||||
uintptr_t base;
|
||||
uint32_t regval;
|
||||
uint32_t burstlen;
|
||||
@ -843,7 +850,7 @@ static int lpc54_eth_ifup(FAR struct net_driver_s *dev)
|
||||
dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
|
||||
#endif
|
||||
|
||||
/* Initialize the PHY */
|
||||
/* Initialize the PHY *****************************************************/
|
||||
|
||||
ret = lpc54_phy_autonegotiate(priv);
|
||||
if (ret < 0)
|
||||
@ -852,8 +859,7 @@ static int lpc54_eth_ifup(FAR struct net_driver_s *dev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Initialize the Ethernet interface */
|
||||
/* Initialize Ethernet DMA */
|
||||
/* Initialize Ethernet DMA ************************************************/
|
||||
/* Reset DMA */
|
||||
|
||||
regval = getreg32(LPC54_ETH_DMA_MODE);
|
||||
@ -872,11 +878,14 @@ static int lpc54_eth_ifup(FAR struct net_driver_s *dev)
|
||||
{
|
||||
base = LPC54_ETH_DMA_CH_CTRL_BASE(i);
|
||||
|
||||
/* REVISIT: burstlen setting for the case of multi-queuing.
|
||||
* REVISIT: Additional logic needed if burstlen > 32.
|
||||
*/
|
||||
#ifdef CONFIG_LPC54_MULTIQUEUE
|
||||
/* REVISIT: burstlen setting for the case of multi-queuing. */
|
||||
# warning Missing logic
|
||||
#else
|
||||
/* REVISIT: Additional logic needed if burstlen > 32 */
|
||||
|
||||
burstlen = 1; /* DMA burst length = 1 */
|
||||
#endif
|
||||
|
||||
/* REVISIT: We would need to set ETH_DMACH_CTRL_PBLx8 in LPC54_ETH_DMACH_CTRL
|
||||
* is required for the burst length setting.
|
||||
@ -890,16 +899,100 @@ static int lpc54_eth_ifup(FAR struct net_driver_s *dev)
|
||||
putreg32(regval, base + LPC54_ETH_DMACH_TX_CTRL_OFFSET);
|
||||
|
||||
|
||||
regval = getreg(base + LPC54_ETH_DMACH_RX_CTRL_OFFSET);
|
||||
regval = getreg(base + LPC54_ETH_DMACH_RX_CTRL_OFFSET);
|
||||
regval &= ~ETH_DMACH_RX_CTRL_RxPBL_MASK;
|
||||
regval |= ETH_DMACH_RX_CTRL_RxPBL(burstlen);
|
||||
putreg32(regval, base + LPC54_ETH_DMACH_RX_CTRL_OFFSET);
|
||||
}
|
||||
|
||||
/* Initializes the Ethernet MTL */
|
||||
/* Initializes the Ethernet MTL *******************************************/
|
||||
/* Set transmit operation mode
|
||||
*
|
||||
* FTQ - Set to flush the queue
|
||||
* TSF - Depends on configuration
|
||||
* TXQEN - Queue 0 disabled; queue 1 enabled
|
||||
* TTC - Set to 32 bytes (ignored if TSF set)
|
||||
* TQS - Set to 2048 bytes
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LPC54_TX_STRFWD
|
||||
regval = ETH_MTL_TXQ_OP_MODE_TSF;
|
||||
#else
|
||||
regval = 0;
|
||||
#endif
|
||||
|
||||
regval |= ETH_MTL_TXQ_OP_MODE_FTQ | ETH_MTL_TXQ_OP_MODE_TTC_32 |
|
||||
ETH_MTL_TXQ_OP_MODE_TQS(LPC54_MTL_TXQUEUE_UNITS);
|
||||
putreg (regval | ETH_MTL_TXQ_OP_MODE_TXQEN_DISABLE,
|
||||
LPC54_ETH_MTL_TXQ_OP_MODE(0));
|
||||
putreg (regval | ETH_MTL_TXQ_OP_MODE_TXQEN_ENABLE,
|
||||
LPC54_ETH_MTL_TXQ_OP_MODE(1));
|
||||
|
||||
/* Set receive operation mode (queue 0 only)
|
||||
*
|
||||
* RTC - Set to 64 bytes (ignored if RSF selected)
|
||||
* FUP - enabled
|
||||
* FEP - disabled
|
||||
* RSF - Depends on configuration
|
||||
* DIS_TCP_EF - Not disabled
|
||||
* RQS - Set to 2048 bytes
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LPC54_RX_STRFWD
|
||||
regval = ETH_MTL_RXQ_OP_MODE_RSF;
|
||||
#else
|
||||
regval = 0;
|
||||
#endif
|
||||
|
||||
regval |= ETH_MTL_RXQ_OP_MODE_RTC_64 | ETH_MTL_RXQ_OP_MODE_FUP |
|
||||
ETH_MTL_RXQ_OP_MODE_RQS(LPC54_MTL_RXQUEUE_UNITS);
|
||||
putreg (regval, LPC54_ETH_MTL_RXQ_OP_MODE(0));
|
||||
|
||||
#ifdef CONFIG_LPC54_MULTIQUEUE
|
||||
/* Set the schedule/arbitration(set for multiple queues) */
|
||||
/* Set the rx queue mapping to dma channel */
|
||||
/* Set the tx/rx queue weight. */
|
||||
/* REVISIT: Missing multi-queue configuration here. */
|
||||
# warning Missing Logic
|
||||
#endif
|
||||
|
||||
/* Initialize the Ethernet MAC ********************************************/
|
||||
/* Instantiate the MAC address that appliation logic should have set in the
|
||||
* device structure:
|
||||
*/
|
||||
|
||||
mptr = (FAR uint8_t *)priv->eth_dev.d_mac.ether.ether_addr_octet;
|
||||
regval = ((uint32_t)mptr[3] << 24) | ((uint32_t)mptr[2] << 16) |
|
||||
((uint32_t)mptr[1] << 8) | ((uint32_t)mptr[0]);
|
||||
putreg32(regval, LPC54_ETH_MAC_ADDR_LOW);
|
||||
|
||||
regval = ((uint32_t)mptr[5] << 8) | ((uint32_t)mptr[4]);
|
||||
putreg32(regval, LPC54_ETH_MAC_ADDR_LOW);
|
||||
|
||||
/* Set the receive address filter */
|
||||
|
||||
regval = ETH_MAC_FRAME_FILTER_PCF_NONE;
|
||||
#ifdef CONFIG_LPC54_RX_PROMISCUOUS
|
||||
regval |= ETH_MAC_FRAME_FILTER_PR;
|
||||
#endif
|
||||
#ifndef CONFIG_LPC54_RX_BROADCAST
|
||||
regval |= ETH_MAC_FRAME_FILTER_DBF;
|
||||
#endif
|
||||
#ifdef CONFIG_LPC54_RX_ALLMULTICAST
|
||||
regval |= ETH_MAC_FRAME_FILTER_PM;
|
||||
#endif
|
||||
putreg32(regval, LPC54_ETH_MAC_FRAME_FILTER).
|
||||
|
||||
/* Configure flow control */
|
||||
#warning Missing logic
|
||||
|
||||
/* Initialize the Ethernet MAC */
|
||||
/* Set the 1us ticket */
|
||||
#warning Missing logic
|
||||
|
||||
/* Set the speed and duplex. */
|
||||
#warning Missing logic
|
||||
|
||||
/* Enable the Rx channel */
|
||||
#warning Missing logic
|
||||
|
||||
/* Setup up Ethernet interrupts */
|
||||
@ -908,9 +1001,6 @@ static int lpc54_eth_ifup(FAR struct net_driver_s *dev)
|
||||
/* Set the sideband flow control for each channel */
|
||||
#warning Missing logic
|
||||
|
||||
/* Instantiate the MAC address from priv->eth_dev.d_mac.ether.ether_addr_octet */
|
||||
#warning Missing logic
|
||||
|
||||
#ifdef CONFIG_NET_ICMPv6
|
||||
/* Set up IPv6 multicast address filtering */
|
||||
|
||||
@ -1664,7 +1754,7 @@ int up_netinitialize(int intf)
|
||||
|
||||
/* Set the CSR clock divider */
|
||||
|
||||
lpc43_set_crsdiv();
|
||||
lpc54_set_crsdiv();
|
||||
|
||||
/* Put the interface in the down state. This amounts to resetting the
|
||||
* device by calling lpc54_eth_ifdown().
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user