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Completes clock initialization

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2465 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2009-12-30 17:50:26 +00:00
parent a8c92fb43a
commit ebe618c07d
1 changed files with 8 additions and 5 deletions
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13
configs/ea3131/src/up_clkinit.c
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@ -234,13 +234,16 @@
* Public Data
****************************************************************************/
/* Default clock configuration for the EA3131 board
/* Default clock configuration for the EA3131 board. Every board must
* provide an implementation of g_boardclks. This rather complex structure
* is used by the boot-up logic to configure initial lpc313x clocking.
*
* FFAST: 12MHz
* MASTER PLL Freq: 180MHz;
* AUDIOPLL Freq: 1024Fs, Fs = 44.1kHz
* FFAST: 12MHz
* MASTER PLL Freq: 180MHz;
* AUDIOPLL Freq: 1024Fs, Fs = 44.1kHz
*
* Domain Input Subdomain Divider Ratio
* ------------------------ ----------------- ----------------- -------------
* 0 - DOMAIN_SYS MASTER PLL(HPLL1) DOMAIN0_DIV0 1/2
* DOMAIN0_DIV1 1
* DOMAIN0_DIV2 1/2
@ -281,7 +284,7 @@
* 11 - DOMAIN_SYSCLKO FFAST - -
*/
const struct lpc313x_clkinit_s g_cgu_default_clks =
const struct lpc313x_clkinit_s g_boardclks =
{
/* Domain 0 (DOMAINID_SYS), Clocks 0 - 29, Fraction dividers 0-6 */