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Fixes for NuTiny-NUC120 configuration and build

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5666 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2013-02-23 15:04:49 +00:00
parent 150aa31bc3
commit ec60353714
16 changed files with 330 additions and 191 deletions
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2
arch/arm/src/armv6-m/up_assert.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv6-m/up_assert.c
*
* Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without

2
arch/arm/src/armv6-m/up_copystate.c
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@ -70,7 +70,7 @@ void up_copystate(uint32_t *dest, uint32_t *src)
{
int i;
/* In the Cortex-M3 model, the state is copied from the stack to the TCB,
/* In the Cortex-M0 model, the state is copied from the stack to the TCB,
* but only a reference is passed to get the state from the TCB. So the
* following check avoids copying the TCB save area onto itself:
*/

7
arch/arm/src/armv6-m/up_exception.S
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@ -1,10 +1,13 @@
/************************************************************************************
* arch/arm/src/armv6-m/up_exception.S
*
* Copyright (C) 2009-2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2012 Michael Smith. All rights reserved.
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* This file was leveraged from the ARMv7-M version which has, in addition:
*
* Copyright (C) 2012 Michael Smith. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:

10
arch/arm/src/armv6-m/up_hardfault.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv6-m/up_hardfault.c
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -92,7 +92,6 @@ int up_hardfault(int irq, FAR void *context)
{
#if defined(CONFIG_DEBUG_HARDFAULT)
uint32_t *regs = (uint32_t*)context;
#endif
/* Dump some hard fault info */
@ -100,10 +99,6 @@ int up_hardfault(int irq, FAR void *context)
hfdbg(" IRQ: %d regs: %p\n", irq, regs);
hfdbg(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x\n",
getbasepri(), getprimask(), getipsr());
hfdbg(" CFAULTS: %08x HFAULTS: %08x DFAULTS: %08x BFAULTADDR: %08x AFAULTS: %08x\n",
getreg32(NVIC_CFAULTS), getreg32(NVIC_HFAULTS),
getreg32(NVIC_DFAULTS), getreg32(NVIC_BFAULT_ADDR),
getreg32(NVIC_AFAULTS));
hfdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
@ -112,9 +107,10 @@ int up_hardfault(int irq, FAR void *context)
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
hfdbg(" xPSR: %08x BASEPRI: %08x (saved)\n",
current_regs[REG_XPSR], current_regs[REG_BASEPRI]);
#endif
(void)irqsave();
lldbg("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS));
lldbg("PANIC!!! Hard fault\n");
PANIC(OSERR_UNEXPECTEDISR);
return OK;
}

2
arch/arm/src/armv6-m/up_initialstate.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv6-m/up_initialstate.c
*
* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without

110
arch/arm/src/armv6-m/up_memfault.c
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@ -1,110 +0,0 @@
/****************************************************************************
* arch/arm/src/armv6-m/up_memfault.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <debug.h>
#include <arch/irq.h>
#include "up_arch.h"
#include "os_internal.h"
#include "nvic.h"
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#undef DEBUG_MEMFAULTS /* Define to debug memory management faults */
#ifdef DEBUG_MEMFAULTS
# define mfdbg(format, arg...) lldbg(format, ##arg)
#else
# define mfdbg(x...)
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_memfault
*
* Description:
* This is Memory Management Fault exception handler. Normally we get here
* when the Cortex M3 MPU is enabled and an MPU fault is detected. However,
* I understand that there are other error conditions that can also generate
* memory management faults.
*
****************************************************************************/
int up_memfault(int irq, FAR void *context)
{
/* Dump some memory management fault info */
(void)irqsave();
lldbg("PANIC!!! Memory Management Fault:\n");
mfdbg(" IRQ: %d context: %p\n", irq, regs);
lldbg(" CFAULTS: %08x MMFAR: %08x\n",
getreg32(NVIC_CFAULTS), getreg32(NVIC_MEMMANAGE_ADDR));
mfdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
mfdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
mfdbg(" PSR=%08x\n", regs[REG_XPSR]);
PANIC(OSERR_UNEXPECTEDISR);
return OK;
}

2
arch/arm/src/armv6-m/up_reprioritizertr.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv6-m/up_reprioritizertr.c
*
* Copyright (C) 2007-2009, 2012-2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without

2
arch/arm/src/armv6-m/up_schedulesigaction.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv6-m/up_schedulesigaction.c
*
* Copyright (C) 2009-2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without

108
arch/arm/src/common/up_internal.h
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@ -232,75 +232,79 @@ extern uint32_t _eramfuncs; /* Copy destination start address in RAM */
/* Low level initialization provided by board-level logic ******************/
extern void up_boot(void);
void up_boot(void);
/* Context switching */
extern void up_copystate(uint32_t *dest, uint32_t *src);
extern void up_decodeirq(uint32_t *regs);
extern int up_saveusercontext(uint32_t *saveregs);
extern void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
extern void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs);
void up_copystate(uint32_t *dest, uint32_t *src);
void up_decodeirq(uint32_t *regs);
int up_saveusercontext(uint32_t *saveregs);
void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs);
/* Signal handling **********************************************************/
extern void up_sigdeliver(void);
void up_sigdeliver(void);
/* Power management *********************************************************/
#ifdef CONFIG_PM
extern void up_pminitialize(void);
void up_pminitialize(void);
#else
# define up_pminitialize()
#endif
#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
extern void up_systemreset(void) noreturn_function;
void up_systemreset(void) noreturn_function;
#endif
/* Interrupt handling *******************************************************/
extern void up_irqinitialize(void);
extern void up_maskack_irq(int irq);
void up_irqinitialize(void);
void up_maskack_irq(int irq);
#if defined(CONFIG_ARCH_CORTEXM0) || defined(CONFIG_ARCH_CORTEXM3) || \
defined(CONFIG_ARCH_CORTEXM4)
extern uint32_t *up_doirq(int irq, uint32_t *regs);
extern int up_svcall(int irq, FAR void *context);
extern int up_hardfault(int irq, FAR void *context);
extern int up_memfault(int irq, FAR void *context);
uint32_t *up_doirq(int irq, uint32_t *regs);
int up_svcall(int irq, FAR void *context);
int up_hardfault(int irq, FAR void *context);
# if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
int up_memfault(int irq, FAR void *context);
# endif /* CONFIG_ARCH_CORTEXM3 || CONFIG_ARCH_CORTEXM4 */
#else /* CONFIG_ARCH_CORTEXM0 || CONFIG_ARCH_CORTEXM3 || CONFIG_ARCH_CORTEXM4 */
extern void up_doirq(int irq, uint32_t *regs);
void up_doirq(int irq, uint32_t *regs);
#ifdef CONFIG_PAGING
extern void up_pginitialize(void);
extern uint32_t *up_va2pte(uintptr_t vaddr);
extern void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr);
void up_pginitialize(void);
uint32_t *up_va2pte(uintptr_t vaddr);
void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr);
#else /* CONFIG_PAGING */
# define up_pginitialize()
extern void up_dataabort(uint32_t *regs);
void up_dataabort(uint32_t *regs);
#endif /* CONFIG_PAGING */
extern void up_prefetchabort(uint32_t *regs);
extern void up_syscall(uint32_t *regs);
extern void up_undefinedinsn(uint32_t *regs);
void up_prefetchabort(uint32_t *regs);
void up_syscall(uint32_t *regs);
void up_undefinedinsn(uint32_t *regs);
#endif /* CONFIG_ARCH_CORTEXM3 || CONFIG_ARCH_CORTEXM4 */
extern void up_vectorundefinsn(void);
extern void up_vectorswi(void);
extern void up_vectorprefetch(void);
extern void up_vectordata(void);
extern void up_vectoraddrexcptn(void);
extern void up_vectorirq(void);
extern void up_vectorfiq(void);
void up_vectorundefinsn(void);
void up_vectorswi(void);
void up_vectorprefetch(void);
void up_vectordata(void);
void up_vectoraddrexcptn(void);
void up_vectorirq(void);
void up_vectorfiq(void);
/* Floating point unit ******************************************************/
#ifdef CONFIG_ARCH_FPU
extern void up_savefpu(uint32_t *regs);
extern void up_restorefpu(const uint32_t *regs);
void up_savefpu(uint32_t *regs);
void up_restorefpu(const uint32_t *regs);
#else
# define up_savefpu(regs)
# define up_restorefpu(regs)
@ -308,18 +312,18 @@ extern void up_restorefpu(const uint32_t *regs);
/* System timer *************************************************************/
extern void up_timerinit(void);
extern int up_timerisr(int irq, uint32_t *regs);
void up_timerinit(void);
int up_timerisr(int irq, uint32_t *regs);
/* Low level serial output **************************************************/
extern void up_lowputc(char ch);
extern void up_puts(const char *str);
extern void up_lowputs(const char *str);
void up_lowputc(char ch);
void up_puts(const char *str);
void up_lowputs(const char *str);
#if CONFIG_NFILE_DESCRIPTORS > 0
extern void up_earlyserialinit(void);
extern void up_serialinit(void);
void up_earlyserialinit(void);
void up_serialinit(void);
#else
# define up_earlyserialinit()
# define up_serialinit()
@ -328,7 +332,7 @@ extern void up_serialinit(void);
/* Defined in drivers/lowconsole.c */
#ifdef CONFIG_DEV_LOWCONSOLE
extern void lowconsole_init(void);
void lowconsole_init(void);
#else
# define lowconsole_init()
#endif
@ -336,7 +340,7 @@ extern void lowconsole_init(void);
/* DMA **********************************************************************/
#ifdef CONFIG_ARCH_DMA
extern void weak_function up_dmainitialize(void);
void weak_function up_dmainitialize(void);
#endif
/* Memory management ********************************************************/
@ -349,14 +353,14 @@ void up_addregion(void);
/* Watchdog timer ***********************************************************/
extern void up_wdtinit(void);
void up_wdtinit(void);
/* LED interfaces provided by board-level logic *****************************/
#ifdef CONFIG_ARCH_LEDS
extern void up_ledinit(void);
extern void up_ledon(int led);
extern void up_ledoff(int led);
void up_ledinit(void);
void up_ledon(int led);
void up_ledoff(int led);
#else
# define up_ledinit()
# define up_ledon(led)
@ -372,7 +376,7 @@ extern void up_ledoff(int led);
*/
#ifdef CONFIG_NET
extern void up_netinitialize(void);
void up_netinitialize(void);
#else
# define up_netinitialize()
#endif
@ -380,8 +384,8 @@ extern void up_netinitialize(void);
/* USB **********************************************************************/
#ifdef CONFIG_USBDEV
extern void up_usbinitialize(void);
extern void up_usbuninitialize(void);
void up_usbinitialize(void);
void up_usbuninitialize(void);
#else
# define up_usbinitialize()
# define up_usbuninitialize()
@ -390,7 +394,7 @@ extern void up_usbuninitialize(void);
/* Random Number Generator (RNG) ********************************************/
#ifdef CONFIG_DEV_RANDOM
extern void up_rnginitialize(void);
void up_rnginitialize(void);
#endif
/****************************************************************************
@ -410,9 +414,9 @@ extern void up_rnginitialize(void);
****************************************************************************/
#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_STACK)
extern size_t up_check_stack(void);
extern size_t up_check_tcbstack(FAR struct tcb_s);
extern size_t up_check_tcbstack_remain(FAR struct tcb_s);
size_t up_check_stack(void);
size_t up_check_tcbstack(FAR struct tcb_s);
size_t up_check_tcbstack_remain(FAR struct tcb_s);
#endif
#endif /* __ASSEMBLY__ */

208
arch/arm/src/nuc1xx/Kconfig
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@ -12,132 +12,340 @@ choice
config ARCH_CHIP_NUC100LC1BN
bool "NUC100LC1BN"
select ARCH_FAMILY_NUC100
select ARCH_NUC_LOWDENSITY
---help---
Nuvoton NUC100 low density chip: Flash 32K SRAM 4K, LQFP48 package
config ARCH_CHIP_NUC100LD1BN
bool "NUC100LD1BN"
select ARCH_FAMILY_NUC100
select ARCH_NUC_LOWDENSITY
---help---
Nuvoton NUC100 low density chip: Flash 64K SRAM 4K, LQFP48 package
config ARCH_CHIP_NUC100LD2BN
bool "NUC100LD2BN"
select ARCH_FAMILY_NUC100
select ARCH_NUC_LOWDENSITY
---help---
Nuvoton NUC100 low density chip: Flash 64K SRAM 8K, LQFP48 package
config ARCH_CHIP_NUC100RC1BN
bool "NUC100RC1BN"
select ARCH_FAMILY_NUC100
select ARCH_NUC_LOWDENSITY
---help---
Nuvoton NUC100 low density chip: Flash 32K SRAM 4K, LQFP64 package
config ARCH_CHIP_NUC100RD1BN
bool "NUC100RD1BN"
select ARCH_FAMILY_NUC100
select ARCH_NUC_LOWDENSITY
---help---
Nuvoton NUC100 low density chip: Flash 64K SRAM 4K, LQFP64 package
config ARCH_CHIP_NUC100RD2BN
bool "NUC100RD2BN"
select ARCH_FAMILY_NUC100
select ARCH_NUC_LOWDENSITY
---help---
Nuvoton NUC100 low density chip: Flash 64K SRAM 8K, LQFP64 package
config ARCH_CHIP_NUC100LD3AN
bool "NUC100LD3AN"
select ARCH_FAMILY_NUC100
select ARCH_NUC_MEDIUMDENSITY
---help---
Nuvoton NUC100 medium density chip: Flash 64K SRAM 16K, LQFP48 package
config ARCH_CHIP_NUC100LE3AN
bool "NUC100LE3AN"
select ARCH_FAMILY_NUC100
select ARCH_NUC_MEDIUMDENSITY
---help---
Nuvoton NUC100 medium density chip: Flash 128K SRAM 16K, LQFP48 package
config ARCH_CHIP_NUC100RD3AN
bool "NUC100RD3AN"
select ARCH_FAMILY_NUC100
select ARCH_NUC_MEDIUMDENSITY
select NUC_HAVE_UART2
---help---
Nuvoton NUC100 medium density chip: Flash 64K SRAM 16K, LQFP64 package
config ARCH_CHIP_NUC100RE3AN
bool "NUC100RE3AN"
select ARCH_FAMILY_NUC100
select ARCH_NUC_MEDIUMDENSITY
select NUC_HAVE_UART2
---help---
Nuvoton NUC100 medium density chip: Flash 128K SRAM 16K, LQFP64 package
config ARCH_CHIP_NUC100VD2AN
bool "NUC100VD2AN"
select ARCH_FAMILY_NUC100
select ARCH_NUC_MEDIUMDENSITY
select NUC_HAVE_UART2
---help---
Nuvoton NUC100 medium density chip: Flash 64K SRAM 8K, LQFP100 package
config ARCH_CHIP_NUC100VD3AN
bool "NUC100VD3AN"
select ARCH_FAMILY_NUC100
select ARCH_NUC_MEDIUMDENSITY
select NUC_HAVE_UART2
---help---
Nuvoton NUC100 medium density chip: Flash 64K SRAM 16K, LQFP100 package
config ARCH_CHIP_NUC100VE3AN
bool "NUC100VE3AN"
select ARCH_FAMILY_NUC100
select ARCH_NUC_MEDIUMDENSITY
select NUC_HAVE_UART2
---help---
Nuvoton NUC100 medium density chip: Flash 128K SRAM 8K, LQFP100 package
config ARCH_CHIP_NUC120LC1BN
bool "NUC120LC1BN"
select ARCH_FAMILY_NUC120
select ARCH_NUC_LOWDENSITY
---help---
Nuvoton NUC120 low density chip: Flash 32K SRAM 4K, LQFP48 package
config ARCH_CHIP_NUC120LD1BN
bool "NUC120LD1BN"
select ARCH_FAMILY_NUC120
select ARCH_NUC_LOWDENSITY
---help---
Nuvoton NUC120 low density chip: Flash 64K SRAM 4K, LQFP48 package
config ARCH_CHIP_NUC120LD2BN
bool "NUC120LD2BN"
select ARCH_FAMILY_NUC120
select ARCH_NUC_LOWDENSITY
---help---
Nuvoton NUC120 low density chip: Flash 64K SRAM 8K, LQFP48 package
config ARCH_CHIP_NUC120RC1BN
bool "NUC120RC1BN"
select ARCH_FAMILY_NUC120
select ARCH_NUC_LOWDENSITY
---help---
Nuvoton NUC120 low density chip: Flash 32K SRAM 4K, LQFP64 package
config ARCH_CHIP_NUC120RD1BN
bool "NUC120RD1BN"
select ARCH_FAMILY_NUC120
select ARCH_NUC_LOWDENSITY
---help---
Nuvoton NUC120 low density chip: Flash 64K SRAM 4K, LQFP64 package
config ARCH_CHIP_NUC120RD2BN
bool "NUC120RD2BN"
select ARCH_FAMILY_NUC120
select ARCH_NUC_LOWDENSITY
---help---
Nuvoton NUC120 low density chip: Flash 64K SRAM 8K, LQFP64 package
config ARCH_CHIP_NUC120LD3AN
bool "NUC120LD3AN"
select ARCH_FAMILY_NUC120
select ARCH_NUC_MEDIUMDENSITY
---help---
Nuvoton NUC120 medium density chip: Flash 64K SRAM 16K, LQFP48 package
config ARCH_CHIP_NUC120LE3AN
bool "NUC120LE3AN"
select ARCH_FAMILY_NUC120
select ARCH_NUC_MEDIUMDENSITY
---help---
Nuvoton NUC120 medium density chip: Flash 128K SRAM 16K, LQFP48 package
config ARCH_CHIP_NUC120RD3AN
bool "NUC120RD3AN"
select ARCH_FAMILY_NUC120
select ARCH_NUC_MEDIUMDENSITY
---help---
Nuvoton NUC120 medium density chip: Flash 64K SRAM 16K, LQFP64 package
config ARCH_CHIP_NUC120RE3AN
bool "NUC120RE3AN"
select ARCH_FAMILY_NUC120
select ARCH_NUC_MEDIUMDENSITY
---help---
Nuvoton NUC120 medium density chip: Flash 128K SRAM 16K, LQFP64 package
config ARCH_CHIP_NUC120VD2AN
bool "NUC120VD2AN"
select ARCH_FAMILY_NUC120
select ARCH_NUC_MEDIUMDENSITY
select NUC_HAVE_UART2
---help---
Nuvoton NUC120 medium density chip: Flash 64K SRAM 8K, LQFP100 package
config ARCH_CHIP_NUC120VD3AN
bool "NUC120VD3AN"
select ARCH_FAMILY_NUC120
select ARCH_NUC_MEDIUMDENSITY
select NUC_HAVE_UART2
---help---
Nuvoton NUC120 medium density chip: Flash 64K SRAM 16K, LQFP100 package
config ARCH_CHIP_NUC120VE3AN
bool "NUC120VE3AN"
select ARCH_FAMILY_NUC120
select ARCH_NUC_MEDIUMDENSITY
select NUC_HAVE_UART2
---help---
Nuvoton NUC120 medium density chip: Flash 128K SRAM 16K, LQFP100 package
endchoice
config ARCH_FAMILY_NUC100
bool
config ARCH_FAMILY_NUC120
bool
config ARCH_NUC_LOWDENSITY
bool
config ARCH_NUC_MEDIUMDENSITY
bool
config NUC_HAVE_UART2
bool
menu "NUC1XX Peripheral Support"
config NUC_PDMA
bool "Peripheral DMA"
default n
config NUC_FMC
bool "Flash memory"
default n
config NUC_EBI
bool "External bus interface"
default n
config NUC_WDT
bool "Watchdog timer"
default n
config NUC_RTC
bool "Real time clock (RTC)"
default n
config NUC_TMR0
bool "Timer0"
default n
config NUC_TMR1
bool "Timer1"
default n
config NUC_TIMR2
bool "Timer2"
default n
config NUC_TIMR3
bool "Timer3"
default n
config NUC_I2C0
bool "I2C0 interface"
default n
config NUC_I2C1
bool "I2C1 interface"
default n
config NUC_SPI0
bool "SPI0 master/slave"
default n
config NUC_SPI1
bool "SPI1 master/slave"
default n
config NUC_SPI2
bool "SPI2 master/slave"
default n
config NUC_SPI3
bool "SPI3 master/slave"
default n
config NUC_PWM0
bool "PWM0"
default n
config NUC_PWM1
bool "PWM1"
default n
config NUC_PWM2
bool "PWM2"
default n
config NUC_PWM3
bool "PWM3"
default n
config NUC_PWM4
bool "PWM4"
default n
config NUC_PWM5
bool "PWM5"
default n
config NUC_PWM6
bool "PWM6"
default n
config NUC_PWM7
bool "PWM7"
default n
config NUC_UART0
bool "UART0"
default y
select ARCH_HAVE_UART0
config NUC_UART1
bool "UART1"
default n
select ARCH_HAVE_UART1
config NUC_UART2
bool "UART2"
default n
depends on NUC_HAVE_UART1
select ARCH_HAVE_UART2
config NUC_USBD
bool "USB 2.0 FS device controller"
default n
depends on ARCH_FAMILY_NUC120
config NUC_ACMP
bool "Analog comparator"
default n
config NUC_ADC
bool "Analog-digital-converter (ADC)"
default n
config NUC_PS2
bool "PS/2 interface"
default n
config NUC_I2S
bool "I2S interface"
default n
endmenu

2
arch/arm/src/nuc1xx/Make.defs
View File

@ -41,7 +41,7 @@ CMN_ASRCS += up_switchcontext.S vfork.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c
CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
CMN_CSRCS += up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_systemreset.c
CMN_CSRCS += up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c

1
arch/arm/src/nuc1xx/nuc_config.h
View File

@ -41,6 +41,7 @@
************************************************************************************/
#include <nuttx/config.h>
#include <arch/nuc1xx/chip.h>
/************************************************************************************
* Pre-processor Definitions

36
arch/arm/src/nuc1xx/nuc_lowputc.c
View File

@ -52,6 +52,7 @@
#include "chip/chip/nuc_clk.h"
#include "chip/chip/nuc_uart.h"
#include "chip/nuc_gcr.h"
#include "nuc_lowputc.h"
/****************************************************************************
@ -205,14 +206,14 @@ void nuc_lowsetup(void)
/* Reset the TX FIFO */
regval = getreg32(NUC_CONSOLE_BASE + NUC_UART_FCR_OFFSET
regval |= UART_FCR_TFR
regval = getreg32(NUC_CONSOLE_BASE + NUC_UART_FCR_OFFSET);
regval |= UART_FCR_TFR;
putreg32(regval, NUC_CONSOLE_BASE + NUC_UART_FCR_OFFSET);
/* Reset the RX FIFO */
regval = getreg32(NUC_CONSOLE_BASE + NUC_UART_FCR_OFFSET
regval |= UART_FCR_RFR
regval = getreg32(NUC_CONSOLE_BASE + NUC_UART_FCR_OFFSET);
regval |= UART_FCR_RFR;
putreg32(regval, NUC_CONSOLE_BASE + NUC_UART_FCR_OFFSET);
/* Set Rx Trigger Level */
@ -256,12 +257,33 @@ void nuc_lowsetup(void)
/* Set the baud */
nuc_setbaud(CONSOLE_BASE, CONSOLE_BAUD);
nuc_setbaud(NUC_CONSOLE_BASE, NUC_CONSOLE_BAUD);
#endif /* HAVE_SERIAL_CONSOLE */
#endif /* HAVE_UART */
}
/****************************************************************************
* Name: nuc_lowputc
*
* Description:
* Output one character to the UART using a simple polling method.
*
*****************************************************************************/
void nuc_lowputc(uint32_t ch)
{
#ifdef HAVE_SERIAL_CONSOLE
/* Wait for the TX FIFO to be empty (excessive!) */
while ((getreg32(NUC_CONSOLE_BASE + NUC_UART_FSR_OFFSET) & UART_FSR_TX_EMPTY) != 0);
/* Then write the character to to the TX FIFO */
putreg32(ch, NUC_CONSOLE_BASE + NUC_UART_THR_OFFSET);
#endif /* HAVE_SERIAL_CONSOLE */
}
/****************************************************************************
* Name: nuc_setbaud
*
@ -317,7 +339,7 @@ void nuc_setbaud(uintptr_t base, uint32_t baud)
for (divx = 8; divx <16; divx++)
{
brd = (clksperbit % (divx+1))
brd = (clksperbit % (divx+1));
if (brd < 3)
{
regval &= ~UART_BAUD_DIVIDER_X_MASK;
@ -331,7 +353,7 @@ void nuc_setbaud(uintptr_t base, uint32_t baud)
}
regval &= ~UART_BAUD_BRD_MASK;
regval &= define UART_BAUD_BRD(brd);
regval |= UART_BAUD_BRD(brd);
putreg32(regval, base + NUC_UART_BAUD_OFFSET);
}

15
arch/arm/src/nuc1xx/nuc_lowputc.h
View File

@ -41,6 +41,7 @@
************************************************************************************/
#include <nuttx/config.h>
#include "nuc_config.h"
/************************************************************************************
* Pre-processor Definitions
@ -97,7 +98,19 @@ void nuc_lowsetup(void);
*****************************************************************************/
#ifdef HAVE_UART
void nuc_setbaud(uintptr_t base, uint32_t baud)
void nuc_setbaud(uintptr_t base, uint32_t baud);
#endif
/****************************************************************************
* Name: nuc_lowputc
*
* Description:
* Output one character to the UART using a simple polling method.
*
*****************************************************************************/
#ifdef HAVE_SERIAL_CONSOLE
void nuc_lowputc(uint32_t ch);
#endif
#undef EXTERN

9
arch/arm/src/nuc1xx/nuc_serial.c
View File

@ -65,6 +65,7 @@
#include "chip.h"
#include "chip/nuc_uart.h"
#include "nuc_lowputc.h"
#include "nuc_serial.h"
/****************************************************************************
@ -935,10 +936,10 @@ int up_putc(int ch)
{
/* Add CR */
up_lowputc('\r');
nuc_lowputc((uint32_t)'\r');
}
up_lowputc(ch);
nuc_lowputc((uint32_t)ch);
#ifdef HAVE_CONSOLE
up_restoreuartint(priv, ier);
#endif
@ -965,10 +966,10 @@ int up_putc(int ch)
{
/* Add CR */
up_lowputc('\r');
nuc_lowputc((uint32_t)'\r');
}
up_lowputc(ch);
nuc_lowputc((uint32_t)ch);
#endif
return ch;
}

5
arch/arm/src/nuc1xx/nuc_start.c
View File

@ -50,6 +50,7 @@
#include "up_arch.h"
#include "up_internal.h"
#include "nuc_config.h"
#include "nuc_lowputc.h"
#include "nuc_clockconfig.h"
@ -90,8 +91,8 @@ const uint32_t g_heapbase = HEAP_BASE;
*
****************************************************************************/
#ifdef CONFIG_DEBUG
# define showprogress(c) up_lowputc(c)
#if defined(CONFIG_DEBUG) && defined(HAVE_SERIAL_CONSOLE)
# define showprogress(c) nuc_lowputc((uint32_t)c)
#else
# define showprogress(c)
#endif