diff --git a/ChangeLog b/ChangeLog index 55dcf0da8a..cb81775a28 100644 --- a/ChangeLog +++ b/ChangeLog @@ -2860,4 +2860,9 @@ not be initialized (F2 and F4 only). Thus, the very high numbered interrupts (like UART6) and cause nested interrupts. This leads to some very difficult to debug crashes. Fix contributed by Mike Smith. + * arch/mips/src/pic32/pic32_head.S and pic32_config.h and + configs/pic32mx7mmb/include/board.h: Extended PIC32 device configuration + capabilities and change board.h to support unique clocking requirements + of the Mikroelektronika PIC32MX7 MMB. That board now works! + diff --git a/arch/mips/src/pic32mx/pic32mx-config.h b/arch/mips/src/pic32mx/pic32mx-config.h index 58b44017f8..4ef88508d3 100644 --- a/arch/mips/src/pic32mx/pic32mx-config.h +++ b/arch/mips/src/pic32mx/pic32mx-config.h @@ -729,6 +729,18 @@ /* DEVCFG1 */ +#ifdef BOARD_SOSC_ENABLE +# define CONFIG_PIC32MX_FSOSCEN DEVCFG1_FSOSCEN +#else +# define CONFIG_PIC32MX_FSOSCEN 0 +#endif + +#ifdef BOARD_SOSC_IESO +# define CONFIG_PIC32MX_IESO DEVCFG1_IESO +#else +# define CONFIG_PIC32MX_IESO 0 +#endif + #undef CONFIG_PIC32MX_PBDIV #if BOARD_PBDIV == 1 # define CONFIG_PIC32MX_PBDIV DEVCFG1_FPBDIV_DIV1 @@ -742,6 +754,30 @@ # error "Unsupported BOARD_PBDIV" #endif +#undef CONFIG_PIC32MX_POSCMOD +#if defined(BOARD_POSC_ECMODE) +# define CONFIG_PIC32MX_POSCMOD DEVCFG1_POSCMOD_EC +#elif defined(BOARD_POSC_XTMODE) +# define CONFIG_PIC32MX_POSCMOD DEVCFG1_POSCMOD_XT +#elif defined(BOARD_POSC_HSMODE) +# define CONFIG_PIC32MX_POSCMOD DEVCFG1_POSCMOD_HS +#elif defined(BOARD_POSC_DISABLED) +# define CONFIG_PIC32MX_POSCMOD DEVCFG1_POSCMOD_DIS +#else +# error "Unknown board POSC mode" +#endif + +#undef CONFIG_PIC32MX_FCKSM +#if defined(BOARD_POSC_SWITCH) +# if defined(BOARD_POSC_FSCM) +# define CONFIG_PIC32MX_FCKSM DEVCFG1_FCKSM_BOTH +# else +# define CONFIG_PIC32MX_FCKSM DEVCFG1_FCKSM_CSONLY +# endif +#else +# define CONFIG_PIC32MX_FCKSM DEVCFG1_FCKSM_NONE +#endif + #undef CONFIG_PIC32MX_WDPS #if BOARD_WD_PRESCALER == 1 # define CONFIG_PIC32MX_WDPS DEVCFG1_WDTPS_1 diff --git a/arch/mips/src/pic32mx/pic32mx-head.S b/arch/mips/src/pic32mx/pic32mx-head.S index a0a7757900..9d610aedd7 100644 --- a/arch/mips/src/pic32mx/pic32mx-head.S +++ b/arch/mips/src/pic32mx/pic32mx-head.S @@ -610,8 +610,9 @@ devconfig2: DEVCFG2_UNUSED devconfig1: - .long DEVCFG1_FNOSC_POSCPLL | DEVCFG1_POSCMOD_HS | \ - CONFIG_PIC32MX_PBDIV | DEVCFG1_FCKSM_NONE | \ + .long DEVCFG1_FNOSC_POSCPLL | CONFIG_PIC32MX_FSOSCEN | \ + CONFIG_PIC32MX_IESO | CONFIG_PIC32MX_POSCMOD | \ + CONFIG_PIC32MX_PBDIV | CONFIG_PIC32MX_FCKSM | \ CONFIG_PIC32MX_WDENABLE | DEVCFG1_UNUSED devconfig0: diff --git a/configs/pcblogic-pic32mx/include/board.h b/configs/pcblogic-pic32mx/include/board.h index 839d3108c0..a47f989b76 100644 --- a/configs/pcblogic-pic32mx/include/board.h +++ b/configs/pcblogic-pic32mx/include/board.h @@ -2,7 +2,7 @@ * configs/pcblogic-pic32mx/include/board.h * include/arch/board/board.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -53,6 +53,7 @@ #define BOARD_POSC_FREQ 8000000 /* Primary OSC XTAL frequency (8MHz) */ #define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */ +#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */ /* PLL configuration and resulting CPU clock. * CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV diff --git a/configs/pic32-starterkit/include/board.h b/configs/pic32-starterkit/include/board.h index 043c166942..5b2880c77e 100644 --- a/configs/pic32-starterkit/include/board.h +++ b/configs/pic32-starterkit/include/board.h @@ -57,6 +57,7 @@ #define BOARD_POSC_FREQ 8000000 /* Primary OSC XTAL frequency (8MHz) */ #define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */ +#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */ /* PLL configuration and resulting CPU clock. * CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV diff --git a/configs/pic32mx7mmb/include/board.h b/configs/pic32mx7mmb/include/board.h index 5c38867c87..a0a1615537 100644 --- a/configs/pic32mx7mmb/include/board.h +++ b/configs/pic32mx7mmb/include/board.h @@ -58,6 +58,14 @@ #define BOARD_POSC_FREQ 8000000 /* Primary OSC XTAL frequency (8MHz) */ #define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */ +/* Clock modes */ + +#define BOARD_POSC_XTMODE 1 /* Resonator, crystal or resonator (XT) mode */ +#undef BOARD_POSC_SWITCH /* Use FRC until POSC stabilizes, then switch */ +#undef BOARD_POSC_FSCM /* Switch to FRC if POSC fails */ +#define BOARD_SOSC_ENABLE 1 /* Enable Secondary Oscillator */ +#define BOARD_SOSC_IESO 1 /* Internal External Switchover mode is enabled */ + /* PLL configuration and resulting CPU clock. * CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV */ @@ -79,8 +87,8 @@ * PBCLOCK = CPU_CLOCK / PBDIV */ -#define BOARD_PBDIV 2 /* Peripheral clock divisor (PBDIV) */ -#define BOARD_PBCLOCK 40000000 /* Peripheral clock (PBCLK = 80MHz/2) */ +#define BOARD_PBDIV 1 /* Peripheral clock divisor (PBDIV) */ +#define BOARD_PBCLOCK 80000000 /* Peripheral clock (PBCLK = 80MHz/1) */ /* Watchdog pre-scaler (re-visit) */ diff --git a/configs/sure-pic32mx/include/board.h b/configs/sure-pic32mx/include/board.h index 66ed642c64..7521c694ee 100644 --- a/configs/sure-pic32mx/include/board.h +++ b/configs/sure-pic32mx/include/board.h @@ -53,6 +53,7 @@ #define BOARD_POSC_FREQ 20000000 /* Primary OSC XTAL frequency (20MHz) */ #define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */ +#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */ /* PLL configuration and resulting CPU clock. * CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV diff --git a/configs/ubw32/include/board.h b/configs/ubw32/include/board.h index 6fb5dfcd28..da8ecc50ca 100644 --- a/configs/ubw32/include/board.h +++ b/configs/ubw32/include/board.h @@ -54,6 +54,7 @@ #define BOARD_POSC_FREQ 8000000 /* Primary OSC XTAL frequency (8MHz) */ #define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) * (Not present on my board) */ +#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */ /* PLL configuration and resulting CPU clock. * CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV