arch/arm: Add RP2040 (Raspberry Pi Pico's SoC) support
This commit is contained in:
Yuichi Nakamura
Xiang Xiao
parent
37d5c1b0d9
commit
ed1da60f52
@ -225,6 +225,13 @@ config ARCH_CHIP_NUC1XX
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---help---
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Nuvoton NUC100/120 architectures (ARM Cortex-M0).
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config ARCH_CHIP_RP2040
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bool "Raspberry Pi RP2040"
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select ARCH_CORTEXM0
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select ARCH_HAVE_RAMVECTORS
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---help---
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Raspberry Pi RP2040 architectures (ARM Cortex-M0+).
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config ARCH_CHIP_S32K1XX
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bool "NXP S32K1XX"
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select ARCH_HAVE_MPU
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@ -746,6 +753,7 @@ config ARCH_CHIP
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default "moxart" if ARCH_CHIP_MOXART
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default "nrf52" if ARCH_CHIP_NRF52
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default "nuc1xx" if ARCH_CHIP_NUC1XX
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default "rp2040" if ARCH_CHIP_RP2040
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default "s32k1xx" if ARCH_CHIP_S32K1XX
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default "sama5" if ARCH_CHIP_SAMA5
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default "samd2l2" if ARCH_CHIP_SAMD2X || ARCH_CHIP_SAML2X
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@ -982,6 +990,9 @@ endif
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if ARCH_CHIP_NUC1XX
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source arch/arm/src/nuc1xx/Kconfig
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endif
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if ARCH_CHIP_RP2040
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source arch/arm/src/rp2040/Kconfig
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endif
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if ARCH_CHIP_SAMA5
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source arch/arm/src/sama5/Kconfig
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endif
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37
arch/arm/include/rp2040/chip.h
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37
arch/arm/include/rp2040/chip.h
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@ -0,0 +1,37 @@
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/****************************************************************************
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* arch/arm/include/rp2040/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_RP2040_CHIP_H
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#define __ARCH_ARM_INCLUDE_RP2040_CHIP_H
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds a priority value, 0-3. The lower the value,
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* the greater the priority of the corresponding interrupt. The processor
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* implements only bits[7:6] of each field, bits[5:0] read as zero and ignore
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* writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Five bits of interrupt priority used */
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#endif /* __ARCH_ARM_INCLUDE_RP2040_CHIP_H */
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124
arch/arm/include/rp2040/irq.h
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124
arch/arm/include/rp2040/irq.h
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@ -0,0 +1,124 @@
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/****************************************************************************
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* arch/arm/include/rp2040/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_RP2040_IRQ_H
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#define __ARCH_ARM_INCLUDE_RP2040_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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*/
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/* Processor Exceptions (vectors 0-15) */
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#define RP2040_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define RP2040_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define RP2040_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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/* Vector 4-10: Reserved */
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#define RP2040_IRQ_SVCALL (11) /* Vector 11: SVC call */
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/* Vector 12-13: Reserved */
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#define RP2040_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define RP2040_IRQ_SYSTICK (15) /* Vector 15: System tick */
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#define RP2040_IRQ_EXTINT (16) /* Vector 16: Vector number of the first external interrupt */
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/* External interrupts (vectors >= 16). These definitions are
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* chip-specific
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*/
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#define RP2040_TIMER_IRQ_0 (RP2040_IRQ_EXTINT+0)
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#define RP2040_TIMER_IRQ_1 (RP2040_IRQ_EXTINT+1)
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#define RP2040_TIMER_IRQ_2 (RP2040_IRQ_EXTINT+2)
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#define RP2040_TIMER_IRQ_3 (RP2040_IRQ_EXTINT+3)
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#define RP2040_PWM_IRQ_WRAP (RP2040_IRQ_EXTINT+4)
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#define RP2040_USBCTRL_IRQ (RP2040_IRQ_EXTINT+5)
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#define RP2040_XIP_IRQ (RP2040_IRQ_EXTINT+6)
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#define RP2040_PIO0_IRQ_0 (RP2040_IRQ_EXTINT+7)
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#define RP2040_PIO0_IRQ_1 (RP2040_IRQ_EXTINT+8)
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#define RP2040_PIO1_IRQ_0 (RP2040_IRQ_EXTINT+9)
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#define RP2040_PIO1_IRQ_1 (RP2040_IRQ_EXTINT+10)
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#define RP2040_DMA_IRQ_0 (RP2040_IRQ_EXTINT+11)
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#define RP2040_DMA_IRQ_1 (RP2040_IRQ_EXTINT+12)
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#define RP2040_IO_IRQ_BANK0 (RP2040_IRQ_EXTINT+13)
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#define RP2040_IO_IRQ_QSPI (RP2040_IRQ_EXTINT+14)
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#define RP2040_SIO_IRQ_PROC0 (RP2040_IRQ_EXTINT+15)
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#define RP2040_SIO_IRQ_PROC1 (RP2040_IRQ_EXTINT+16)
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#define RP2040_CLOCKS_IRQ (RP2040_IRQ_EXTINT+17)
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#define RP2040_SPI0_IRQ (RP2040_IRQ_EXTINT+18)
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#define RP2040_SPI1_IRQ (RP2040_IRQ_EXTINT+19)
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#define RP2040_UART0_IRQ (RP2040_IRQ_EXTINT+20)
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#define RP2040_UART1_IRQ (RP2040_IRQ_EXTINT+21)
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#define RP2040_ADC_IRQ_FIFO (RP2040_IRQ_EXTINT+22)
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#define RP2040_I2C0_IRQ (RP2040_IRQ_EXTINT+23)
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#define RP2040_I2C1_IRQ (RP2040_IRQ_EXTINT+24)
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#define RP2040_RTC_IRQ (RP2040_IRQ_EXTINT+25)
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#define RP2040_IRQ_NEXTINT (32)
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#define RP2040_IRQ_NIRQS (RP2040_IRQ_EXTINT+RP2040_IRQ_NEXTINT)
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#define NR_VECTORS RP2040_IRQ_NIRQS
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#define NR_IRQS RP2040_IRQ_NIRQS
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_INCLUDE_RP2040_IRQ_H */
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74
arch/arm/src/rp2040/Kconfig
Normal file
74
arch/arm/src/rp2040/Kconfig
Normal file
@ -0,0 +1,74 @@
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#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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comment "RP2040 Configuration Options"
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config RP2040_UART0
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bool "UART0"
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default y
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select UART0_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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if RP2040_UART0
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config RP2040_UART0_BAUD
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int "RP2040 UART0 BAUD"
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default 115200
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config RP2040_UART0_PARITY
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int "RP2040 UART0 parity"
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default 0
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range 0 2
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---help---
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RP2040 UART0 parity. 0=None, 1=Odd, 2=Even. Default: None
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config RP2040_UART0_BITS
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int "RP2040 UART0 number of bits"
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default 8
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range 5 8
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---help---
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RP2040 UART0 number of bits. Default: 8
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config RP2040_UART0_2STOP
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int "RP2040 UART0 two stop bits"
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default 0
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---help---
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0=1 stop bit, 1=Two stop bits. Default: 1 stop bit
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endif
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config RP2040_UART1
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bool "UART1"
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default n
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select UART1_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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if RP2040_UART1
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config RP2040_UART1_BAUD
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int "RP2040 UART1 BAUD"
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default 115200
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config RP2040_UART1_PARITY
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int "RP2040 UART1 parity"
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default 0
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range 0 2
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---help---
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RP2040 UART1 parity. 0=None, 1=Odd, 2=Even. Default: None
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config RP2040_UART1_BITS
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int "RP2040 UART1 number of bits"
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default 8
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range 5 8
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---help---
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RP2040 UART1 number of bits. Default: 8
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config RP2040_UART1_2STOP
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int "RP2040 UART1 two stop bits"
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default 0
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---help---
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0=1 stop bit, 1=Two stop bits. Default: 1 stop bit
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endif
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68
arch/arm/src/rp2040/Make.defs
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68
arch/arm/src/rp2040/Make.defs
Normal file
@ -0,0 +1,68 @@
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############################################################################
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# arch/arm/src/rp2040/Make.defs
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#
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# Licensed to the Apache Software Foundation (ASF) under one or more
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# contributor license agreements. See the NOTICE file distributed with
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# this work for additional information regarding copyright ownership. The
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# ASF licenses this file to you under the Apache License, Version 2.0 (the
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# "License"); you may not use this file except in compliance with the
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# License. You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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#
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############################################################################
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CMN_ASRCS = arm_exception.S arm_saveusercontext.S arm_fullcontextrestore.S
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CMN_ASRCS += arm_switchcontext.S vfork.S
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CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c arm_copyfullstate.c
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CMN_CSRCS += arm_createstack.c arm_mdelay.c arm_udelay.c arm_exit.c
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CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
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CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
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CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
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CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
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CMN_CSRCS += arm_systemreset.c arm_unblocktask.c arm_usestack.c arm_doirq.c
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CMN_CSRCS += arm_hardfault.c arm_svcall.c arm_vectors.c arm_vfork.c
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ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
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CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
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endif
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ifeq ($(CONFIG_BUILD_PROTECTED),y)
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CMN_CSRCS += arm_task_start.c arm_pthread_start.c
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CMN_CSRCS += arm_signal_dispatch.c
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CMN_UASRCS += arm_signal_handler.S
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endif
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ifeq ($(CONFIG_STACK_COLORATION),y)
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CMN_CSRCS += arm_checkstack.c
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endif
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ifeq ($(CONFIG_DEBUG_FEATURES),y)
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CMN_CSRCS += arm_dumpnvic.c
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endif
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CHIP_CSRCS += rp2040_idle.c
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CHIP_CSRCS += rp2040_irq.c
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CHIP_CSRCS += rp2040_uart.c
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CHIP_CSRCS += rp2040_serial.c
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CHIP_CSRCS += rp2040_start.c
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CHIP_CSRCS += rp2040_timerisr.c
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CHIP_CSRCS += rp2040_gpio.c
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CHIP_CSRCS += rp2040_clock.c
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CHIP_CSRCS += rp2040_xosc.c
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CHIP_CSRCS += rp2040_pll.c
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ifneq ($(PICO_SDK_PATH),)
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include chip/boot2/Make.defs
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else
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ifeq ($(CONFIG_RP2040_FLASH_BOOT),y)
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$(error $$(PICO_SDK_PATH) must be specified for flash boot)
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endif
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endif
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66
arch/arm/src/rp2040/chip.h
Normal file
66
arch/arm/src/rp2040/chip.h
Normal file
@ -0,0 +1,66 @@
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/****************************************************************************
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* arch/arm/src/rp2040/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
|
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
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* "License"); you may not use this file except in compliance with the
|
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* License. You may obtain a copy of the License at
|
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
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* License for the specific language governing permissions and limitations
|
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* under the License.
|
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_RP2040_CHIP_H
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#define __ARCH_ARM_SRC_RP2040_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <nuttx/arch.h>
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#endif
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/* Include the chip capabilities file */
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#include <arch/rp2040/chip.h>
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/* Define the number of interrupt vectors that need to be supported for
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* this chip
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*/
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#define ARMV6M_PERIPHERAL_INTERRUPTS 32
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/* Include the memory map file. Other chip hardware files should then
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* include this file for the proper setup.
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*/
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#include "hardware/rp2040_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_RP2040_CHIP_H */
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544
arch/arm/src/rp2040/hardware/rp2040_clocks.h
Normal file
544
arch/arm/src/rp2040/hardware/rp2040_clocks.h
Normal file
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/****************************************************************************
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* arch/arm/src/rp2040/hardware/rp2040_clocks.h
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*
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* Generated from rp2040.svd originally provided by
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* Raspberry Pi (Trading) Ltd.
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*
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* Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_CLOCKS_H
|
||||
#define __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_CLOCKS_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hardware/rp2040_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Clock index **************************************************************/
|
||||
|
||||
#define RP2040_CLOCKS_NDX_GPOUT0 0 /* Clock output to GPIO 21 */
|
||||
#define RP2040_CLOCKS_NDX_GPOUT1 1 /* Clock output to GPIO 23 */
|
||||
#define RP2040_CLOCKS_NDX_GPOUT2 2 /* Clock output to GPIO 24 */
|
||||
#define RP2040_CLOCKS_NDX_GPOUT3 3 /* Clock output to GPIO 25 */
|
||||
#define RP2040_CLOCKS_NDX_REF 4 /* Reference clock */
|
||||
#define RP2040_CLOCKS_NDX_SYS 5 /* System clock */
|
||||
#define RP2040_CLOCKS_NDX_PERI 6 /* Peripheral clock */
|
||||
#define RP2040_CLOCKS_NDX_USB 7 /* USB clock */
|
||||
#define RP2040_CLOCKS_NDX_ADC 8 /* ADC clock */
|
||||
#define RP2040_CLOCKS_NDX_RTC 9 /* RTC clock */
|
||||
#define RP2040_CLOCKS_NDX_MAX 10
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define RP2040_CLOCKS_CLK_CTRL_OFFSET 0x000000 /* Clock control */
|
||||
#define RP2040_CLOCKS_CLK_DIV_OFFSET 0x000004 /* Clock divisor */
|
||||
#define RP2040_CLOCKS_CLK_SELECTED_OFFSET 0x000008 /* Indicates which src is currently selected */
|
||||
|
||||
#define RP2040_CLOCKS_CLK_NDX_CTRL_OFFSET(n) ((n) * 12 + RP2040_CLOCKS_CLK_CTRL_OFFSET)
|
||||
#define RP2040_CLOCKS_CLK_NDX_DIV_OFFSET(n) ((n) * 12 + RP2040_CLOCKS_CLK_DIV_OFFSET)
|
||||
#define RP2040_CLOCKS_CLK_NDX_SELECTED_OFFSET(n) ((n) * 12 + RP2040_CLOCKS_CLK_SELECTED_OFFSET)
|
||||
|
||||
#define RP2040_CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET 0x000078
|
||||
#define RP2040_CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET 0x00007c
|
||||
#define RP2040_CLOCKS_FC0_REF_KHZ_OFFSET 0x000080 /* Reference clock frequency in kHz */
|
||||
#define RP2040_CLOCKS_FC0_MIN_KHZ_OFFSET 0x000084 /* Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags */
|
||||
#define RP2040_CLOCKS_FC0_MAX_KHZ_OFFSET 0x000088 /* Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags */
|
||||
#define RP2040_CLOCKS_FC0_DELAY_OFFSET 0x00008c /* Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period */
|
||||
#define RP2040_CLOCKS_FC0_INTERVAL_OFFSET 0x000090 /* The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us */
|
||||
#define RP2040_CLOCKS_FC0_SRC_OFFSET 0x000094 /* Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count */
|
||||
#define RP2040_CLOCKS_FC0_STATUS_OFFSET 0x000098 /* Frequency counter status */
|
||||
#define RP2040_CLOCKS_FC0_RESULT_OFFSET 0x00009c /* Result of frequency measurement, only valid when status_done=1 */
|
||||
#define RP2040_CLOCKS_WAKE_EN0_OFFSET 0x0000a0 /* enable clock in wake mode */
|
||||
#define RP2040_CLOCKS_WAKE_EN1_OFFSET 0x0000a4 /* enable clock in wake mode */
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_OFFSET 0x0000a8 /* enable clock in sleep mode */
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_OFFSET 0x0000ac /* enable clock in sleep mode */
|
||||
#define RP2040_CLOCKS_ENABLED0_OFFSET 0x0000b0 /* indicates the state of the clock enable */
|
||||
#define RP2040_CLOCKS_ENABLED1_OFFSET 0x0000b4 /* indicates the state of the clock enable */
|
||||
#define RP2040_CLOCKS_INTR_OFFSET 0x0000b8 /* Raw Interrupts */
|
||||
#define RP2040_CLOCKS_INTE_OFFSET 0x0000bc /* Interrupt Enable */
|
||||
#define RP2040_CLOCKS_INTF_OFFSET 0x0000c0 /* Interrupt Force */
|
||||
#define RP2040_CLOCKS_INTS_OFFSET 0x0000c4 /* Interrupt status after masking & forcing */
|
||||
|
||||
/* Register definitions *****************************************************/
|
||||
|
||||
#define RP2040_CLOCKS_CLK_NDX_CTRL(n) (RP2040_CLOCKS_BASE + RP2040_CLOCKS_CLK_NDX_CTRL_OFFSET(n))
|
||||
#define RP2040_CLOCKS_CLK_NDX_DIV(n) (RP2040_CLOCKS_BASE + RP2040_CLOCKS_CLK_NDX_DIV_OFFSET(n))
|
||||
#define RP2040_CLOCKS_CLK_NDX_SELECTED(n) (RP2040_CLOCKS_BASE + RP2040_CLOCKS_CLK_NDX_SELECTED_OFFSET(n))
|
||||
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL (RP2040_CLOCKS_CLK_NDX_CTRL(RP2040_CLOCKS_NDX_GPOUT0))
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_DIV (RP2040_CLOCKS_CLK_NDX_DIV(RP2040_CLOCKS_NDX_GPOUT0))
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_SELECTED (RP2040_CLOCKS_CLK_NDX_SELECTED(RP2040_CLOCKS_NDX_GPOUT0))
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL (RP2040_CLOCKS_CLK_NDX_CTRL(RP2040_CLOCKS_NDX_GPOUT1))
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_DIV (RP2040_CLOCKS_CLK_NDX_DIV(RP2040_CLOCKS_NDX_GPOUT1))
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_SELECTED (RP2040_CLOCKS_CLK_NDX_SELECTED(RP2040_CLOCKS_NDX_GPOUT1))
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL (RP2040_CLOCKS_CLK_NDX_CTRL(RP2040_CLOCKS_NDX_GPOUT2))
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_DIV (RP2040_CLOCKS_CLK_NDX_DIV(RP2040_CLOCKS_NDX_GPOUT2))
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_SELECTED (RP2040_CLOCKS_CLK_NDX_SELECTED(RP2040_CLOCKS_NDX_GPOUT2))
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL (RP2040_CLOCKS_CLK_NDX_CTRL(RP2040_CLOCKS_NDX_GPOUT3))
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_DIV (RP2040_CLOCKS_CLK_NDX_DIV(RP2040_CLOCKS_NDX_GPOUT3))
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_SELECTED (RP2040_CLOCKS_CLK_NDX_SELECTED(RP2040_CLOCKS_NDX_GPOUT3))
|
||||
#define RP2040_CLOCKS_CLK_REF_CTRL (RP2040_CLOCKS_CLK_NDX_CTRL(RP2040_CLOCKS_NDX_REF))
|
||||
#define RP2040_CLOCKS_CLK_REF_DIV (RP2040_CLOCKS_CLK_NDX_DIV(RP2040_CLOCKS_NDX_REF))
|
||||
#define RP2040_CLOCKS_CLK_REF_SELECTED (RP2040_CLOCKS_CLK_NDX_SELECTED(RP2040_CLOCKS_NDX_REF))
|
||||
#define RP2040_CLOCKS_CLK_SYS_CTRL (RP2040_CLOCKS_CLK_NDX_CTRL(RP2040_CLOCKS_NDX_SYS))
|
||||
#define RP2040_CLOCKS_CLK_SYS_DIV (RP2040_CLOCKS_CLK_NDX_DIV(RP2040_CLOCKS_NDX_SYS))
|
||||
#define RP2040_CLOCKS_CLK_SYS_SELECTED (RP2040_CLOCKS_CLK_NDX_SELECTED(RP2040_CLOCKS_NDX_SYS))
|
||||
#define RP2040_CLOCKS_CLK_PERI_CTRL (RP2040_CLOCKS_CLK_NDX_CTRL(RP2040_CLOCKS_NDX_PERI))
|
||||
#define RP2040_CLOCKS_CLK_PERI_SELECTED (RP2040_CLOCKS_CLK_NDX_SELECTED(RP2040_CLOCKS_NDX_PERI))
|
||||
#define RP2040_CLOCKS_CLK_USB_CTRL (RP2040_CLOCKS_CLK_NDX_CTRL(RP2040_CLOCKS_NDX_USB))
|
||||
#define RP2040_CLOCKS_CLK_USB_DIV (RP2040_CLOCKS_CLK_NDX_DIV(RP2040_CLOCKS_NDX_USB))
|
||||
#define RP2040_CLOCKS_CLK_USB_SELECTED (RP2040_CLOCKS_CLK_NDX_SELECTED(RP2040_CLOCKS_NDX_USB))
|
||||
#define RP2040_CLOCKS_CLK_ADC_CTRL (RP2040_CLOCKS_CLK_NDX_CTRL(RP2040_CLOCKS_NDX_ADC))
|
||||
#define RP2040_CLOCKS_CLK_ADC_DIV (RP2040_CLOCKS_CLK_NDX_DIV(RP2040_CLOCKS_NDX_ADC))
|
||||
#define RP2040_CLOCKS_CLK_ADC_SELECTED (RP2040_CLOCKS_CLK_NDX_SELECTED(RP2040_CLOCKS_NDX_ADC))
|
||||
#define RP2040_CLOCKS_CLK_RTC_CTRL (RP2040_CLOCKS_CLK_NDX_CTRL(RP2040_CLOCKS_NDX_RTC))
|
||||
#define RP2040_CLOCKS_CLK_RTC_DIV (RP2040_CLOCKS_CLK_NDX_DIV(RP2040_CLOCKS_NDX_RTC))
|
||||
#define RP2040_CLOCKS_CLK_RTC_SELECTED (RP2040_CLOCKS_CLK_NDX_SELECTED(RP2040_CLOCKS_NDX_RTC))
|
||||
|
||||
#define RP2040_CLOCKS_CLK_SYS_RESUS_CTRL (RP2040_CLOCKS_BASE + RP2040_CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET)
|
||||
#define RP2040_CLOCKS_CLK_SYS_RESUS_STATUS (RP2040_CLOCKS_BASE + RP2040_CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET)
|
||||
#define RP2040_CLOCKS_FC0_REF_KHZ (RP2040_CLOCKS_BASE + RP2040_CLOCKS_FC0_REF_KHZ_OFFSET)
|
||||
#define RP2040_CLOCKS_FC0_MIN_KHZ (RP2040_CLOCKS_BASE + RP2040_CLOCKS_FC0_MIN_KHZ_OFFSET)
|
||||
#define RP2040_CLOCKS_FC0_MAX_KHZ (RP2040_CLOCKS_BASE + RP2040_CLOCKS_FC0_MAX_KHZ_OFFSET)
|
||||
#define RP2040_CLOCKS_FC0_DELAY (RP2040_CLOCKS_BASE + RP2040_CLOCKS_FC0_DELAY_OFFSET)
|
||||
#define RP2040_CLOCKS_FC0_INTERVAL (RP2040_CLOCKS_BASE + RP2040_CLOCKS_FC0_INTERVAL_OFFSET)
|
||||
#define RP2040_CLOCKS_FC0_SRC (RP2040_CLOCKS_BASE + RP2040_CLOCKS_FC0_SRC_OFFSET)
|
||||
#define RP2040_CLOCKS_FC0_STATUS (RP2040_CLOCKS_BASE + RP2040_CLOCKS_FC0_STATUS_OFFSET)
|
||||
#define RP2040_CLOCKS_FC0_RESULT (RP2040_CLOCKS_BASE + RP2040_CLOCKS_FC0_RESULT_OFFSET)
|
||||
#define RP2040_CLOCKS_WAKE_EN0 (RP2040_CLOCKS_BASE + RP2040_CLOCKS_WAKE_EN0_OFFSET)
|
||||
#define RP2040_CLOCKS_WAKE_EN1 (RP2040_CLOCKS_BASE + RP2040_CLOCKS_WAKE_EN1_OFFSET)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0 (RP2040_CLOCKS_BASE + RP2040_CLOCKS_SLEEP_EN0_OFFSET)
|
||||
#define RP2040_CLOCKS_SLEEP_EN1 (RP2040_CLOCKS_BASE + RP2040_CLOCKS_SLEEP_EN1_OFFSET)
|
||||
#define RP2040_CLOCKS_ENABLED0 (RP2040_CLOCKS_BASE + RP2040_CLOCKS_ENABLED0_OFFSET)
|
||||
#define RP2040_CLOCKS_ENABLED1 (RP2040_CLOCKS_BASE + RP2040_CLOCKS_ENABLED1_OFFSET)
|
||||
#define RP2040_CLOCKS_INTR (RP2040_CLOCKS_BASE + RP2040_CLOCKS_INTR_OFFSET)
|
||||
#define RP2040_CLOCKS_INTE (RP2040_CLOCKS_BASE + RP2040_CLOCKS_INTE_OFFSET)
|
||||
#define RP2040_CLOCKS_INTF (RP2040_CLOCKS_BASE + RP2040_CLOCKS_INTF_OFFSET)
|
||||
#define RP2040_CLOCKS_INTS (RP2040_CLOCKS_BASE + RP2040_CLOCKS_INTS_OFFSET)
|
||||
|
||||
/* Register bit definitions *************************************************/
|
||||
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_PHASE_MASK (0x03 << RP2040_CLOCKS_CLK_GPOUT0_CTRL_PHASE_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_DC50 (1 << 12) /* Enables duty cycle correction for odd divisors */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MASK (0x0f << RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x0 << RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLKSRC_GPIN0 (0x1 << RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLKSRC_GPIN1 (0x2 << RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLKSRC_PLL_USB (0x3 << RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ROSC_CLKSRC (0x4 << RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_XOSC_CLKSRC (0x5 << RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_SYS (0x6 << RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_USB (0x7 << RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_ADC (0x8 << RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_RTC (0x9 << RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_REF (0xa << RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
|
||||
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_DIV_INT_SHIFT (8) /* Integer component of the divisor, 0 -> divide by 2^16 */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_DIV_INT_MASK (0xffffff << RP2040_CLOCKS_CLK_GPOUT0_DIV_INT_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT0_DIV_FRAC_MASK (0xff) /* Fractional component of the divisor */
|
||||
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_PHASE_MASK (0x03 << RP2040_CLOCKS_CLK_GPOUT1_CTRL_PHASE_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_DC50 (1 << 12) /* Enables duty cycle correction for odd divisors */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MASK (0x0f << RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x0 << RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLKSRC_GPIN0 (0x1 << RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLKSRC_GPIN1 (0x2 << RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLKSRC_PLL_USB (0x3 << RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ROSC_CLKSRC (0x4 << RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_XOSC_CLKSRC (0x5 << RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_SYS (0x6 << RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_USB (0x7 << RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_ADC (0x8 << RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_RTC (0x9 << RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_REF (0xa << RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
|
||||
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_DIV_INT_SHIFT (8) /* Integer component of the divisor, 0 -> divide by 2^16 */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_DIV_INT_MASK (0xffffff << RP2040_CLOCKS_CLK_GPOUT1_DIV_INT_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT1_DIV_FRAC_MASK (0xff) /* Fractional component of the divisor */
|
||||
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_PHASE_MASK (0x03 << RP2040_CLOCKS_CLK_GPOUT2_CTRL_PHASE_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_DC50 (1 << 12) /* Enables duty cycle correction for odd divisors */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MASK (0x0f << RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x0 << RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLKSRC_GPIN0 (0x1 << RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLKSRC_GPIN1 (0x2 << RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLKSRC_PLL_USB (0x3 << RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x4 << RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_XOSC_CLKSRC (0x5 << RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_SYS (0x6 << RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_USB (0x7 << RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_ADC (0x8 << RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_RTC (0x9 << RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_REF (0xa << RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
|
||||
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_DIV_INT_SHIFT (8) /* Integer component of the divisor, 0 -> divide by 2^16 */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_DIV_INT_MASK (0xffffff << RP2040_CLOCKS_CLK_GPOUT2_DIV_INT_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT2_DIV_FRAC_MASK (0xff) /* Fractional component of the divisor */
|
||||
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_PHASE_MASK (0x03 << RP2040_CLOCKS_CLK_GPOUT3_CTRL_PHASE_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_DC50 (1 << 12) /* Enables duty cycle correction for odd divisors */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MASK (0x0f << RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x0 << RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLKSRC_GPIN0 (0x1 << RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLKSRC_GPIN1 (0x2 << RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLKSRC_PLL_USB (0x3 << RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x4 << RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_XOSC_CLKSRC (0x5 << RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_SYS (0x6 << RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_USB (0x7 << RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_ADC (0x8 << RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_RTC (0x9 << RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_REF (0xa << RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
|
||||
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_DIV_INT_SHIFT (8) /* Integer component of the divisor, 0 -> divide by 2^16 */
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_DIV_INT_MASK (0xffffff << RP2040_CLOCKS_CLK_GPOUT3_DIV_INT_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_GPOUT3_DIV_FRAC_MASK (0xff) /* Fractional component of the divisor */
|
||||
|
||||
#define RP2040_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
|
||||
#define RP2040_CLOCKS_CLK_REF_CTRL_AUXSRC_MASK (0x03 << RP2040_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_REF_CTRL_AUXSRC_CLKSRC_PLL_USB (0x0 << RP2040_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_REF_CTRL_AUXSRC_CLKSRC_GPIN0 (0x1 << RP2040_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_REF_CTRL_AUXSRC_CLKSRC_GPIN1 (0x2 << RP2040_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_REF_CTRL_SRC_MASK (0x03)
|
||||
#define RP2040_CLOCKS_CLK_REF_CTRL_SRC_ROSC_CLKSRC_PH (0x0)
|
||||
#define RP2040_CLOCKS_CLK_REF_CTRL_SRC_CLKSRC_CLK_REF_AUX (0x1)
|
||||
#define RP2040_CLOCKS_CLK_REF_CTRL_SRC_XOSC_CLKSRC (0x2)
|
||||
|
||||
#define RP2040_CLOCKS_CLK_REF_DIV_INT_SHIFT (8) /* Integer component of the divisor, 0 -> divide by 2^16 */
|
||||
#define RP2040_CLOCKS_CLK_REF_DIV_INT_MASK (0x03 << RP2040_CLOCKS_CLK_REF_DIV_INT_SHIFT)
|
||||
|
||||
#define RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
|
||||
#define RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_MASK (0x07 << RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x0 << RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_PLL_USB (0x1 << RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_ROSC_CLKSRC (0x2 << RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_XOSC_CLKSRC (0x3 << RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_GPIN0 (0x4 << RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_GPIN1 (0x5 << RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_SYS_CTRL_SRC (1 << 0)
|
||||
#define RP2040_CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX (0x1)
|
||||
|
||||
#define RP2040_CLOCKS_CLK_SYS_DIV_INT_SHIFT (8) /* Integer component of the divisor, 0 -> divide by 2^16 */
|
||||
#define RP2040_CLOCKS_CLK_SYS_DIV_INT_MASK (0xffffff << RP2040_CLOCKS_CLK_SYS_DIV_INT_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_SYS_DIV_FRAC_MASK (0xff) /* Fractional component of the divisor */
|
||||
|
||||
#define RP2040_CLOCKS_CLK_PERI_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
|
||||
#define RP2040_CLOCKS_CLK_PERI_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
|
||||
#define RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
|
||||
#define RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_MASK (0x07 << RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLK_SYS (0x0 << RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x1 << RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLKSRC_PLL_USB (0x2 << RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x3 << RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_XOSC_CLKSRC (0x4 << RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLKSRC_GPIN0 (0x5 << RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLKSRC_GPIN1 (0x6 << RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
|
||||
|
||||
#define RP2040_CLOCKS_CLK_USB_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
|
||||
#define RP2040_CLOCKS_CLK_USB_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
|
||||
#define RP2040_CLOCKS_CLK_USB_CTRL_PHASE_MASK (0x03 << RP2040_CLOCKS_CLK_USB_CTRL_PHASE_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_USB_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
|
||||
#define RP2040_CLOCKS_CLK_USB_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
|
||||
#define RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
|
||||
#define RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_MASK (0x07 << RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_PLL_USB (0x0 << RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x1 << RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x2 << RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_XOSC_CLKSRC (0x3 << RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_GPIN0 (0x4 << RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_GPIN1 (0x5 << RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
|
||||
|
||||
#define RP2040_CLOCKS_CLK_USB_DIV_INT_SHIFT (8) /* Integer component of the divisor, 0 -> divide by 2^16 */
|
||||
#define RP2040_CLOCKS_CLK_USB_DIV_INT_MASK (0x03 << RP2040_CLOCKS_CLK_USB_DIV_INT_SHIFT)
|
||||
|
||||
#define RP2040_CLOCKS_CLK_ADC_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
|
||||
#define RP2040_CLOCKS_CLK_ADC_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
|
||||
#define RP2040_CLOCKS_CLK_ADC_CTRL_PHASE_MASK (0x03 << RP2040_CLOCKS_CLK_ADC_CTRL_PHASE_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_ADC_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
|
||||
#define RP2040_CLOCKS_CLK_ADC_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
|
||||
#define RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
|
||||
#define RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_MASK (0x07 << RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_PLL_USB (0x0 << RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x1 << RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x2 << RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_XOSC_CLKSRC (0x3 << RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_GPIN0 (0x4 << RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_GPIN1 (0x5 << RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
|
||||
|
||||
#define RP2040_CLOCKS_CLK_ADC_DIV_INT_SHIFT (8) /* Integer component of the divisor, 0 -> divide by 2^16 */
|
||||
#define RP2040_CLOCKS_CLK_ADC_DIV_INT_MASK (0x03 << RP2040_CLOCKS_CLK_ADC_DIV_INT_SHIFT)
|
||||
|
||||
#define RP2040_CLOCKS_CLK_RTC_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
|
||||
#define RP2040_CLOCKS_CLK_RTC_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
|
||||
#define RP2040_CLOCKS_CLK_RTC_CTRL_PHASE_MASK (0x03 << RP2040_CLOCKS_CLK_RTC_CTRL_PHASE_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_RTC_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
|
||||
#define RP2040_CLOCKS_CLK_RTC_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
|
||||
#define RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
|
||||
#define RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_MASK (0x07 << RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_CLKSRC_PLL_USB (0x0 << RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x1 << RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x2 << RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_XOSC_CLKSRC (0x3 << RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_CLKSRC_GPIN0 (0x4 << RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_CLKSRC_GPIN1 (0x5 << RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_SHIFT)
|
||||
|
||||
#define RP2040_CLOCKS_CLK_RTC_DIV_INT_SHIFT (8) /* Integer component of the divisor, 0 -> divide by 2^16 */
|
||||
#define RP2040_CLOCKS_CLK_RTC_DIV_INT_MASK (0xffffff << RP2040_CLOCKS_CLK_RTC_DIV_INT_SHIFT)
|
||||
#define RP2040_CLOCKS_CLK_RTC_DIV_FRAC_MASK (0xff) /* Fractional component of the divisor */
|
||||
|
||||
#define RP2040_CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR (1 << 16) /* For clearing the resus after the fault that triggered it has been corrected */
|
||||
#define RP2040_CLOCKS_CLK_SYS_RESUS_CTRL_FRCE (1 << 12) /* Force a resus, for test purposes only */
|
||||
#define RP2040_CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE (1 << 8) /* Enable resus */
|
||||
#define RP2040_CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MASK (0xff) /* This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq */
|
||||
|
||||
#define RP2040_CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED (1 << 0) /* Clock has been resuscitated, correct the error then send ctrl_clear=1 */
|
||||
|
||||
#define RP2040_CLOCKS_FC0_REF_KHZ_MASK (0xfffff)
|
||||
|
||||
#define RP2040_CLOCKS_FC0_MIN_KHZ_MASK (0x1ffffff)
|
||||
|
||||
#define RP2040_CLOCKS_FC0_MAX_KHZ_MASK (0x1ffffff)
|
||||
|
||||
#define RP2040_CLOCKS_FC0_DELAY_MASK (0x07)
|
||||
|
||||
#define RP2040_CLOCKS_FC0_INTERVAL_MASK (0x0f)
|
||||
|
||||
#define RP2040_CLOCKS_FC0_SRC_MASK (0xff)
|
||||
#define RP2040_CLOCKS_FC0_SRC_NULL (0x0)
|
||||
#define RP2040_CLOCKS_FC0_SRC_PLL_SYS_CLKSRC_PRIMARY (0x1)
|
||||
#define RP2040_CLOCKS_FC0_SRC_PLL_USB_CLKSRC_PRIMARY (0x2)
|
||||
#define RP2040_CLOCKS_FC0_SRC_ROSC_CLKSRC (0x3)
|
||||
#define RP2040_CLOCKS_FC0_SRC_ROSC_CLKSRC_PH (0x4)
|
||||
#define RP2040_CLOCKS_FC0_SRC_XOSC_CLKSRC (0x5)
|
||||
#define RP2040_CLOCKS_FC0_SRC_CLKSRC_GPIN0 (0x6)
|
||||
#define RP2040_CLOCKS_FC0_SRC_CLKSRC_GPIN1 (0x7)
|
||||
#define RP2040_CLOCKS_FC0_SRC_CLK_REF (0x8)
|
||||
#define RP2040_CLOCKS_FC0_SRC_CLK_SYS (0x9)
|
||||
#define RP2040_CLOCKS_FC0_SRC_CLK_PERI (0xa)
|
||||
#define RP2040_CLOCKS_FC0_SRC_CLK_USB (0xb)
|
||||
#define RP2040_CLOCKS_FC0_SRC_CLK_ADC (0xc)
|
||||
#define RP2040_CLOCKS_FC0_SRC_CLK_RTC (0xd)
|
||||
|
||||
#define RP2040_CLOCKS_FC0_STATUS_DIED (1 << 28) /* Test clock stopped during test */
|
||||
#define RP2040_CLOCKS_FC0_STATUS_FAST (1 << 24) /* Test clock faster than expected, only valid when status_done=1 */
|
||||
#define RP2040_CLOCKS_FC0_STATUS_SLOW (1 << 20) /* Test clock slower than expected, only valid when status_done=1 */
|
||||
#define RP2040_CLOCKS_FC0_STATUS_FAIL (1 << 16) /* Test failed */
|
||||
#define RP2040_CLOCKS_FC0_STATUS_WAITING (1 << 12) /* Waiting for test clock to start */
|
||||
#define RP2040_CLOCKS_FC0_STATUS_RUNNING (1 << 8) /* Test running */
|
||||
#define RP2040_CLOCKS_FC0_STATUS_DONE (1 << 4) /* Test complete */
|
||||
#define RP2040_CLOCKS_FC0_STATUS_PASS (1 << 0) /* Test passed */
|
||||
|
||||
#define RP2040_CLOCKS_FC0_RESULT_KHZ_SHIFT (5)
|
||||
#define RP2040_CLOCKS_FC0_RESULT_KHZ_MASK (0x1ffffff << RP2040_CLOCKS_FC0_RESULT_KHZ_SHIFT)
|
||||
#define RP2040_CLOCKS_FC0_RESULT_FRAC_MASK (0x1f)
|
||||
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_sram3 (1 << 31)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_sram2 (1 << 30)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_sram1 (1 << 29)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_sram0 (1 << 28)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_spi1 (1 << 27)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_peri_spi1 (1 << 26)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_spi0 (1 << 25)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_peri_spi0 (1 << 24)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_sio (1 << 23)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_rtc (1 << 22)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_rtc_rtc (1 << 21)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_rosc (1 << 20)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_rom (1 << 19)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_resets (1 << 18)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_pwm (1 << 17)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_psm (1 << 16)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_pll_usb (1 << 15)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_pll_sys (1 << 14)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_pio1 (1 << 13)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_pio0 (1 << 12)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_pads (1 << 11)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_vreg_and_chip_reset (1 << 10)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_jtag (1 << 9)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_io (1 << 8)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_i2c1 (1 << 7)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_i2c0 (1 << 6)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_dma (1 << 5)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_busfabric (1 << 4)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_busctrl (1 << 3)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_adc (1 << 2)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_adc_adc (1 << 1)
|
||||
#define RP2040_CLOCKS_WAKE_EN0_clk_sys_clocks (1 << 0)
|
||||
|
||||
#define RP2040_CLOCKS_WAKE_EN1_clk_sys_xosc (1 << 14)
|
||||
#define RP2040_CLOCKS_WAKE_EN1_clk_sys_xip (1 << 13)
|
||||
#define RP2040_CLOCKS_WAKE_EN1_clk_sys_watchdog (1 << 12)
|
||||
#define RP2040_CLOCKS_WAKE_EN1_clk_usb_usbctrl (1 << 11)
|
||||
#define RP2040_CLOCKS_WAKE_EN1_clk_sys_usbctrl (1 << 10)
|
||||
#define RP2040_CLOCKS_WAKE_EN1_clk_sys_uart1 (1 << 9)
|
||||
#define RP2040_CLOCKS_WAKE_EN1_clk_peri_uart1 (1 << 8)
|
||||
#define RP2040_CLOCKS_WAKE_EN1_clk_sys_uart0 (1 << 7)
|
||||
#define RP2040_CLOCKS_WAKE_EN1_clk_peri_uart0 (1 << 6)
|
||||
#define RP2040_CLOCKS_WAKE_EN1_clk_sys_timer (1 << 5)
|
||||
#define RP2040_CLOCKS_WAKE_EN1_clk_sys_tbman (1 << 4)
|
||||
#define RP2040_CLOCKS_WAKE_EN1_clk_sys_sysinfo (1 << 3)
|
||||
#define RP2040_CLOCKS_WAKE_EN1_clk_sys_syscfg (1 << 2)
|
||||
#define RP2040_CLOCKS_WAKE_EN1_clk_sys_sram5 (1 << 1)
|
||||
#define RP2040_CLOCKS_WAKE_EN1_clk_sys_sram4 (1 << 0)
|
||||
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_sram3 (1 << 31)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_sram2 (1 << 30)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_sram1 (1 << 29)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_sram0 (1 << 28)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_spi1 (1 << 27)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_peri_spi1 (1 << 26)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_spi0 (1 << 25)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_peri_spi0 (1 << 24)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_sio (1 << 23)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_rtc (1 << 22)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_rtc_rtc (1 << 21)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_rosc (1 << 20)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_rom (1 << 19)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_resets (1 << 18)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_pwm (1 << 17)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_psm (1 << 16)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_pll_usb (1 << 15)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_pll_sys (1 << 14)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_pio1 (1 << 13)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_pio0 (1 << 12)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_pads (1 << 11)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_vreg_and_chip_reset (1 << 10)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_jtag (1 << 9)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_io (1 << 8)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_i2c1 (1 << 7)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_i2c0 (1 << 6)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_dma (1 << 5)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_busfabric (1 << 4)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_busctrl (1 << 3)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_adc (1 << 2)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_adc_adc (1 << 1)
|
||||
#define RP2040_CLOCKS_SLEEP_EN0_clk_sys_clocks (1 << 0)
|
||||
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_clk_sys_xosc (1 << 14)
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_clk_sys_xip (1 << 13)
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_clk_sys_watchdog (1 << 12)
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_clk_usb_usbctrl (1 << 11)
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_clk_sys_usbctrl (1 << 10)
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_clk_sys_uart1 (1 << 9)
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_clk_peri_uart1 (1 << 8)
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_clk_sys_uart0 (1 << 7)
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_clk_peri_uart0 (1 << 6)
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_clk_sys_timer (1 << 5)
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_clk_sys_tbman (1 << 4)
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_clk_sys_sysinfo (1 << 3)
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_clk_sys_syscfg (1 << 2)
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_clk_sys_sram5 (1 << 1)
|
||||
#define RP2040_CLOCKS_SLEEP_EN1_clk_sys_sram4 (1 << 0)
|
||||
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_sram3 (1 << 31)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_sram2 (1 << 30)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_sram1 (1 << 29)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_sram0 (1 << 28)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_spi1 (1 << 27)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_peri_spi1 (1 << 26)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_spi0 (1 << 25)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_peri_spi0 (1 << 24)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_sio (1 << 23)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_rtc (1 << 22)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_rtc_rtc (1 << 21)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_rosc (1 << 20)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_rom (1 << 19)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_resets (1 << 18)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_pwm (1 << 17)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_psm (1 << 16)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_pll_usb (1 << 15)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_pll_sys (1 << 14)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_pio1 (1 << 13)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_pio0 (1 << 12)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_pads (1 << 11)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_vreg_and_chip_reset (1 << 10)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_jtag (1 << 9)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_io (1 << 8)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_i2c1 (1 << 7)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_i2c0 (1 << 6)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_dma (1 << 5)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_busfabric (1 << 4)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_busctrl (1 << 3)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_adc (1 << 2)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_adc_adc (1 << 1)
|
||||
#define RP2040_CLOCKS_ENABLED0_clk_sys_clocks (1 << 0)
|
||||
|
||||
#define RP2040_CLOCKS_ENABLED1_clk_sys_xosc (1 << 14)
|
||||
#define RP2040_CLOCKS_ENABLED1_clk_sys_xip (1 << 13)
|
||||
#define RP2040_CLOCKS_ENABLED1_clk_sys_watchdog (1 << 12)
|
||||
#define RP2040_CLOCKS_ENABLED1_clk_usb_usbctrl (1 << 11)
|
||||
#define RP2040_CLOCKS_ENABLED1_clk_sys_usbctrl (1 << 10)
|
||||
#define RP2040_CLOCKS_ENABLED1_clk_sys_uart1 (1 << 9)
|
||||
#define RP2040_CLOCKS_ENABLED1_clk_peri_uart1 (1 << 8)
|
||||
#define RP2040_CLOCKS_ENABLED1_clk_sys_uart0 (1 << 7)
|
||||
#define RP2040_CLOCKS_ENABLED1_clk_peri_uart0 (1 << 6)
|
||||
#define RP2040_CLOCKS_ENABLED1_clk_sys_timer (1 << 5)
|
||||
#define RP2040_CLOCKS_ENABLED1_clk_sys_tbman (1 << 4)
|
||||
#define RP2040_CLOCKS_ENABLED1_clk_sys_sysinfo (1 << 3)
|
||||
#define RP2040_CLOCKS_ENABLED1_clk_sys_syscfg (1 << 2)
|
||||
#define RP2040_CLOCKS_ENABLED1_clk_sys_sram5 (1 << 1)
|
||||
#define RP2040_CLOCKS_ENABLED1_clk_sys_sram4 (1 << 0)
|
||||
|
||||
#define RP2040_CLOCKS_INTR_CLK_SYS_RESUS (1 << 0)
|
||||
|
||||
#define RP2040_CLOCKS_INTE_CLK_SYS_RESUS (1 << 0)
|
||||
|
||||
#define RP2040_CLOCKS_INTF_CLK_SYS_RESUS (1 << 0)
|
||||
|
||||
#define RP2040_CLOCKS_INTS_CLK_SYS_RESUS (1 << 0)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_CLOCKS_H */
|
||||
128
arch/arm/src/rp2040/hardware/rp2040_io_bank0.h
Normal file
128
arch/arm/src/rp2040/hardware/rp2040_io_bank0.h
Normal file
@ -0,0 +1,128 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/hardware/rp2040_io_bank0.h
|
||||
*
|
||||
* Generated from rp2040.svd originally provided by
|
||||
* Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_IO_BANK0_H
|
||||
#define __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_IO_BANK0_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hardware/rp2040_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define RP2040_IO_BANK0_GPIO_STATUS_OFFSET(n) ((n) * 8 + 0x000000) /* GPIO status */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_OFFSET(n) ((n) * 8 + 0x000004) /* GPIO control including function select and overrides. */
|
||||
#define RP2040_IO_BANK0_INTR_OFFSET(n) (((n) >> 3) * 4 + 0x0000f0) /* Raw Interrupts */
|
||||
#define RP2040_IO_BANK0_PROC_INTE_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x30) + 0x000100) /* Interrupt Enable */
|
||||
#define RP2040_IO_BANK0_PROC_INTF_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x30) + 0x000110) /* Interrupt Force */
|
||||
#define RP2040_IO_BANK0_PROC_INTS_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x30) + 0x000120) /* Interrupt status after masking & forcing */
|
||||
#define RP2040_IO_BANK0_DORMANT_WAKE_INTE_OFFSET(n) (((n) >> 3) * 4 + 0x000160) /* Interrupt Enable for dormant_wake */
|
||||
#define RP2040_IO_BANK0_DORMANT_WAKE_INTF_OFFSET(n) (((n) >> 3) * 4 + 0x000170) /* Interrupt Force for dormant_wake */
|
||||
#define RP2040_IO_BANK0_DORMANT_WAKE_INTS_OFFSET(n) (((n) >> 3) * 4 + 0x000180) /* Interrupt status after masking & forcing for dormant_wake */
|
||||
|
||||
/* Register definitions *****************************************************/
|
||||
|
||||
#define RP2040_IO_BANK0_GPIO_STATUS(n) (RP2040_IO_BANK0_BASE + RP2040_IO_BANK0_GPIO_STATUS_OFFSET(n))
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL(n) (RP2040_IO_BANK0_BASE + RP2040_IO_BANK0_GPIO_CTRL_OFFSET(n))
|
||||
#define RP2040_IO_BANK0_INTR(n) (RP2040_IO_BANK0_BASE + RP2040_IO_BANK0_INTR_OFFSET(n))
|
||||
#define RP2040_IO_BANK0_PROC_INTE(n, p) (RP2040_IO_BANK0_BASE + RP2040_IO_BANK0_PROC_INTE_OFFSET(n, p))
|
||||
#define RP2040_IO_BANK0_PROC_INTF(n, p) (RP2040_IO_BANK0_BASE + RP2040_IO_BANK0_PROC_INTF_OFFSET(n, p))
|
||||
#define RP2040_IO_BANK0_PROC_INTS(n, p) (RP2040_IO_BANK0_BASE + RP2040_IO_BANK0_PROC_INTS_OFFSET(n, p))
|
||||
#define RP2040_IO_BANK0_DORMANT_WAKE_INTE(n) (RP2040_IO_BANK0_BASE + RP2040_IO_BANK0_DORMANT_WAKE_INTE_OFFSET(n))
|
||||
#define RP2040_IO_BANK0_DORMANT_WAKE_INTF(n) (RP2040_IO_BANK0_BASE + RP2040_IO_BANK0_DORMANT_WAKE_INTF_OFFSET(n))
|
||||
#define RP2040_IO_BANK0_DORMANT_WAKE_INTS(n) (RP2040_IO_BANK0_BASE + RP2040_IO_BANK0_DORMANT_WAKE_INTS_OFFSET(n))
|
||||
|
||||
/* Register bit definitions *************************************************/
|
||||
|
||||
#define RP2040_IO_BANK0_GPIO_STATUS_IRQTOPROC (1 << 26) /* interrupt to processors, after override is applied */
|
||||
#define RP2040_IO_BANK0_GPIO_STATUS_IRQFROMPAD (1 << 24) /* interrupt from pad before override is applied */
|
||||
#define RP2040_IO_BANK0_GPIO_STATUS_INTOPERI (1 << 19) /* input signal to peripheral, after override is applied */
|
||||
#define RP2040_IO_BANK0_GPIO_STATUS_INFROMPAD (1 << 17) /* input signal from pad, before override is applied */
|
||||
#define RP2040_IO_BANK0_GPIO_STATUS_OETOPAD (1 << 13) /* output enable to pad after register override is applied */
|
||||
#define RP2040_IO_BANK0_GPIO_STATUS_OEFROMPERI (1 << 12) /* output enable from selected peripheral, before register override is applied */
|
||||
#define RP2040_IO_BANK0_GPIO_STATUS_OUTTOPAD (1 << 9) /* output signal to pad after register override is applied */
|
||||
#define RP2040_IO_BANK0_GPIO_STATUS_OUTFROMPERI (1 << 8) /* output signal from selected peripheral, before register override is applied */
|
||||
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_IRQOVER_SHIFT (28)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_IRQOVER_MASK (0x03 << RP2040_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_IRQOVER_NORMAL (0x0 << RP2040_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* don't invert the interrupt */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_IRQOVER_INVERT (0x1 << RP2040_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* invert the interrupt */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_IRQOVER_LOW (0x2 << RP2040_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* drive interrupt low */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_IRQOVER_HIGH (0x3 << RP2040_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* drive interrupt high */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_INOVER_SHIFT (16)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_INOVER_MASK (0x03 << RP2040_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_INOVER_NORMAL (0x0 << RP2040_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* don't invert the peri input */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_INOVER_INVERT (0x1 << RP2040_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* invert the peri input */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_INOVER_LOW (0x2 << RP2040_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* drive peri input low */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_INOVER_HIGH (0x3 << RP2040_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* drive peri input high */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_OEOVER_SHIFT (12)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_OEOVER_MASK (0x03 << RP2040_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_OEOVER_NORMAL (0x0 << RP2040_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* drive output enable from peripheral signal selected by funcsel */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_OEOVER_INVERT (0x1 << RP2040_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* drive output enable from inverse of peripheral signal selected by funcsel */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_OEOVER_DISABLE (0x2 << RP2040_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* disable output */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_OEOVER_ENABLE (0x3 << RP2040_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* enable output */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_OUTOVER_SHIFT (8)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_OUTOVER_MASK (0x03 << RP2040_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_OUTOVER_NORMAL (0x0 << RP2040_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output from peripheral signal selected by funcsel */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_OUTOVER_INVERT (0x1 << RP2040_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output from inverse of peripheral signal selected by funcsel */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_OUTOVER_LOW (0x2 << RP2040_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output low */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_OUTOVER_HIGH (0x3 << RP2040_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output high */
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_MASK (0x1f)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_JTAG (0x0)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_SPI (0x1)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_UART (0x2)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_I2C (0x3)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_PWM (0x4)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_SIO (0x5)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_PIO0 (0x6)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_PIO1 (0x7)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_CLOCKS (0x8)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_USB (0x9)
|
||||
#define RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_NULL (0x1f)
|
||||
|
||||
#define RP2040_IO_BANK0_INTR_GPIO_EDGE_HIGH(n) (1 << (((n) & 0x7) * 4 + 3))
|
||||
#define RP2040_IO_BANK0_INTR_GPIO_EDGE_LOW(n) (1 << (((n) & 0x7) * 4 + 2))
|
||||
#define RP2040_IO_BANK0_INTR_GPIO_LEVEL_HIGH(n) (1 << (((n) & 0x7) * 4 + 1))
|
||||
#define RP2040_IO_BANK0_INTR_GPIO_LEVEL_LOW(n) (1 << (((n) & 0x7) * 4))
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_IO_BANK0_H */
|
||||
135
arch/arm/src/rp2040/hardware/rp2040_memorymap.h
Normal file
135
arch/arm/src/rp2040/hardware/rp2040_memorymap.h
Normal file
@ -0,0 +1,135 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/hardware/rp2040_memorymap.h
|
||||
*
|
||||
* Generated from rp2040.svd originally provided by
|
||||
* Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_MEMORYMAP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "arm_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define RP2040_FLASH_BASE 0x10000000 /* -0x001fffff: FLASH memory space (2048KB) */
|
||||
#define RP2040_SRAM_BASE 0x20000000 /* -0x20041fff: SRAM memory space (264KB) */
|
||||
|
||||
#define RP2040_XIP_CTRL_BASE 0x14000000 /* QSPI flash execute-in-place block */
|
||||
#define RP2040_XIP_SSI_BASE 0x18000000
|
||||
#define RP2040_SYSINFO_BASE 0x40000000
|
||||
#define RP2040_SYSCFG_BASE 0x40004000 /* Register block for various chip control signals */
|
||||
#define RP2040_CLOCKS_BASE 0x40008000
|
||||
#define RP2040_RESETS_BASE 0x4000c000
|
||||
#define RP2040_PSM_BASE 0x40010000
|
||||
#define RP2040_IO_BANK0_BASE 0x40014000
|
||||
#define RP2040_IO_QSPI_BASE 0x40018000
|
||||
#define RP2040_PADS_BANK0_BASE 0x4001c000
|
||||
#define RP2040_PADS_QSPI_BASE 0x40020000
|
||||
#define RP2040_XOSC_BASE 0x40024000 /* Controls the crystal oscillator */
|
||||
#define RP2040_PLL_SYS_BASE 0x40028000
|
||||
#define RP2040_PLL_USB_BASE 0x4002c000
|
||||
#define RP2040_BUSCTRL_BASE 0x40030000 /* Register block for busfabric control signals and performance counters */
|
||||
#define RP2040_UART0_BASE 0x40034000
|
||||
#define RP2040_UART1_BASE 0x40038000
|
||||
#define RP2040_SPI0_BASE 0x4003c000
|
||||
#define RP2040_SPI1_BASE 0x40040000
|
||||
#define RP2040_I2C0_BASE 0x40044000 /* DW_apb_i2c address block */
|
||||
#define RP2040_I2C1_BASE 0x40048000 /* DW_apb_i2c address block */
|
||||
#define RP2040_ADC_BASE 0x4004c000 /* Control and data interface to SAR ADC */
|
||||
#define RP2040_PWM_BASE 0x40050000 /* Simple PWM */
|
||||
#define RP2040_TIMER_BASE 0x40054000 /* Controls time and alarms time is a 64 bit value indicating the time in usec since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq */
|
||||
#define RP2040_WATCHDOG_BASE 0x40058000
|
||||
#define RP2040_RTC_BASE 0x4005c000 /* Register block to control RTC */
|
||||
#define RP2040_ROSC_BASE 0x40060000
|
||||
#define RP2040_VREG_AND_CHIP_RESET_BASE 0x40064000 /* control and status for on-chip voltage regulator and chip level reset subsystem */
|
||||
#define RP2040_TBMAN_BASE 0x4006c000 /* Testbench manager. Allows the programmer to know what platform their software is running on. */
|
||||
#define RP2040_DMA_BASE 0x50000000 /* DMA with separate read and write masters */
|
||||
#define RP2040_USBCTRL_REGS_BASE 0x50110000 /* USB FS/LS controller device registers */
|
||||
#define RP2040_PIO0_BASE 0x50200000 /* Programmable IO block */
|
||||
#define RP2040_PIO1_BASE 0x50300000 /* Programmable IO block */
|
||||
#define RP2040_SIO_BASE 0xd0000000 /* Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access. */
|
||||
#define RP2040_PPB_BASE 0xe0000000
|
||||
|
||||
#define RP2040_ATOMIC_XOR_REG_OFFSET 0x1000
|
||||
#define RP2040_ATOMIC_SET_REG_OFFSET 0x2000
|
||||
#define RP2040_ATOMIC_CLR_REG_OFFSET 0x3000
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
# define xorbits_reg32(v,a) putreg32(v, (a) | RP2040_ATOMIC_XOR_REG_OFFSET)
|
||||
# define setbits_reg32(v,a) putreg32(v, (a) | RP2040_ATOMIC_SET_REG_OFFSET)
|
||||
# define clrbits_reg32(v,a) putreg32(v, (a) | RP2040_ATOMIC_CLR_REG_OFFSET)
|
||||
# define modbits_reg32(v,m,a) xorbits_reg32((getreg32(a) ^ (v)) & (m), a)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_MEMORYMAP_H */
|
||||
82
arch/arm/src/rp2040/hardware/rp2040_pads_bank0.h
Normal file
82
arch/arm/src/rp2040/hardware/rp2040_pads_bank0.h
Normal file
@ -0,0 +1,82 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/hardware/rp2040_pads_bank0.h
|
||||
*
|
||||
* Generated from rp2040.svd originally provided by
|
||||
* Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_PADS_BANK0_H
|
||||
#define __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_PADS_BANK0_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hardware/rp2040_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define RP2040_PADS_BANK0_VOLTAGE_SELECT_OFFSET 0x000000 /* Voltage select. Per bank control */
|
||||
#define RP2040_PADS_BANK0_GPIO_OFFSET(n) ((n) * 4 + 0x000004) /* Pad control register */
|
||||
#define RP2040_PADS_BANK0_SWCLK_OFFSET 0x00007c /* Pad control register */
|
||||
#define RP2040_PADS_BANK0_SWD_OFFSET 0x000080 /* Pad control register */
|
||||
|
||||
/* Register definitions *****************************************************/
|
||||
|
||||
#define RP2040_PADS_BANK0_VOLTAGE_SELECT (RP2040_PADS_BANK0_BASE + RP2040_PADS_BANK0_VOLTAGE_SELECT_OFFSET)
|
||||
#define RP2040_PADS_BANK0_GPIO(n) (RP2040_PADS_BANK0_BASE + RP2040_PADS_BANK0_GPIO_OFFSET(n))
|
||||
#define RP2040_PADS_BANK0_SWCLK (RP2040_PADS_BANK0_BASE + RP2040_PADS_BANK0_SWCLK_OFFSET)
|
||||
#define RP2040_PADS_BANK0_SWD (RP2040_PADS_BANK0_BASE + RP2040_PADS_BANK0_SWD_OFFSET)
|
||||
|
||||
/* Register bit definitions *************************************************/
|
||||
|
||||
#define RP2040_PADS_BANK0_VOLTAGE_SELECT_1_8V (1 << 0) /* Set voltage to 1.8V (DVDD <= 1V8) */
|
||||
|
||||
#define RP2040_PADS_BANK0_GPIO_OD (1 << 7) /* Output disable. Has priority over output enable from peripherals */
|
||||
#define RP2040_PADS_BANK0_GPIO_IE (1 << 6) /* Input enable */
|
||||
#define RP2040_PADS_BANK0_GPIO_DRIVE_SHIFT (4) /* Drive strength. */
|
||||
#define RP2040_PADS_BANK0_GPIO_DRIVE_MASK (0x03 << RP2040_PADS_BANK0_GPIO0_DRIVE_SHIFT)
|
||||
#define RP2040_PADS_BANK0_GPIO_DRIVE_2MA (0x0 << RP2040_PADS_BANK0_GPIO0_DRIVE_SHIFT)
|
||||
#define RP2040_PADS_BANK0_GPIO_DRIVE_4MA (0x1 << RP2040_PADS_BANK0_GPIO0_DRIVE_SHIFT)
|
||||
#define RP2040_PADS_BANK0_GPIO_DRIVE_8MA (0x2 << RP2040_PADS_BANK0_GPIO0_DRIVE_SHIFT)
|
||||
#define RP2040_PADS_BANK0_GPIO_DRIVE_12MA (0x3 << RP2040_PADS_BANK0_GPIO0_DRIVE_SHIFT)
|
||||
#define RP2040_PADS_BANK0_GPIO_PUE (1 << 3) /* Pull up enable */
|
||||
#define RP2040_PADS_BANK0_GPIO_PDE (1 << 2) /* Pull down enable */
|
||||
#define RP2040_PADS_BANK0_GPIO_SCHMITT (1 << 1) /* Enable schmitt trigger */
|
||||
#define RP2040_PADS_BANK0_GPIO_SLEWFAST (1 << 0) /* Slew rate control. 1 = Fast, 0 = Slow */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_PADS_BANK0_H */
|
||||
90
arch/arm/src/rp2040/hardware/rp2040_pll.h
Normal file
90
arch/arm/src/rp2040/hardware/rp2040_pll.h
Normal file
@ -0,0 +1,90 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/hardware/rp2040_pll.h
|
||||
*
|
||||
* Generated from rp2040.svd originally provided by
|
||||
* Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_PLL_H
|
||||
#define __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_PLL_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hardware/rp2040_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define RP2040_PLL_CS_OFFSET 0x000000 /* Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=400MHz, max=1600MHz */
|
||||
#define RP2040_PLL_PWR_OFFSET 0x000004 /* Controls the PLL power modes. */
|
||||
#define RP2040_PLL_FBDIV_INT_OFFSET 0x000008 /* Feedback divisor (note: this PLL does not support fractional division) */
|
||||
#define RP2040_PLL_PRIM_OFFSET 0x00000c /* Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2 */
|
||||
|
||||
/* Register definitions (PLL_SYS) *******************************************/
|
||||
|
||||
#define RP2040_PLL_SYS_CS (RP2040_PLL_SYS_BASE + RP2040_PLL_CS_OFFSET)
|
||||
#define RP2040_PLL_SYS_PWR (RP2040_PLL_SYS_BASE + RP2040_PLL_PWR_OFFSET)
|
||||
#define RP2040_PLL_SYS_FBDIV_INT (RP2040_PLL_SYS_BASE + RP2040_PLL_FBDIV_INT_OFFSET)
|
||||
#define RP2040_PLL_SYS_PRIM (RP2040_PLL_SYS_BASE + RP2040_PLL_PRIM_OFFSET)
|
||||
|
||||
/* Register definitions (PLL_USB) *******************************************/
|
||||
|
||||
#define RP2040_PLL_USB_CS (RP2040_PLL_USB_BASE + RP2040_PLL_CS_OFFSET)
|
||||
#define RP2040_PLL_USB_PWR (RP2040_PLL_USB_BASE + RP2040_PLL_PWR_OFFSET)
|
||||
#define RP2040_PLL_USB_FBDIV_INT (RP2040_PLL_USB_BASE + RP2040_PLL_FBDIV_INT_OFFSET)
|
||||
#define RP2040_PLL_USB_PRIM (RP2040_PLL_USB_BASE + RP2040_PLL_PRIM_OFFSET)
|
||||
|
||||
/* Register bit definitions *************************************************/
|
||||
|
||||
#define RP2040_PLL_CS_LOCK (1 << 31) /* PLL is locked */
|
||||
#define RP2040_PLL_CS_BYPASS (1 << 8) /* Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. */
|
||||
#define RP2040_PLL_CS_REFDIV_MASK (0x3f) /* Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. */
|
||||
|
||||
#define RP2040_PLL_PWR_VCOPD (1 << 5) /* PLL VCO powerdown To save power set high when PLL output not required or bypass=1. */
|
||||
#define RP2040_PLL_PWR_POSTDIVPD (1 << 3) /* PLL post divider powerdown To save power set high when PLL output not required or bypass=1. */
|
||||
#define RP2040_PLL_PWR_DSMPD (1 << 2) /* PLL DSM powerdown Nothing is achieved by setting this low. */
|
||||
#define RP2040_PLL_PWR_PD (1 << 0) /* PLL powerdown To save power set high when PLL output not required. */
|
||||
|
||||
#define RP2040_PLL_FBDIV_INT_MASK (0xfff) /* see ctrl reg description for constraints */
|
||||
|
||||
#define RP2040_PLL_PRIM_POSTDIV1_SHIFT (16) /* divide by 1-7 */
|
||||
#define RP2040_PLL_PRIM_POSTDIV1_MASK (0x07 << RP2040_PLL_PRIM_POSTDIV1_SHIFT)
|
||||
#define RP2040_PLL_PRIM_POSTDIV2_SHIFT (12) /* divide by 1-7 */
|
||||
#define RP2040_PLL_PRIM_POSTDIV2_MASK (0x07 << RP2040_PLL_PRIM_POSTDIV2_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_PLL_H */
|
||||
143
arch/arm/src/rp2040/hardware/rp2040_resets.h
Normal file
143
arch/arm/src/rp2040/hardware/rp2040_resets.h
Normal file
@ -0,0 +1,143 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/hardware/rp2040_resets.h
|
||||
*
|
||||
* Generated from rp2040.svd originally provided by
|
||||
* Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_RESETS_H
|
||||
#define __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_RESETS_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hardware/rp2040_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define RP2040_RESETS_RESET_OFFSET 0x000000 /* Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. */
|
||||
#define RP2040_RESETS_WDSEL_OFFSET 0x000004 /* Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. */
|
||||
#define RP2040_RESETS_RESET_DONE_OFFSET 0x000008 /* Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. */
|
||||
|
||||
/* Register definitions *****************************************************/
|
||||
|
||||
#define RP2040_RESETS_RESET (RP2040_RESETS_BASE + RP2040_RESETS_RESET_OFFSET)
|
||||
#define RP2040_RESETS_WDSEL (RP2040_RESETS_BASE + RP2040_RESETS_WDSEL_OFFSET)
|
||||
#define RP2040_RESETS_RESET_DONE (RP2040_RESETS_BASE + RP2040_RESETS_RESET_DONE_OFFSET)
|
||||
|
||||
/* Register bit definitions *************************************************/
|
||||
|
||||
#define RP2040_RESETS_RESET_USBCTRL (1 << 24)
|
||||
#define RP2040_RESETS_RESET_UART1 (1 << 23)
|
||||
#define RP2040_RESETS_RESET_UART0 (1 << 22)
|
||||
#define RP2040_RESETS_RESET_TIMER (1 << 21)
|
||||
#define RP2040_RESETS_RESET_TBMAN (1 << 20)
|
||||
#define RP2040_RESETS_RESET_SYSINFO (1 << 19)
|
||||
#define RP2040_RESETS_RESET_SYSCFG (1 << 18)
|
||||
#define RP2040_RESETS_RESET_SPI1 (1 << 17)
|
||||
#define RP2040_RESETS_RESET_SPI0 (1 << 16)
|
||||
#define RP2040_RESETS_RESET_RTC (1 << 15)
|
||||
#define RP2040_RESETS_RESET_PWM (1 << 14)
|
||||
#define RP2040_RESETS_RESET_PLL_USB (1 << 13)
|
||||
#define RP2040_RESETS_RESET_PLL_SYS (1 << 12)
|
||||
#define RP2040_RESETS_RESET_PIO1 (1 << 11)
|
||||
#define RP2040_RESETS_RESET_PIO0 (1 << 10)
|
||||
#define RP2040_RESETS_RESET_PADS_QSPI (1 << 9)
|
||||
#define RP2040_RESETS_RESET_PADS_BANK0 (1 << 8)
|
||||
#define RP2040_RESETS_RESET_JTAG (1 << 7)
|
||||
#define RP2040_RESETS_RESET_IO_QSPI (1 << 6)
|
||||
#define RP2040_RESETS_RESET_IO_BANK0 (1 << 5)
|
||||
#define RP2040_RESETS_RESET_I2C1 (1 << 4)
|
||||
#define RP2040_RESETS_RESET_I2C0 (1 << 3)
|
||||
#define RP2040_RESETS_RESET_DMA (1 << 2)
|
||||
#define RP2040_RESETS_RESET_BUSCTRL (1 << 1)
|
||||
#define RP2040_RESETS_RESET_ADC (1 << 0)
|
||||
|
||||
#define RP2040_RESETS_WDSEL_USBCTRL (1 << 24)
|
||||
#define RP2040_RESETS_WDSEL_UART1 (1 << 23)
|
||||
#define RP2040_RESETS_WDSEL_UART0 (1 << 22)
|
||||
#define RP2040_RESETS_WDSEL_TIMER (1 << 21)
|
||||
#define RP2040_RESETS_WDSEL_TBMAN (1 << 20)
|
||||
#define RP2040_RESETS_WDSEL_SYSINFO (1 << 19)
|
||||
#define RP2040_RESETS_WDSEL_SYSCFG (1 << 18)
|
||||
#define RP2040_RESETS_WDSEL_SPI1 (1 << 17)
|
||||
#define RP2040_RESETS_WDSEL_SPI0 (1 << 16)
|
||||
#define RP2040_RESETS_WDSEL_RTC (1 << 15)
|
||||
#define RP2040_RESETS_WDSEL_PWM (1 << 14)
|
||||
#define RP2040_RESETS_WDSEL_PLL_USB (1 << 13)
|
||||
#define RP2040_RESETS_WDSEL_PLL_SYS (1 << 12)
|
||||
#define RP2040_RESETS_WDSEL_PIO1 (1 << 11)
|
||||
#define RP2040_RESETS_WDSEL_PIO0 (1 << 10)
|
||||
#define RP2040_RESETS_WDSEL_PADS_QSPI (1 << 9)
|
||||
#define RP2040_RESETS_WDSEL_PADS_BANK0 (1 << 8)
|
||||
#define RP2040_RESETS_WDSEL_JTAG (1 << 7)
|
||||
#define RP2040_RESETS_WDSEL_IO_QSPI (1 << 6)
|
||||
#define RP2040_RESETS_WDSEL_IO_BANK0 (1 << 5)
|
||||
#define RP2040_RESETS_WDSEL_I2C1 (1 << 4)
|
||||
#define RP2040_RESETS_WDSEL_I2C0 (1 << 3)
|
||||
#define RP2040_RESETS_WDSEL_DMA (1 << 2)
|
||||
#define RP2040_RESETS_WDSEL_BUSCTRL (1 << 1)
|
||||
#define RP2040_RESETS_WDSEL_ADC (1 << 0)
|
||||
|
||||
#define RP2040_RESETS_RESET_DONE_USBCTRL (1 << 24)
|
||||
#define RP2040_RESETS_RESET_DONE_UART1 (1 << 23)
|
||||
#define RP2040_RESETS_RESET_DONE_UART0 (1 << 22)
|
||||
#define RP2040_RESETS_RESET_DONE_TIMER (1 << 21)
|
||||
#define RP2040_RESETS_RESET_DONE_TBMAN (1 << 20)
|
||||
#define RP2040_RESETS_RESET_DONE_SYSINFO (1 << 19)
|
||||
#define RP2040_RESETS_RESET_DONE_SYSCFG (1 << 18)
|
||||
#define RP2040_RESETS_RESET_DONE_SPI1 (1 << 17)
|
||||
#define RP2040_RESETS_RESET_DONE_SPI0 (1 << 16)
|
||||
#define RP2040_RESETS_RESET_DONE_RTC (1 << 15)
|
||||
#define RP2040_RESETS_RESET_DONE_PWM (1 << 14)
|
||||
#define RP2040_RESETS_RESET_DONE_PLL_USB (1 << 13)
|
||||
#define RP2040_RESETS_RESET_DONE_PLL_SYS (1 << 12)
|
||||
#define RP2040_RESETS_RESET_DONE_PIO1 (1 << 11)
|
||||
#define RP2040_RESETS_RESET_DONE_PIO0 (1 << 10)
|
||||
#define RP2040_RESETS_RESET_DONE_PADS_QSPI (1 << 9)
|
||||
#define RP2040_RESETS_RESET_DONE_PADS_BANK0 (1 << 8)
|
||||
#define RP2040_RESETS_RESET_DONE_JTAG (1 << 7)
|
||||
#define RP2040_RESETS_RESET_DONE_IO_QSPI (1 << 6)
|
||||
#define RP2040_RESETS_RESET_DONE_IO_BANK0 (1 << 5)
|
||||
#define RP2040_RESETS_RESET_DONE_I2C1 (1 << 4)
|
||||
#define RP2040_RESETS_RESET_DONE_I2C0 (1 << 3)
|
||||
#define RP2040_RESETS_RESET_DONE_DMA (1 << 2)
|
||||
#define RP2040_RESETS_RESET_DONE_BUSCTRL (1 << 1)
|
||||
#define RP2040_RESETS_RESET_DONE_ADC (1 << 0)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_RESETS_H */
|
||||
127
arch/arm/src/rp2040/hardware/rp2040_rosc.h
Normal file
127
arch/arm/src/rp2040/hardware/rp2040_rosc.h
Normal file
@ -0,0 +1,127 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/hardware/rp2040_rosc.h
|
||||
*
|
||||
* Generated from rp2040.svd originally provided by
|
||||
* Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_ROSC_H
|
||||
#define __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_ROSC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hardware/rp2040_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define RP2040_ROSC_CTRL_OFFSET 0x000000 /* Ring Oscillator control */
|
||||
#define RP2040_ROSC_FREQA_OFFSET 0x000004 /* The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength */
|
||||
#define RP2040_ROSC_FREQB_OFFSET 0x000008 /* For a detailed description see freqa register */
|
||||
#define RP2040_ROSC_DORMANT_OFFSET 0x00000c /* Ring Oscillator pause control This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode */
|
||||
#define RP2040_ROSC_DIV_OFFSET 0x000010 /* Controls the output divider */
|
||||
#define RP2040_ROSC_PHASE_OFFSET 0x000014 /* Controls the phase shifted output */
|
||||
#define RP2040_ROSC_STATUS_OFFSET 0x000018 /* Ring Oscillator Status */
|
||||
#define RP2040_ROSC_RANDOMBIT_OFFSET 0x00001c /* This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency */
|
||||
#define RP2040_ROSC_COUNT_OFFSET 0x000020 /* A down counter running at the ROSC frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware. */
|
||||
|
||||
/* Register definitions *****************************************************/
|
||||
|
||||
#define RP2040_ROSC_CTRL (RP2040_ROSC_BASE + RP2040_ROSC_CTRL_OFFSET)
|
||||
#define RP2040_ROSC_FREQA (RP2040_ROSC_BASE + RP2040_ROSC_FREQA_OFFSET)
|
||||
#define RP2040_ROSC_FREQB (RP2040_ROSC_BASE + RP2040_ROSC_FREQB_OFFSET)
|
||||
#define RP2040_ROSC_DORMANT (RP2040_ROSC_BASE + RP2040_ROSC_DORMANT_OFFSET)
|
||||
#define RP2040_ROSC_DIV (RP2040_ROSC_BASE + RP2040_ROSC_DIV_OFFSET)
|
||||
#define RP2040_ROSC_PHASE (RP2040_ROSC_BASE + RP2040_ROSC_PHASE_OFFSET)
|
||||
#define RP2040_ROSC_STATUS (RP2040_ROSC_BASE + RP2040_ROSC_STATUS_OFFSET)
|
||||
#define RP2040_ROSC_RANDOMBIT (RP2040_ROSC_BASE + RP2040_ROSC_RANDOMBIT_OFFSET)
|
||||
#define RP2040_ROSC_COUNT (RP2040_ROSC_BASE + RP2040_ROSC_COUNT_OFFSET)
|
||||
|
||||
/* Register bit definitions *************************************************/
|
||||
|
||||
#define RP2040_ROSC_CTRL_ENABLE_SHIFT (12) /* On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. */
|
||||
#define RP2040_ROSC_CTRL_ENABLE_MASK (0xfff << RP2040_ROSC_CTRL_ENABLE_SHIFT)
|
||||
#define RP2040_ROSC_CTRL_ENABLE_DISABLE (0xd1e << RP2040_ROSC_CTRL_ENABLE_SHIFT)
|
||||
#define RP2040_ROSC_CTRL_ENABLE_ENABLE (0xfab << RP2040_ROSC_CTRL_ENABLE_SHIFT)
|
||||
#define RP2040_ROSC_CTRL_FREQ_RANGE_MASK (0xfff)
|
||||
#define RP2040_ROSC_CTRL_FREQ_RANGE_LOW (0xfa4)
|
||||
#define RP2040_ROSC_CTRL_FREQ_RANGE_MEDIUM (0xfa5)
|
||||
#define RP2040_ROSC_CTRL_FREQ_RANGE_HIGH (0xfa7)
|
||||
#define RP2040_ROSC_CTRL_FREQ_RANGE_TOOHIGH (0xfa6)
|
||||
|
||||
#define RP2040_ROSC_FREQA_PASSWD_SHIFT (16) /* Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 */
|
||||
#define RP2040_ROSC_FREQA_PASSWD_MASK (0xffff << RP2040_ROSC_FREQA_PASSWD_SHIFT)
|
||||
#define RP2040_ROSC_FREQA_PASSWD_PASS (0x9696 << RP2040_ROSC_FREQA_PASSWD_SHIFT)
|
||||
#define RP2040_ROSC_FREQA_DS3_SHIFT (12) /* Stage 3 drive strength */
|
||||
#define RP2040_ROSC_FREQA_DS3_MASK (0x07 << RP2040_ROSC_FREQA_DS3_SHIFT)
|
||||
#define RP2040_ROSC_FREQA_DS2_SHIFT (8) /* Stage 2 drive strength */
|
||||
#define RP2040_ROSC_FREQA_DS2_MASK (0x07 << RP2040_ROSC_FREQA_DS2_SHIFT)
|
||||
#define RP2040_ROSC_FREQA_DS1_SHIFT (4) /* Stage 1 drive strength */
|
||||
#define RP2040_ROSC_FREQA_DS1_MASK (0x07 << RP2040_ROSC_FREQA_DS1_SHIFT)
|
||||
#define RP2040_ROSC_FREQA_DS0_MASK (0x07) /* Stage 0 drive strength */
|
||||
|
||||
#define RP2040_ROSC_FREQB_PASSWD_SHIFT (16) /* Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 */
|
||||
#define RP2040_ROSC_FREQB_PASSWD_MASK (0xffff << RP2040_ROSC_FREQB_PASSWD_SHIFT)
|
||||
#define RP2040_ROSC_FREQB_PASSWD_PASS (0x9696 << RP2040_ROSC_FREQB_PASSWD_SHIFT)
|
||||
#define RP2040_ROSC_FREQB_DS7_SHIFT (12) /* Stage 7 drive strength */
|
||||
#define RP2040_ROSC_FREQB_DS7_MASK (0x07 << RP2040_ROSC_FREQB_DS7_SHIFT)
|
||||
#define RP2040_ROSC_FREQB_DS6_SHIFT (8) /* Stage 6 drive strength */
|
||||
#define RP2040_ROSC_FREQB_DS6_MASK (0x07 << RP2040_ROSC_FREQB_DS6_SHIFT)
|
||||
#define RP2040_ROSC_FREQB_DS5_SHIFT (4) /* Stage 5 drive strength */
|
||||
#define RP2040_ROSC_FREQB_DS5_MASK (0x07 << RP2040_ROSC_FREQB_DS5_SHIFT)
|
||||
#define RP2040_ROSC_FREQB_DS4_MASK (0x07) /* Stage 4 drive strength */
|
||||
|
||||
#define RP2040_ROSC_DIV_MASK (0xfff)
|
||||
#define RP2040_ROSC_DIV_PASS (0xaa0)
|
||||
|
||||
#define RP2040_ROSC_PHASE_PASSWD_SHIFT (4) /* set to 0xaa0 any other value enables the output with shift=0 */
|
||||
#define RP2040_ROSC_PHASE_PASSWD_MASK (0xff << RP2040_ROSC_PHASE_PASSWD_SHIFT)
|
||||
#define RP2040_ROSC_PHASE_ENABLE (1 << 3) /* enable the phase-shifted output this can be changed on-the-fly */
|
||||
#define RP2040_ROSC_PHASE_FLIP (1 << 2) /* invert the phase-shifted output this is ignored when div=1 */
|
||||
#define RP2040_ROSC_PHASE_SHIFT_MASK (0x03) /* phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1 */
|
||||
|
||||
#define RP2040_ROSC_STATUS_STABLE (1 << 31) /* Oscillator is running and stable */
|
||||
#define RP2040_ROSC_STATUS_BADWRITE (1 << 24) /* An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT */
|
||||
#define RP2040_ROSC_STATUS_DIV_RUNNING (1 << 16) /* post-divider is running this resets to 0 but transitions to 1 during chip startup */
|
||||
#define RP2040_ROSC_STATUS_ENABLED (1 << 12) /* Oscillator is enabled but not necessarily running and stable this resets to 0 but transitions to 1 during chip startup */
|
||||
|
||||
#define RP2040_ROSC_RANDOMBIT (1 << 0)
|
||||
|
||||
#define RP2040_ROSC_COUNT_MASK (0xff)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_ROSC_H */
|
||||
355
arch/arm/src/rp2040/hardware/rp2040_sio.h
Normal file
355
arch/arm/src/rp2040/hardware/rp2040_sio.h
Normal file
@ -0,0 +1,355 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/hardware/rp2040_sio.h
|
||||
*
|
||||
* Generated from rp2040.svd originally provided by
|
||||
* Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_SIO_H
|
||||
#define __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_SIO_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hardware/rp2040_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define RP2040_SIO_CPUID_OFFSET 0x000000 /* Processor core identifier Value is 0 when read from processor core 0, and 1 when read from processor core 1. */
|
||||
#define RP2040_SIO_GPIO_IN_OFFSET 0x000004 /* Input value for GPIO pins */
|
||||
#define RP2040_SIO_GPIO_HI_IN_OFFSET 0x000008 /* Input value for QSPI pins */
|
||||
#define RP2040_SIO_GPIO_OUT_OFFSET 0x000010 /* GPIO output value */
|
||||
#define RP2040_SIO_GPIO_OUT_SET_OFFSET 0x000014 /* GPIO output value set */
|
||||
#define RP2040_SIO_GPIO_OUT_CLR_OFFSET 0x000018 /* GPIO output value clear */
|
||||
#define RP2040_SIO_GPIO_OUT_XOR_OFFSET 0x00001c /* GPIO output value XOR */
|
||||
#define RP2040_SIO_GPIO_OE_OFFSET 0x000020 /* GPIO output enable */
|
||||
#define RP2040_SIO_GPIO_OE_SET_OFFSET 0x000024 /* GPIO output enable set */
|
||||
#define RP2040_SIO_GPIO_OE_CLR_OFFSET 0x000028 /* GPIO output enable clear */
|
||||
#define RP2040_SIO_GPIO_OE_XOR_OFFSET 0x00002c /* GPIO output enable XOR */
|
||||
#define RP2040_SIO_GPIO_HI_OUT_OFFSET 0x000030 /* QSPI output value */
|
||||
#define RP2040_SIO_GPIO_HI_OUT_SET_OFFSET 0x000034 /* QSPI output value set */
|
||||
#define RP2040_SIO_GPIO_HI_OUT_CLR_OFFSET 0x000038 /* QSPI output value clear */
|
||||
#define RP2040_SIO_GPIO_HI_OUT_XOR_OFFSET 0x00003c /* QSPI output value XOR */
|
||||
#define RP2040_SIO_GPIO_HI_OE_OFFSET 0x000040 /* QSPI output enable */
|
||||
#define RP2040_SIO_GPIO_HI_OE_SET_OFFSET 0x000044 /* QSPI output enable set */
|
||||
#define RP2040_SIO_GPIO_HI_OE_CLR_OFFSET 0x000048 /* QSPI output enable clear */
|
||||
#define RP2040_SIO_GPIO_HI_OE_XOR_OFFSET 0x00004c /* QSPI output enable XOR */
|
||||
#define RP2040_SIO_FIFO_ST_OFFSET 0x000050 /* Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. */
|
||||
#define RP2040_SIO_FIFO_WR_OFFSET 0x000054 /* Write access to this core's TX FIFO */
|
||||
#define RP2040_SIO_FIFO_RD_OFFSET 0x000058 /* Read access to this core's RX FIFO */
|
||||
#define RP2040_SIO_SPINLOCK_ST_OFFSET 0x00005c /* Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging. */
|
||||
#define RP2040_SIO_DIV_UDIVIDEND_OFFSET 0x000060 /* Divider unsigned dividend Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation. */
|
||||
#define RP2040_SIO_DIV_UDIVISOR_OFFSET 0x000064 /* Divider unsigned divisor Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation. */
|
||||
#define RP2040_SIO_DIV_SDIVIDEND_OFFSET 0x000068 /* Divider signed dividend The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. */
|
||||
#define RP2040_SIO_DIV_SDIVISOR_OFFSET 0x00006c /* Divider signed divisor The same as UDIVISOR, but starts a signed calculation, rather than unsigned. */
|
||||
#define RP2040_SIO_DIV_QUOTIENT_OFFSET 0x000070 /* Divider result quotient The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order REMAINDER, QUOTIENT if CSR_DIRTY is used. */
|
||||
#define RP2040_SIO_DIV_REMAINDER_OFFSET 0x000074 /* Divider result remainder The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. For signed calculations, REMAINDER is negative only when DIVIDEND is negative. This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. */
|
||||
#define RP2040_SIO_DIV_CSR_OFFSET 0x000078 /* Control and status register for divider. */
|
||||
#define RP2040_SIO_INTERP0_ACCUM0_OFFSET 0x000080 /* Read/write access to accumulator 0 */
|
||||
#define RP2040_SIO_INTERP0_ACCUM1_OFFSET 0x000084 /* Read/write access to accumulator 1 */
|
||||
#define RP2040_SIO_INTERP0_BASE0_OFFSET 0x000088 /* Read/write access to BASE0 register. */
|
||||
#define RP2040_SIO_INTERP0_BASE1_OFFSET 0x00008c /* Read/write access to BASE1 register. */
|
||||
#define RP2040_SIO_INTERP0_BASE2_OFFSET 0x000090 /* Read/write access to BASE2 register. */
|
||||
#define RP2040_SIO_INTERP0_POP_LANE0_OFFSET 0x000094 /* Read LANE0 result, and simultaneously write lane results to both accumulators (POP). */
|
||||
#define RP2040_SIO_INTERP0_POP_LANE1_OFFSET 0x000098 /* Read LANE1 result, and simultaneously write lane results to both accumulators (POP). */
|
||||
#define RP2040_SIO_INTERP0_POP_FULL_OFFSET 0x00009c /* Read FULL result, and simultaneously write lane results to both accumulators (POP). */
|
||||
#define RP2040_SIO_INTERP0_PEEK_LANE0_OFFSET 0x0000a0 /* Read LANE0 result, without altering any internal state (PEEK). */
|
||||
#define RP2040_SIO_INTERP0_PEEK_LANE1_OFFSET 0x0000a4 /* Read LANE1 result, without altering any internal state (PEEK). */
|
||||
#define RP2040_SIO_INTERP0_PEEK_FULL_OFFSET 0x0000a8 /* Read FULL result, without altering any internal state (PEEK). */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_OFFSET 0x0000ac /* Control register for lane 0 */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE1_OFFSET 0x0000b0 /* Control register for lane 1 */
|
||||
#define RP2040_SIO_INTERP0_ACCUM0_ADD_OFFSET 0x0000b4 /* Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). */
|
||||
#define RP2040_SIO_INTERP0_ACCUM1_ADD_OFFSET 0x0000b8 /* Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). */
|
||||
#define RP2040_SIO_INTERP0_BASE_1AND0_OFFSET 0x0000bc /* On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. */
|
||||
#define RP2040_SIO_INTERP1_ACCUM0_OFFSET 0x0000c0 /* Read/write access to accumulator 0 */
|
||||
#define RP2040_SIO_INTERP1_ACCUM1_OFFSET 0x0000c4 /* Read/write access to accumulator 1 */
|
||||
#define RP2040_SIO_INTERP1_BASE0_OFFSET 0x0000c8 /* Read/write access to BASE0 register. */
|
||||
#define RP2040_SIO_INTERP1_BASE1_OFFSET 0x0000cc /* Read/write access to BASE1 register. */
|
||||
#define RP2040_SIO_INTERP1_BASE2_OFFSET 0x0000d0 /* Read/write access to BASE2 register. */
|
||||
#define RP2040_SIO_INTERP1_POP_LANE0_OFFSET 0x0000d4 /* Read LANE0 result, and simultaneously write lane results to both accumulators (POP). */
|
||||
#define RP2040_SIO_INTERP1_POP_LANE1_OFFSET 0x0000d8 /* Read LANE1 result, and simultaneously write lane results to both accumulators (POP). */
|
||||
#define RP2040_SIO_INTERP1_POP_FULL_OFFSET 0x0000dc /* Read FULL result, and simultaneously write lane results to both accumulators (POP). */
|
||||
#define RP2040_SIO_INTERP1_PEEK_LANE0_OFFSET 0x0000e0 /* Read LANE0 result, without altering any internal state (PEEK). */
|
||||
#define RP2040_SIO_INTERP1_PEEK_LANE1_OFFSET 0x0000e4 /* Read LANE1 result, without altering any internal state (PEEK). */
|
||||
#define RP2040_SIO_INTERP1_PEEK_FULL_OFFSET 0x0000e8 /* Read FULL result, without altering any internal state (PEEK). */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_OFFSET 0x0000ec /* Control register for lane 0 */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE1_OFFSET 0x0000f0 /* Control register for lane 1 */
|
||||
#define RP2040_SIO_INTERP1_ACCUM0_ADD_OFFSET 0x0000f4 /* Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). */
|
||||
#define RP2040_SIO_INTERP1_ACCUM1_ADD_OFFSET 0x0000f8 /* Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). */
|
||||
#define RP2040_SIO_INTERP1_BASE_1AND0_OFFSET 0x0000fc /* On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. */
|
||||
#define RP2040_SIO_SPINLOCK0_OFFSET 0x000100 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK1_OFFSET 0x000104 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK2_OFFSET 0x000108 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK3_OFFSET 0x00010c /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK4_OFFSET 0x000110 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK5_OFFSET 0x000114 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK6_OFFSET 0x000118 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK7_OFFSET 0x00011c /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK8_OFFSET 0x000120 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK9_OFFSET 0x000124 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK10_OFFSET 0x000128 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK11_OFFSET 0x00012c /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK12_OFFSET 0x000130 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK13_OFFSET 0x000134 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK14_OFFSET 0x000138 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK15_OFFSET 0x00013c /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK16_OFFSET 0x000140 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK17_OFFSET 0x000144 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK18_OFFSET 0x000148 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK19_OFFSET 0x00014c /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK20_OFFSET 0x000150 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK21_OFFSET 0x000154 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK22_OFFSET 0x000158 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK23_OFFSET 0x00015c /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK24_OFFSET 0x000160 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK25_OFFSET 0x000164 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK26_OFFSET 0x000168 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK27_OFFSET 0x00016c /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK28_OFFSET 0x000170 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK29_OFFSET 0x000174 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK30_OFFSET 0x000178 /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
#define RP2040_SIO_SPINLOCK31_OFFSET 0x00017c /* Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */
|
||||
|
||||
/* Register definitions *****************************************************/
|
||||
|
||||
#define RP2040_SIO_CPUID (RP2040_SIO_BASE + RP2040_SIO_CPUID_OFFSET)
|
||||
#define RP2040_SIO_GPIO_IN (RP2040_SIO_BASE + RP2040_SIO_GPIO_IN_OFFSET)
|
||||
#define RP2040_SIO_GPIO_HI_IN (RP2040_SIO_BASE + RP2040_SIO_GPIO_HI_IN_OFFSET)
|
||||
#define RP2040_SIO_GPIO_OUT (RP2040_SIO_BASE + RP2040_SIO_GPIO_OUT_OFFSET)
|
||||
#define RP2040_SIO_GPIO_OUT_SET (RP2040_SIO_BASE + RP2040_SIO_GPIO_OUT_SET_OFFSET)
|
||||
#define RP2040_SIO_GPIO_OUT_CLR (RP2040_SIO_BASE + RP2040_SIO_GPIO_OUT_CLR_OFFSET)
|
||||
#define RP2040_SIO_GPIO_OUT_XOR (RP2040_SIO_BASE + RP2040_SIO_GPIO_OUT_XOR_OFFSET)
|
||||
#define RP2040_SIO_GPIO_OE (RP2040_SIO_BASE + RP2040_SIO_GPIO_OE_OFFSET)
|
||||
#define RP2040_SIO_GPIO_OE_SET (RP2040_SIO_BASE + RP2040_SIO_GPIO_OE_SET_OFFSET)
|
||||
#define RP2040_SIO_GPIO_OE_CLR (RP2040_SIO_BASE + RP2040_SIO_GPIO_OE_CLR_OFFSET)
|
||||
#define RP2040_SIO_GPIO_OE_XOR (RP2040_SIO_BASE + RP2040_SIO_GPIO_OE_XOR_OFFSET)
|
||||
#define RP2040_SIO_GPIO_HI_OUT (RP2040_SIO_BASE + RP2040_SIO_GPIO_HI_OUT_OFFSET)
|
||||
#define RP2040_SIO_GPIO_HI_OUT_SET (RP2040_SIO_BASE + RP2040_SIO_GPIO_HI_OUT_SET_OFFSET)
|
||||
#define RP2040_SIO_GPIO_HI_OUT_CLR (RP2040_SIO_BASE + RP2040_SIO_GPIO_HI_OUT_CLR_OFFSET)
|
||||
#define RP2040_SIO_GPIO_HI_OUT_XOR (RP2040_SIO_BASE + RP2040_SIO_GPIO_HI_OUT_XOR_OFFSET)
|
||||
#define RP2040_SIO_GPIO_HI_OE (RP2040_SIO_BASE + RP2040_SIO_GPIO_HI_OE_OFFSET)
|
||||
#define RP2040_SIO_GPIO_HI_OE_SET (RP2040_SIO_BASE + RP2040_SIO_GPIO_HI_OE_SET_OFFSET)
|
||||
#define RP2040_SIO_GPIO_HI_OE_CLR (RP2040_SIO_BASE + RP2040_SIO_GPIO_HI_OE_CLR_OFFSET)
|
||||
#define RP2040_SIO_GPIO_HI_OE_XOR (RP2040_SIO_BASE + RP2040_SIO_GPIO_HI_OE_XOR_OFFSET)
|
||||
#define RP2040_SIO_FIFO_ST (RP2040_SIO_BASE + RP2040_SIO_FIFO_ST_OFFSET)
|
||||
#define RP2040_SIO_FIFO_WR (RP2040_SIO_BASE + RP2040_SIO_FIFO_WR_OFFSET)
|
||||
#define RP2040_SIO_FIFO_RD (RP2040_SIO_BASE + RP2040_SIO_FIFO_RD_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK_ST (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK_ST_OFFSET)
|
||||
#define RP2040_SIO_DIV_UDIVIDEND (RP2040_SIO_BASE + RP2040_SIO_DIV_UDIVIDEND_OFFSET)
|
||||
#define RP2040_SIO_DIV_UDIVISOR (RP2040_SIO_BASE + RP2040_SIO_DIV_UDIVISOR_OFFSET)
|
||||
#define RP2040_SIO_DIV_SDIVIDEND (RP2040_SIO_BASE + RP2040_SIO_DIV_SDIVIDEND_OFFSET)
|
||||
#define RP2040_SIO_DIV_SDIVISOR (RP2040_SIO_BASE + RP2040_SIO_DIV_SDIVISOR_OFFSET)
|
||||
#define RP2040_SIO_DIV_QUOTIENT (RP2040_SIO_BASE + RP2040_SIO_DIV_QUOTIENT_OFFSET)
|
||||
#define RP2040_SIO_DIV_REMAINDER (RP2040_SIO_BASE + RP2040_SIO_DIV_REMAINDER_OFFSET)
|
||||
#define RP2040_SIO_DIV_CSR (RP2040_SIO_BASE + RP2040_SIO_DIV_CSR_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_ACCUM0 (RP2040_SIO_BASE + RP2040_SIO_INTERP0_ACCUM0_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_ACCUM1 (RP2040_SIO_BASE + RP2040_SIO_INTERP0_ACCUM1_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_BASE0 (RP2040_SIO_BASE + RP2040_SIO_INTERP0_BASE0_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_BASE1 (RP2040_SIO_BASE + RP2040_SIO_INTERP0_BASE1_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_BASE2 (RP2040_SIO_BASE + RP2040_SIO_INTERP0_BASE2_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_POP_LANE0 (RP2040_SIO_BASE + RP2040_SIO_INTERP0_POP_LANE0_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_POP_LANE1 (RP2040_SIO_BASE + RP2040_SIO_INTERP0_POP_LANE1_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_POP_FULL (RP2040_SIO_BASE + RP2040_SIO_INTERP0_POP_FULL_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_PEEK_LANE0 (RP2040_SIO_BASE + RP2040_SIO_INTERP0_PEEK_LANE0_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_PEEK_LANE1 (RP2040_SIO_BASE + RP2040_SIO_INTERP0_PEEK_LANE1_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_PEEK_FULL (RP2040_SIO_BASE + RP2040_SIO_INTERP0_PEEK_FULL_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0 (RP2040_SIO_BASE + RP2040_SIO_INTERP0_CTRL_LANE0_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE1 (RP2040_SIO_BASE + RP2040_SIO_INTERP0_CTRL_LANE1_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_ACCUM0_ADD (RP2040_SIO_BASE + RP2040_SIO_INTERP0_ACCUM0_ADD_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_ACCUM1_ADD (RP2040_SIO_BASE + RP2040_SIO_INTERP0_ACCUM1_ADD_OFFSET)
|
||||
#define RP2040_SIO_INTERP0_BASE_1AND0 (RP2040_SIO_BASE + RP2040_SIO_INTERP0_BASE_1AND0_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_ACCUM0 (RP2040_SIO_BASE + RP2040_SIO_INTERP1_ACCUM0_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_ACCUM1 (RP2040_SIO_BASE + RP2040_SIO_INTERP1_ACCUM1_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_BASE0 (RP2040_SIO_BASE + RP2040_SIO_INTERP1_BASE0_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_BASE1 (RP2040_SIO_BASE + RP2040_SIO_INTERP1_BASE1_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_BASE2 (RP2040_SIO_BASE + RP2040_SIO_INTERP1_BASE2_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_POP_LANE0 (RP2040_SIO_BASE + RP2040_SIO_INTERP1_POP_LANE0_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_POP_LANE1 (RP2040_SIO_BASE + RP2040_SIO_INTERP1_POP_LANE1_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_POP_FULL (RP2040_SIO_BASE + RP2040_SIO_INTERP1_POP_FULL_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_PEEK_LANE0 (RP2040_SIO_BASE + RP2040_SIO_INTERP1_PEEK_LANE0_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_PEEK_LANE1 (RP2040_SIO_BASE + RP2040_SIO_INTERP1_PEEK_LANE1_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_PEEK_FULL (RP2040_SIO_BASE + RP2040_SIO_INTERP1_PEEK_FULL_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0 (RP2040_SIO_BASE + RP2040_SIO_INTERP1_CTRL_LANE0_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE1 (RP2040_SIO_BASE + RP2040_SIO_INTERP1_CTRL_LANE1_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_ACCUM0_ADD (RP2040_SIO_BASE + RP2040_SIO_INTERP1_ACCUM0_ADD_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_ACCUM1_ADD (RP2040_SIO_BASE + RP2040_SIO_INTERP1_ACCUM1_ADD_OFFSET)
|
||||
#define RP2040_SIO_INTERP1_BASE_1AND0 (RP2040_SIO_BASE + RP2040_SIO_INTERP1_BASE_1AND0_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK0 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK0_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK1 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK1_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK2 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK2_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK3 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK3_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK4 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK4_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK5 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK5_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK6 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK6_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK7 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK7_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK8 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK8_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK9 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK9_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK10 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK10_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK11 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK11_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK12 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK12_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK13 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK13_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK14 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK14_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK15 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK15_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK16 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK16_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK17 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK17_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK18 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK18_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK19 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK19_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK20 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK20_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK21 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK21_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK22 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK22_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK23 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK23_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK24 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK24_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK25 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK25_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK26 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK26_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK27 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK27_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK28 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK28_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK29 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK29_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK30 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK30_OFFSET)
|
||||
#define RP2040_SIO_SPINLOCK31 (RP2040_SIO_BASE + RP2040_SIO_SPINLOCK31_OFFSET)
|
||||
|
||||
/* Register bit definitions *************************************************/
|
||||
|
||||
#define RP2040_SIO_GPIO_IN_MASK (0x3fffffff) /* Input value for GPIO0...29 */
|
||||
|
||||
#define RP2040_SIO_GPIO_HI_IN_MASK (0x3f) /* Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3 */
|
||||
|
||||
#define RP2040_SIO_GPIO_OUT_MASK (0x3fffffff) /* Set output level (1/0 -> high/low) for GPIO0...29. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. */
|
||||
|
||||
#define RP2040_SIO_GPIO_OUT_SET_MASK (0x3fffffff) /* Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` */
|
||||
|
||||
#define RP2040_SIO_GPIO_OUT_CLR_MASK (0x3fffffff) /* Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` */
|
||||
|
||||
#define RP2040_SIO_GPIO_OUT_XOR_MASK (0x3fffffff) /* Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` */
|
||||
|
||||
#define RP2040_SIO_GPIO_OE_MASK (0x3fffffff) /* Set output enable (1/0 -> output/input) for GPIO0...29. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. */
|
||||
|
||||
#define RP2040_SIO_GPIO_OE_SET_MASK (0x3fffffff) /* Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` */
|
||||
|
||||
#define RP2040_SIO_GPIO_OE_CLR_MASK (0x3fffffff) /* Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` */
|
||||
|
||||
#define RP2040_SIO_GPIO_OE_XOR_MASK (0x3fffffff) /* Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` */
|
||||
|
||||
#define RP2040_SIO_GPIO_HI_OUT_MASK (0x3f) /* Set output level (1/0 -> high/low) for QSPI IO0...5. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. */
|
||||
|
||||
#define RP2040_SIO_GPIO_HI_OUT_SET_MASK (0x3f) /* Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` */
|
||||
|
||||
#define RP2040_SIO_GPIO_HI_OUT_CLR_MASK (0x3f) /* Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` */
|
||||
|
||||
#define RP2040_SIO_GPIO_HI_OUT_XOR_MASK (0x3f) /* Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` */
|
||||
|
||||
#define RP2040_SIO_GPIO_HI_OE_MASK (0x3f) /* Set output enable (1/0 -> output/input) for QSPI IO0...5. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. */
|
||||
|
||||
#define RP2040_SIO_GPIO_HI_OE_SET_MASK (0x3f) /* Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` */
|
||||
|
||||
#define RP2040_SIO_GPIO_HI_OE_CLR_MASK (0x3f) /* Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` */
|
||||
|
||||
#define RP2040_SIO_GPIO_HI_OE_XOR_MASK (0x3f) /* Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` */
|
||||
|
||||
#define RP2040_SIO_FIFO_ST_ROE (1 << 3) /* Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. */
|
||||
#define RP2040_SIO_FIFO_ST_WOF (1 << 2) /* Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. */
|
||||
#define RP2040_SIO_FIFO_ST_RDY (1 << 1) /* Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) */
|
||||
#define RP2040_SIO_FIFO_ST_VLD (1 << 0) /* Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) */
|
||||
|
||||
#define RP2040_SIO_DIV_CSR_DIRTY (1 << 1) /* Changes to 1 when any register is written, and back to 0 when QUOTIENT is read. Software can use this flag to make save/restore more efficient (skip if not DIRTY). If the flag is used in this way, it's recommended to either read QUOTIENT only, or REMAINDER and then QUOTIENT, to prevent data loss on context switch. */
|
||||
#define RP2040_SIO_DIV_CSR_READY (1 << 0) /* Reads as 0 when a calculation is in progress, 1 otherwise. Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no matter if one is already in progress. Writing to a result register will immediately terminate any in-progress calculation and set the READY and DIRTY flags. */
|
||||
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_OVERF (1 << 25) /* Set if either OVERF0 or OVERF1 is set. */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_OVERF1 (1 << 24) /* Indicates if any masked-off MSBs in ACCUM1 are set. */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_OVERF0 (1 << 23) /* Indicates if any masked-off MSBs in ACCUM0 are set. */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_BLEND (1 << 21) /* Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_FORCE_MSB_SHIFT (19) /* ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM. */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MASK (0x03 << RP2040_SIO_INTERP0_CTRL_LANE0_FORCE_MSB_SHIFT)
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_ADD_RAW (1 << 18) /* If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_CROSS_RESULT (1 << 17) /* If 1, feed the opposite lane's result into this lane's accumulator on POP. */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_CROSS_INPUT (1 << 16) /* If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_SIGNED (1 << 15) /* If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_MASK_MSB_SHIFT (10) /* The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_MASK_MSB_MASK (0x1f << RP2040_SIO_INTERP0_CTRL_LANE0_MASK_MSB_SHIFT)
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_MASK_LSB_SHIFT (5) /* The least-significant bit allowed to pass by the mask (inclusive) */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_MASK_LSB_MASK (0x1f << RP2040_SIO_INTERP0_CTRL_LANE0_MASK_LSB_SHIFT)
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE0_SHIFT_MASK (0x1f) /* Logical right-shift applied to accumulator before masking */
|
||||
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE1_FORCE_MSB_SHIFT (19) /* ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM. */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MASK (0x03 << RP2040_SIO_INTERP0_CTRL_LANE1_FORCE_MSB_SHIFT)
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE1_ADD_RAW (1 << 18) /* If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE1_CROSS_RESULT (1 << 17) /* If 1, feed the opposite lane's result into this lane's accumulator on POP. */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE1_CROSS_INPUT (1 << 16) /* If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE1_SIGNED (1 << 15) /* If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE1_MASK_MSB_SHIFT (10) /* The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE1_MASK_MSB_MASK (0x1f << RP2040_SIO_INTERP0_CTRL_LANE1_MASK_MSB_SHIFT)
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE1_MASK_LSB_SHIFT (5) /* The least-significant bit allowed to pass by the mask (inclusive) */
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE1_MASK_LSB_MASK (0x1f << RP2040_SIO_INTERP0_CTRL_LANE1_MASK_LSB_SHIFT)
|
||||
#define RP2040_SIO_INTERP0_CTRL_LANE1_SHIFT_MASK (0x1f) /* Logical right-shift applied to accumulator before masking */
|
||||
|
||||
#define RP2040_SIO_INTERP0_ACCUM0_ADD_MASK (0xffffff)
|
||||
|
||||
#define RP2040_SIO_INTERP0_ACCUM1_ADD_MASK (0xffffff)
|
||||
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_OVERF (1 << 25) /* Set if either OVERF0 or OVERF1 is set. */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_OVERF1 (1 << 24) /* Indicates if any masked-off MSBs in ACCUM1 are set. */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_OVERF0 (1 << 23) /* Indicates if any masked-off MSBs in ACCUM0 are set. */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_CLAMP (1 << 22) /* Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_FORCE_MSB_SHIFT (19) /* ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM. */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MASK (0x03 << RP2040_SIO_INTERP1_CTRL_LANE0_FORCE_MSB_SHIFT)
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_ADD_RAW (1 << 18) /* If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_CROSS_RESULT (1 << 17) /* If 1, feed the opposite lane's result into this lane's accumulator on POP. */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_CROSS_INPUT (1 << 16) /* If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_SIGNED (1 << 15) /* If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_MASK_MSB_SHIFT (10) /* The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_MASK_MSB_MASK (0x1f << RP2040_SIO_INTERP1_CTRL_LANE0_MASK_MSB_SHIFT)
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_MASK_LSB_SHIFT (5) /* The least-significant bit allowed to pass by the mask (inclusive) */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_MASK_LSB_MASK (0x1f << RP2040_SIO_INTERP1_CTRL_LANE0_MASK_LSB_SHIFT)
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE0_SHIFT_MASK (0x1f) /* Logical right-shift applied to accumulator before masking */
|
||||
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE1_FORCE_MSB_SHIFT (19) /* ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM. */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MASK (0x03 << RP2040_SIO_INTERP1_CTRL_LANE1_FORCE_MSB_SHIFT)
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE1_ADD_RAW (1 << 18) /* If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE1_CROSS_RESULT (1 << 17) /* If 1, feed the opposite lane's result into this lane's accumulator on POP. */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE1_CROSS_INPUT (1 << 16) /* If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE1_SIGNED (1 << 15) /* If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE1_MASK_MSB_SHIFT (10) /* The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE1_MASK_MSB_MASK (0x1f << RP2040_SIO_INTERP1_CTRL_LANE1_MASK_MSB_SHIFT)
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE1_MASK_LSB_SHIFT (5) /* The least-significant bit allowed to pass by the mask (inclusive) */
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE1_MASK_LSB_MASK (0x1f << RP2040_SIO_INTERP1_CTRL_LANE1_MASK_LSB_SHIFT)
|
||||
#define RP2040_SIO_INTERP1_CTRL_LANE1_SHIFT_MASK (0x1f) /* Logical right-shift applied to accumulator before masking */
|
||||
|
||||
#define RP2040_SIO_INTERP1_ACCUM0_ADD_MASK (0xffffff)
|
||||
|
||||
#define RP2040_SIO_INTERP1_ACCUM1_ADD_MASK (0xffffff)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_SIO_H */
|
||||
257
arch/arm/src/rp2040/hardware/rp2040_uart01.h
Normal file
257
arch/arm/src/rp2040/hardware/rp2040_uart01.h
Normal file
@ -0,0 +1,257 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/hardware/rp2040_uart01.h
|
||||
*
|
||||
* Generated from rp2040.svd originally provided by
|
||||
* Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_UART01_H
|
||||
#define __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_UART01_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hardware/rp2040_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define RP2040_UART_UARTDR_OFFSET 0x000000 /* Data Register, UARTDR */
|
||||
#define RP2040_UART_UARTRSR_OFFSET 0x000004 /* Receive Status Register/Error Clear Register, UARTRSR/UARTECR */
|
||||
#define RP2040_UART_UARTFR_OFFSET 0x000018 /* Flag Register, UARTFR */
|
||||
#define RP2040_UART_UARTILPR_OFFSET 0x000020 /* IrDA Low-Power Counter Register, UARTILPR */
|
||||
#define RP2040_UART_UARTIBRD_OFFSET 0x000024 /* Integer Baud Rate Register, UARTIBRD */
|
||||
#define RP2040_UART_UARTFBRD_OFFSET 0x000028 /* Fractional Baud Rate Register, UARTFBRD */
|
||||
#define RP2040_UART_UARTLCR_H_OFFSET 0x00002c /* Line Control Register, UARTLCR_H */
|
||||
#define RP2040_UART_UARTCR_OFFSET 0x000030 /* Control Register, UARTCR */
|
||||
#define RP2040_UART_UARTIFLS_OFFSET 0x000034 /* Interrupt FIFO Level Select Register, UARTIFLS */
|
||||
#define RP2040_UART_UARTIMSC_OFFSET 0x000038 /* Interrupt Mask Set/Clear Register, UARTIMSC */
|
||||
#define RP2040_UART_UARTRIS_OFFSET 0x00003c /* Raw Interrupt Status Register, UARTRIS */
|
||||
#define RP2040_UART_UARTMIS_OFFSET 0x000040 /* Masked Interrupt Status Register, UARTMIS */
|
||||
#define RP2040_UART_UARTICR_OFFSET 0x000044 /* Interrupt Clear Register, UARTICR */
|
||||
#define RP2040_UART_UARTDMACR_OFFSET 0x000048 /* DMA Control Register, UARTDMACR */
|
||||
#define RP2040_UART_UARTPERIPHID0_OFFSET 0x000fe0 /* UARTPeriphID0 Register */
|
||||
#define RP2040_UART_UARTPERIPHID1_OFFSET 0x000fe4 /* UARTPeriphID1 Register */
|
||||
#define RP2040_UART_UARTPERIPHID2_OFFSET 0x000fe8 /* UARTPeriphID2 Register */
|
||||
#define RP2040_UART_UARTPERIPHID3_OFFSET 0x000fec /* UARTPeriphID3 Register */
|
||||
#define RP2040_UART_UARTPCELLID0_OFFSET 0x000ff0 /* UARTPCellID0 Register */
|
||||
#define RP2040_UART_UARTPCELLID1_OFFSET 0x000ff4 /* UARTPCellID1 Register */
|
||||
#define RP2040_UART_UARTPCELLID2_OFFSET 0x000ff8 /* UARTPCellID2 Register */
|
||||
#define RP2040_UART_UARTPCELLID3_OFFSET 0x000ffc /* UARTPCellID3 Register */
|
||||
|
||||
/* Register definitions (UART) **********************************************/
|
||||
|
||||
#define RP2040_UART0_UARTDR (RP2040_UART_BASE + RP2040_UART_UARTDR_OFFSET)
|
||||
#define RP2040_UART0_UARTRSR (RP2040_UART_BASE + RP2040_UART_UARTRSR_OFFSET)
|
||||
#define RP2040_UART0_UARTFR (RP2040_UART_BASE + RP2040_UART_UARTFR_OFFSET)
|
||||
#define RP2040_UART0_UARTILPR (RP2040_UART_BASE + RP2040_UART_UARTILPR_OFFSET)
|
||||
#define RP2040_UART0_UARTIBRD (RP2040_UART_BASE + RP2040_UART_UARTIBRD_OFFSET)
|
||||
#define RP2040_UART0_UARTFBRD (RP2040_UART_BASE + RP2040_UART_UARTFBRD_OFFSET)
|
||||
#define RP2040_UART0_UARTLCR_H (RP2040_UART_BASE + RP2040_UART_UARTLCR_H_OFFSET)
|
||||
#define RP2040_UART0_UARTCR (RP2040_UART_BASE + RP2040_UART_UARTCR_OFFSET)
|
||||
#define RP2040_UART0_UARTIFLS (RP2040_UART_BASE + RP2040_UART_UARTIFLS_OFFSET)
|
||||
#define RP2040_UART0_UARTIMSC (RP2040_UART_BASE + RP2040_UART_UARTIMSC_OFFSET)
|
||||
#define RP2040_UART0_UARTRIS (RP2040_UART_BASE + RP2040_UART_UARTRIS_OFFSET)
|
||||
#define RP2040_UART0_UARTMIS (RP2040_UART_BASE + RP2040_UART_UARTMIS_OFFSET)
|
||||
#define RP2040_UART0_UARTICR (RP2040_UART_BASE + RP2040_UART_UARTICR_OFFSET)
|
||||
#define RP2040_UART0_UARTDMACR (RP2040_UART_BASE + RP2040_UART_UARTDMACR_OFFSET)
|
||||
#define RP2040_UART0_UARTPERIPHID0 (RP2040_UART_BASE + RP2040_UART_UARTPERIPHID0_OFFSET)
|
||||
#define RP2040_UART0_UARTPERIPHID1 (RP2040_UART_BASE + RP2040_UART_UARTPERIPHID1_OFFSET)
|
||||
#define RP2040_UART0_UARTPERIPHID2 (RP2040_UART_BASE + RP2040_UART_UARTPERIPHID2_OFFSET)
|
||||
#define RP2040_UART0_UARTPERIPHID3 (RP2040_UART_BASE + RP2040_UART_UARTPERIPHID3_OFFSET)
|
||||
#define RP2040_UART0_UARTPCELLID0 (RP2040_UART_BASE + RP2040_UART_UARTPCELLID0_OFFSET)
|
||||
#define RP2040_UART0_UARTPCELLID1 (RP2040_UART_BASE + RP2040_UART_UARTPCELLID1_OFFSET)
|
||||
#define RP2040_UART0_UARTPCELLID2 (RP2040_UART_BASE + RP2040_UART_UARTPCELLID2_OFFSET)
|
||||
#define RP2040_UART0_UARTPCELLID3 (RP2040_UART_BASE + RP2040_UART_UARTPCELLID3_OFFSET)
|
||||
|
||||
/* Register definitions (UART1) *********************************************/
|
||||
|
||||
#define RP2040_UART1_UARTDR (RP2040_UART1_BASE + RP2040_UART_UARTDR_OFFSET)
|
||||
#define RP2040_UART1_UARTRSR (RP2040_UART1_BASE + RP2040_UART_UARTRSR_OFFSET)
|
||||
#define RP2040_UART1_UARTFR (RP2040_UART1_BASE + RP2040_UART_UARTFR_OFFSET)
|
||||
#define RP2040_UART1_UARTILPR (RP2040_UART1_BASE + RP2040_UART_UARTILPR_OFFSET)
|
||||
#define RP2040_UART1_UARTIBRD (RP2040_UART1_BASE + RP2040_UART_UARTIBRD_OFFSET)
|
||||
#define RP2040_UART1_UARTFBRD (RP2040_UART1_BASE + RP2040_UART_UARTFBRD_OFFSET)
|
||||
#define RP2040_UART1_UARTLCR_H (RP2040_UART1_BASE + RP2040_UART_UARTLCR_H_OFFSET)
|
||||
#define RP2040_UART1_UARTCR (RP2040_UART1_BASE + RP2040_UART_UARTCR_OFFSET)
|
||||
#define RP2040_UART1_UARTIFLS (RP2040_UART1_BASE + RP2040_UART_UARTIFLS_OFFSET)
|
||||
#define RP2040_UART1_UARTIMSC (RP2040_UART1_BASE + RP2040_UART_UARTIMSC_OFFSET)
|
||||
#define RP2040_UART1_UARTRIS (RP2040_UART1_BASE + RP2040_UART_UARTRIS_OFFSET)
|
||||
#define RP2040_UART1_UARTMIS (RP2040_UART1_BASE + RP2040_UART_UARTMIS_OFFSET)
|
||||
#define RP2040_UART1_UARTICR (RP2040_UART1_BASE + RP2040_UART_UARTICR_OFFSET)
|
||||
#define RP2040_UART1_UARTDMACR (RP2040_UART1_BASE + RP2040_UART_UARTDMACR_OFFSET)
|
||||
#define RP2040_UART1_UARTPERIPHID0 (RP2040_UART1_BASE + RP2040_UART_UARTPERIPHID0_OFFSET)
|
||||
#define RP2040_UART1_UARTPERIPHID1 (RP2040_UART1_BASE + RP2040_UART_UARTPERIPHID1_OFFSET)
|
||||
#define RP2040_UART1_UARTPERIPHID2 (RP2040_UART1_BASE + RP2040_UART_UARTPERIPHID2_OFFSET)
|
||||
#define RP2040_UART1_UARTPERIPHID3 (RP2040_UART1_BASE + RP2040_UART_UARTPERIPHID3_OFFSET)
|
||||
#define RP2040_UART1_UARTPCELLID0 (RP2040_UART1_BASE + RP2040_UART_UARTPCELLID0_OFFSET)
|
||||
#define RP2040_UART1_UARTPCELLID1 (RP2040_UART1_BASE + RP2040_UART_UARTPCELLID1_OFFSET)
|
||||
#define RP2040_UART1_UARTPCELLID2 (RP2040_UART1_BASE + RP2040_UART_UARTPCELLID2_OFFSET)
|
||||
#define RP2040_UART1_UARTPCELLID3 (RP2040_UART1_BASE + RP2040_UART_UARTPCELLID3_OFFSET)
|
||||
|
||||
/* Register bit definitions *************************************************/
|
||||
|
||||
#define RP2040_UART_UARTDR_OE (1 << 11) /* Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. */
|
||||
#define RP2040_UART_UARTDR_BE (1 << 10) /* Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. */
|
||||
#define RP2040_UART_UARTDR_PE (1 << 9) /* Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. */
|
||||
#define RP2040_UART_UARTDR_FE (1 << 8) /* Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. */
|
||||
#define RP2040_UART_UARTDR_DATA_MASK (0xff) /* Receive (read) data character. Transmit (write) data character. */
|
||||
|
||||
#define RP2040_UART_UARTRSR_OE (1 << 3) /* Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. */
|
||||
#define RP2040_UART_UARTRSR_BE (1 << 2) /* Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. */
|
||||
#define RP2040_UART_UARTRSR_PE (1 << 1) /* Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. */
|
||||
#define RP2040_UART_UARTRSR_FE (1 << 0) /* Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. */
|
||||
|
||||
#define RP2040_UART_UARTFR_RI (1 << 8) /* Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. */
|
||||
#define RP2040_UART_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. */
|
||||
#define RP2040_UART_UARTFR_RXFF (1 << 6) /* Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. */
|
||||
#define RP2040_UART_UARTFR_TXFF (1 << 5) /* Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. */
|
||||
#define RP2040_UART_UARTFR_RXFE (1 << 4) /* Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. */
|
||||
#define RP2040_UART_UARTFR_BUSY (1 << 3) /* UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. */
|
||||
#define RP2040_UART_UARTFR_DCD (1 << 2) /* Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. */
|
||||
#define RP2040_UART_UARTFR_DSR (1 << 1) /* Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. */
|
||||
#define RP2040_UART_UARTFR_CTS (1 << 0) /* Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. */
|
||||
|
||||
#define RP2040_UART_UARTILPR_ILPDVSR_MASK (0xff) /* 8-bit low-power divisor value. These bits are cleared to 0 at reset. */
|
||||
|
||||
#define RP2040_UART_UARTIBRD_BAUD_DIVINT_MASK (0xffff) /* The integer baud rate divisor. These bits are cleared to 0 on reset. */
|
||||
|
||||
#define RP2040_UART_UARTFBRD_BAUD_DIVFRAC_MASK (0x3f) /* The fractional baud rate divisor. These bits are cleared to 0 on reset. */
|
||||
|
||||
#define RP2040_UART_UARTLCR_H_SPS (1 << 7) /* Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. */
|
||||
#define RP2040_UART_UARTLCR_H_WLEN_SHIFT (5) /* Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. */
|
||||
#define RP2040_UART_UARTLCR_H_WLEN_MASK (0x03 << RP2040_UART_UARTLCR_H_WLEN_SHIFT)
|
||||
#define RP2040_UART_UARTLCR_H_FEN (1 << 4) /* Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). */
|
||||
#define RP2040_UART_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. */
|
||||
#define RP2040_UART_UARTLCR_H_EPS (1 << 2) /* Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. */
|
||||
#define RP2040_UART_UARTLCR_H_PEN (1 << 1) /* Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. */
|
||||
#define RP2040_UART_UARTLCR_H_BRK (1 << 0) /* Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. */
|
||||
|
||||
#define RP2040_UART_LCR_H_WLEN(x) ((((x) - 5) << RP2040_UART_UARTLCR_H_WLEN_SHIFT) & RP2040_UART_UARTLCR_H_WLEN_MASK)
|
||||
|
||||
#define RP2040_UART_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. */
|
||||
#define RP2040_UART_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. */
|
||||
#define RP2040_UART_UARTCR_OUT2 (1 << 13) /* This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). */
|
||||
#define RP2040_UART_UARTCR_OUT1 (1 << 12) /* This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). */
|
||||
#define RP2040_UART_UARTCR_RTS (1 << 11) /* Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. */
|
||||
#define RP2040_UART_UARTCR_DTR (1 << 10) /* Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. */
|
||||
#define RP2040_UART_UARTCR_RXE (1 << 9) /* Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. */
|
||||
#define RP2040_UART_UARTCR_TXE (1 << 8) /* Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. */
|
||||
#define RP2040_UART_UARTCR_LBE (1 << 7) /* Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. */
|
||||
#define RP2040_UART_UARTCR_SIRLP (1 << 2) /* SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. */
|
||||
#define RP2040_UART_UARTCR_SIREN (1 << 1) /* SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. */
|
||||
#define RP2040_UART_UARTCR_UARTEN (1 << 0) /* UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. */
|
||||
|
||||
#define RP2040_UART_UARTIFLS_RXIFLSEL_SHIFT (3) /* Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. */
|
||||
#define RP2040_UART_UARTIFLS_RXIFLSEL_MASK (0x07 << RP2040_UART_UARTIFLS_RXIFLSEL_SHIFT)
|
||||
#define RP2040_UART_UARTIFLS_TXIFLSEL_MASK (0x07) /* Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. */
|
||||
|
||||
#define RP2040_UART_INTR_ALL (0x7ff) /* All of interrupts */
|
||||
|
||||
#define RP2040_UART_UARTIMSC_OEIM (1 << 10) /* Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. */
|
||||
#define RP2040_UART_UARTIMSC_BEIM (1 << 9) /* Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. */
|
||||
#define RP2040_UART_UARTIMSC_PEIM (1 << 8) /* Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. */
|
||||
#define RP2040_UART_UARTIMSC_FEIM (1 << 7) /* Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. */
|
||||
#define RP2040_UART_UARTIMSC_RTIM (1 << 6) /* Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. */
|
||||
#define RP2040_UART_UARTIMSC_TXIM (1 << 5) /* Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. */
|
||||
#define RP2040_UART_UARTIMSC_RXIM (1 << 4) /* Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. */
|
||||
#define RP2040_UART_UARTIMSC_DSRMIM (1 << 3) /* nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. */
|
||||
#define RP2040_UART_UARTIMSC_DCDMIM (1 << 2) /* nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. */
|
||||
#define RP2040_UART_UARTIMSC_CTSMIM (1 << 1) /* nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. */
|
||||
#define RP2040_UART_UARTIMSC_RIMIM (1 << 0) /* nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. */
|
||||
|
||||
#define RP2040_UART_UARTRIS_OERIS (1 << 10) /* Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. */
|
||||
#define RP2040_UART_UARTRIS_BERIS (1 << 9) /* Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. */
|
||||
#define RP2040_UART_UARTRIS_PERIS (1 << 8) /* Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. */
|
||||
#define RP2040_UART_UARTRIS_FERIS (1 << 7) /* Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. */
|
||||
#define RP2040_UART_UARTRIS_RTRIS (1 << 6) /* Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a */
|
||||
#define RP2040_UART_UARTRIS_TXRIS (1 << 5) /* Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. */
|
||||
#define RP2040_UART_UARTRIS_RXRIS (1 << 4) /* Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. */
|
||||
#define RP2040_UART_UARTRIS_DSRRMIS (1 << 3) /* nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. */
|
||||
#define RP2040_UART_UARTRIS_DCDRMIS (1 << 2) /* nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. */
|
||||
#define RP2040_UART_UARTRIS_CTSRMIS (1 << 1) /* nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. */
|
||||
#define RP2040_UART_UARTRIS_RIRMIS (1 << 0) /* nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. */
|
||||
|
||||
#define RP2040_UART_UARTMIS_OEMIS (1 << 10) /* Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. */
|
||||
#define RP2040_UART_UARTMIS_BEMIS (1 << 9) /* Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. */
|
||||
#define RP2040_UART_UARTMIS_PEMIS (1 << 8) /* Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. */
|
||||
#define RP2040_UART_UARTMIS_FEMIS (1 << 7) /* Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. */
|
||||
#define RP2040_UART_UARTMIS_RTMIS (1 << 6) /* Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. */
|
||||
#define RP2040_UART_UARTMIS_TXMIS (1 << 5) /* Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. */
|
||||
#define RP2040_UART_UARTMIS_RXMIS (1 << 4) /* Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. */
|
||||
#define RP2040_UART_UARTMIS_DSRMMIS (1 << 3) /* nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. */
|
||||
#define RP2040_UART_UARTMIS_DCDMMIS (1 << 2) /* nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. */
|
||||
#define RP2040_UART_UARTMIS_CTSMMIS (1 << 1) /* nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. */
|
||||
#define RP2040_UART_UARTMIS_RIMMIS (1 << 0) /* nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. */
|
||||
|
||||
#define RP2040_UART_UARTICR_OEIC (1 << 10) /* Overrun error interrupt clear. Clears the UARTOEINTR interrupt. */
|
||||
#define RP2040_UART_UARTICR_BEIC (1 << 9) /* Break error interrupt clear. Clears the UARTBEINTR interrupt. */
|
||||
#define RP2040_UART_UARTICR_PEIC (1 << 8) /* Parity error interrupt clear. Clears the UARTPEINTR interrupt. */
|
||||
#define RP2040_UART_UARTICR_FEIC (1 << 7) /* Framing error interrupt clear. Clears the UARTFEINTR interrupt. */
|
||||
#define RP2040_UART_UARTICR_RTIC (1 << 6) /* Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. */
|
||||
#define RP2040_UART_UARTICR_TXIC (1 << 5) /* Transmit interrupt clear. Clears the UARTTXINTR interrupt. */
|
||||
#define RP2040_UART_UARTICR_RXIC (1 << 4) /* Receive interrupt clear. Clears the UARTRXINTR interrupt. */
|
||||
#define RP2040_UART_UARTICR_DSRMIC (1 << 3) /* nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. */
|
||||
#define RP2040_UART_UARTICR_DCDMIC (1 << 2) /* nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. */
|
||||
#define RP2040_UART_UARTICR_CTSMIC (1 << 1) /* nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. */
|
||||
#define RP2040_UART_UARTICR_RIMIC (1 << 0) /* nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. */
|
||||
|
||||
#define RP2040_UART_UARTDMACR_DMAONERR (1 << 2) /* DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. */
|
||||
#define RP2040_UART_UARTDMACR_TXDMAE (1 << 1) /* Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. */
|
||||
#define RP2040_UART_UARTDMACR_RXDMAE (1 << 0) /* Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. */
|
||||
|
||||
#define RP2040_UART_UARTPERIPHID0_PARTNUMBER0_MASK (0xff) /* These bits read back as 0x11 */
|
||||
|
||||
#define RP2040_UART_UARTPERIPHID1_DESIGNER0_SHIFT (4) /* These bits read back as 0x1 */
|
||||
#define RP2040_UART_UARTPERIPHID1_DESIGNER0_MASK (0x0f << RP2040_UART_UARTPERIPHID1_DESIGNER0_SHIFT)
|
||||
#define RP2040_UART_UARTPERIPHID1_PARTNUMBER1_MASK (0x0f) /* These bits read back as 0x0 */
|
||||
|
||||
#define RP2040_UART_UARTPERIPHID2_REVISION_SHIFT (4) /* This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 */
|
||||
#define RP2040_UART_UARTPERIPHID2_REVISION_MASK (0x0f << RP2040_UART_UARTPERIPHID2_REVISION_SHIFT)
|
||||
#define RP2040_UART_UARTPERIPHID2_DESIGNER1_MASK (0x0f) /* These bits read back as 0x4 */
|
||||
|
||||
#define RP2040_UART_UARTPERIPHID3_CONFIGURATION_MASK (0xff) /* These bits read back as 0x00 */
|
||||
|
||||
#define RP2040_UART_UARTPCELLID0_MASK (0xff) /* These bits read back as 0x0D */
|
||||
|
||||
#define RP2040_UART_UARTPCELLID1_MASK (0xff) /* These bits read back as 0xF0 */
|
||||
|
||||
#define RP2040_UART_UARTPCELLID2_MASK (0xff) /* These bits read back as 0x05 */
|
||||
|
||||
#define RP2040_UART_UARTPCELLID3_MASK (0xff) /* These bits read back as 0xB1 */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_UART01_H */
|
||||
101
arch/arm/src/rp2040/hardware/rp2040_watchdog.h
Normal file
101
arch/arm/src/rp2040/hardware/rp2040_watchdog.h
Normal file
@ -0,0 +1,101 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/hardware/rp2040_watchdog.h
|
||||
*
|
||||
* Generated from rp2040.svd originally provided by
|
||||
* Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_WATCHDOG_H
|
||||
#define __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_WATCHDOG_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hardware/rp2040_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define RP2040_WATCHDOG_CTRL_OFFSET 0x000000 /* Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software. */
|
||||
#define RP2040_WATCHDOG_LOAD_OFFSET 0x000004 /* Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). */
|
||||
#define RP2040_WATCHDOG_REASON_OFFSET 0x000008 /* Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. */
|
||||
#define RP2040_WATCHDOG_SCRATCH0_OFFSET 0x00000c /* Scratch register. Information persists through soft reset of the chip. */
|
||||
#define RP2040_WATCHDOG_SCRATCH1_OFFSET 0x000010 /* Scratch register. Information persists through soft reset of the chip. */
|
||||
#define RP2040_WATCHDOG_SCRATCH2_OFFSET 0x000014 /* Scratch register. Information persists through soft reset of the chip. */
|
||||
#define RP2040_WATCHDOG_SCRATCH3_OFFSET 0x000018 /* Scratch register. Information persists through soft reset of the chip. */
|
||||
#define RP2040_WATCHDOG_SCRATCH4_OFFSET 0x00001c /* Scratch register. Information persists through soft reset of the chip. */
|
||||
#define RP2040_WATCHDOG_SCRATCH5_OFFSET 0x000020 /* Scratch register. Information persists through soft reset of the chip. */
|
||||
#define RP2040_WATCHDOG_SCRATCH6_OFFSET 0x000024 /* Scratch register. Information persists through soft reset of the chip. */
|
||||
#define RP2040_WATCHDOG_SCRATCH7_OFFSET 0x000028 /* Scratch register. Information persists through soft reset of the chip. */
|
||||
#define RP2040_WATCHDOG_TICK_OFFSET 0x00002c /* Controls the tick generator */
|
||||
|
||||
/* Register definitions *****************************************************/
|
||||
|
||||
#define RP2040_WATCHDOG_CTRL (RP2040_WATCHDOG_BASE + RP2040_WATCHDOG_CTRL_OFFSET)
|
||||
#define RP2040_WATCHDOG_LOAD (RP2040_WATCHDOG_BASE + RP2040_WATCHDOG_LOAD_OFFSET)
|
||||
#define RP2040_WATCHDOG_REASON (RP2040_WATCHDOG_BASE + RP2040_WATCHDOG_REASON_OFFSET)
|
||||
#define RP2040_WATCHDOG_SCRATCH0 (RP2040_WATCHDOG_BASE + RP2040_WATCHDOG_SCRATCH0_OFFSET)
|
||||
#define RP2040_WATCHDOG_SCRATCH1 (RP2040_WATCHDOG_BASE + RP2040_WATCHDOG_SCRATCH1_OFFSET)
|
||||
#define RP2040_WATCHDOG_SCRATCH2 (RP2040_WATCHDOG_BASE + RP2040_WATCHDOG_SCRATCH2_OFFSET)
|
||||
#define RP2040_WATCHDOG_SCRATCH3 (RP2040_WATCHDOG_BASE + RP2040_WATCHDOG_SCRATCH3_OFFSET)
|
||||
#define RP2040_WATCHDOG_SCRATCH4 (RP2040_WATCHDOG_BASE + RP2040_WATCHDOG_SCRATCH4_OFFSET)
|
||||
#define RP2040_WATCHDOG_SCRATCH5 (RP2040_WATCHDOG_BASE + RP2040_WATCHDOG_SCRATCH5_OFFSET)
|
||||
#define RP2040_WATCHDOG_SCRATCH6 (RP2040_WATCHDOG_BASE + RP2040_WATCHDOG_SCRATCH6_OFFSET)
|
||||
#define RP2040_WATCHDOG_SCRATCH7 (RP2040_WATCHDOG_BASE + RP2040_WATCHDOG_SCRATCH7_OFFSET)
|
||||
#define RP2040_WATCHDOG_TICK (RP2040_WATCHDOG_BASE + RP2040_WATCHDOG_TICK_OFFSET)
|
||||
|
||||
/* Register bit definitions *************************************************/
|
||||
|
||||
#define RP2040_WATCHDOG_CTRL_TRIGGER (1 << 31) /* Trigger a watchdog reset */
|
||||
#define RP2040_WATCHDOG_CTRL_ENABLE (1 << 30) /* When not enabled the watchdog timer is paused */
|
||||
#define RP2040_WATCHDOG_CTRL_PAUSE_DBG1 (1 << 26) /* Pause the watchdog timer when processor 1 is in debug mode */
|
||||
#define RP2040_WATCHDOG_CTRL_PAUSE_DBG0 (1 << 25) /* Pause the watchdog timer when processor 0 is in debug mode */
|
||||
#define RP2040_WATCHDOG_CTRL_PAUSE_JTAG (1 << 24) /* Pause the watchdog timer when JTAG is accessing the bus fabric */
|
||||
#define RP2040_WATCHDOG_CTRL_TIME_MASK (0xffffff) /* Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered */
|
||||
|
||||
#define RP2040_WATCHDOG_LOAD_MASK (0xffffff)
|
||||
|
||||
#define RP2040_WATCHDOG_REASON_FORCE (1 << 1)
|
||||
#define RP2040_WATCHDOG_REASON_TIMER (1 << 0)
|
||||
|
||||
#define RP2040_WATCHDOG_TICK_COUNT_SHIFT (11) /* Count down timer: the remaining number clk_tick cycles before the next tick is generated. */
|
||||
#define RP2040_WATCHDOG_TICK_COUNT_MASK (0x1ff << RP2040_WATCHDOG_TICK_COUNT_SHIFT)
|
||||
#define RP2040_WATCHDOG_TICK_RUNNING (1 << 10) /* Is the tick generator running? */
|
||||
#define RP2040_WATCHDOG_TICK_ENABLE (1 << 9) /* start / stop tick generation */
|
||||
#define RP2040_WATCHDOG_TICK_CYCLES_MASK (0x1ff) /* Total number of clk_tick cycles before the next tick. */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_WATCHDOG_H */
|
||||
93
arch/arm/src/rp2040/hardware/rp2040_xosc.h
Normal file
93
arch/arm/src/rp2040/hardware/rp2040_xosc.h
Normal file
@ -0,0 +1,93 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/hardware/rp2040_xosc.h
|
||||
*
|
||||
* Generated from rp2040.svd originally provided by
|
||||
* Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_XOSC_H
|
||||
#define __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_XOSC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "hardware/rp2040_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define RP2040_XOSC_CTRL_OFFSET 0x000000 /* Crystal Oscillator Control */
|
||||
#define RP2040_XOSC_STATUS_OFFSET 0x000004 /* Crystal Oscillator Status */
|
||||
#define RP2040_XOSC_DORMANT_OFFSET 0x000008 /* Crystal Oscillator pause control This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE WARNING: stop the PLLs before selecting dormant mode WARNING: setup the irq before selecting dormant mode */
|
||||
#define RP2040_XOSC_STARTUP_OFFSET 0x00000c /* Controls the startup delay */
|
||||
#define RP2040_XOSC_COUNT_OFFSET 0x00001c /* A down counter running at the xosc frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware. */
|
||||
|
||||
/* Register definitions *****************************************************/
|
||||
|
||||
#define RP2040_XOSC_CTRL (RP2040_XOSC_BASE + RP2040_XOSC_CTRL_OFFSET)
|
||||
#define RP2040_XOSC_STATUS (RP2040_XOSC_BASE + RP2040_XOSC_STATUS_OFFSET)
|
||||
#define RP2040_XOSC_DORMANT (RP2040_XOSC_BASE + RP2040_XOSC_DORMANT_OFFSET)
|
||||
#define RP2040_XOSC_STARTUP (RP2040_XOSC_BASE + RP2040_XOSC_STARTUP_OFFSET)
|
||||
#define RP2040_XOSC_COUNT (RP2040_XOSC_BASE + RP2040_XOSC_COUNT_OFFSET)
|
||||
|
||||
/* Register bit definitions *************************************************/
|
||||
|
||||
#define RP2040_XOSC_CTRL_ENABLE_SHIFT (12) /* On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. */
|
||||
#define RP2040_XOSC_CTRL_ENABLE_MASK (0xfff << RP2040_XOSC_CTRL_ENABLE_SHIFT)
|
||||
#define RP2040_XOSC_CTRL_ENABLE_DISABLE (0xd1e << RP2040_XOSC_CTRL_ENABLE_SHIFT)
|
||||
#define RP2040_XOSC_CTRL_ENABLE_ENABLE (0xfab << RP2040_XOSC_CTRL_ENABLE_SHIFT)
|
||||
#define RP2040_XOSC_CTRL_FREQ_RANGE_MASK (0xfff)
|
||||
#define RP2040_XOSC_CTRL_FREQ_RANGE_1_15MHZ (0xaa0)
|
||||
#define RP2040_XOSC_CTRL_FREQ_RANGE_RESERVED_1 (0xaa1)
|
||||
#define RP2040_XOSC_CTRL_FREQ_RANGE_RESERVED_2 (0xaa2)
|
||||
#define RP2040_XOSC_CTRL_FREQ_RANGE_RESERVED_3 (0xaa3)
|
||||
|
||||
#define RP2040_XOSC_STATUS_STABLE (1 << 31) /* Oscillator is running and stable */
|
||||
#define RP2040_XOSC_STATUS_BADWRITE (1 << 24) /* An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT */
|
||||
#define RP2040_XOSC_STATUS_ENABLED (1 << 12) /* Oscillator is enabled but not necessarily running and stable, resets to 0 */
|
||||
#define RP2040_XOSC_STATUS_FREQ_RANGE_MASK (0x03)
|
||||
#define RP2040_XOSC_STATUS_FREQ_RANGE_1_15MHZ (0x0)
|
||||
#define RP2040_XOSC_STATUS_FREQ_RANGE_RESERVED_1 (0x1)
|
||||
#define RP2040_XOSC_STATUS_FREQ_RANGE_RESERVED_2 (0x2)
|
||||
#define RP2040_XOSC_STATUS_FREQ_RANGE_RESERVED_3 (0x3)
|
||||
|
||||
#define RP2040_XOSC_STARTUP_X4 (1 << 20) /* Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly */
|
||||
#define RP2040_XOSC_STARTUP_DELAY_MASK (0x3fff) /* in multiples of 256*xtal_period */
|
||||
|
||||
#define RP2040_XOSC_COUNT_MASK (0xff)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_XOSC_H */
|
||||
350
arch/arm/src/rp2040/rp2040_clock.c
Normal file
350
arch/arm/src/rp2040/rp2040_clock.c
Normal file
@ -0,0 +1,350 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_clock.c
|
||||
*
|
||||
* Based upon the software originally developed by
|
||||
* Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "arm_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#include "rp2040_clock.h"
|
||||
#include "rp2040_xosc.h"
|
||||
#include "rp2040_pll.h"
|
||||
#include "hardware/rp2040_clocks.h"
|
||||
#include "hardware/rp2040_resets.h"
|
||||
#include "hardware/rp2040_watchdog.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define RESETS_RESET_BITS 0x01ffffff
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
static uint32_t rp2040_clock_freq[RP2040_CLOCKS_NDX_MAX];
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
static inline bool has_glitchless_mux(int clk_index)
|
||||
{
|
||||
return clk_index == RP2040_CLOCKS_NDX_SYS ||
|
||||
clk_index == RP2040_CLOCKS_NDX_REF;
|
||||
}
|
||||
|
||||
bool rp2040_clock_configure(int clk_index,
|
||||
uint32_t src, uint32_t auxsrc,
|
||||
uint32_t src_freq, uint32_t freq)
|
||||
{
|
||||
uint32_t div;
|
||||
|
||||
assert(src_freq >= freq);
|
||||
|
||||
if (freq > src_freq)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Div register is 24.8 int.frac divider so multiply by 2^8
|
||||
* (left shift by 8)
|
||||
*/
|
||||
|
||||
div = (uint32_t) (((uint64_t) src_freq << 8) / freq);
|
||||
|
||||
/* If increasing divisor, set divisor before source. Otherwise set source
|
||||
* before divisor. This avoids a momentary overspeed when e.g. switching
|
||||
* to a faster source and increasing divisor to compensate.
|
||||
*/
|
||||
|
||||
if (div > getreg32(RP2040_CLOCKS_CLK_NDX_DIV(clk_index)))
|
||||
{
|
||||
putreg32(div, RP2040_CLOCKS_CLK_NDX_DIV(clk_index));
|
||||
}
|
||||
|
||||
if (has_glitchless_mux(clk_index) &&
|
||||
src == RP2040_CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX)
|
||||
{
|
||||
/* If switching a glitchless slice (ref or sys) to an aux source,
|
||||
* switch away from aux *first* to avoid passing glitches when
|
||||
* changing aux mux.
|
||||
* Assume (!!!) glitchless source 0 is no faster than the aux source.
|
||||
*/
|
||||
|
||||
clrbits_reg32(RP2040_CLOCKS_CLK_REF_CTRL_SRC_MASK,
|
||||
RP2040_CLOCKS_CLK_NDX_CTRL(clk_index));
|
||||
while (!(getreg32(RP2040_CLOCKS_CLK_NDX_SELECTED(clk_index)) & 1u))
|
||||
;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If no glitchless mux, cleanly stop the clock to avoid glitches
|
||||
* propagating when changing aux mux. Note it would be a really bad
|
||||
* idea to do this on one of the glitchless clocks (clk_sys, clk_ref).
|
||||
*/
|
||||
|
||||
clrbits_reg32(RP2040_CLOCKS_CLK_GPOUT0_CTRL_ENABLE,
|
||||
RP2040_CLOCKS_CLK_NDX_CTRL(clk_index));
|
||||
|
||||
if (rp2040_clock_freq[clk_index] > 0)
|
||||
{
|
||||
/* Delay for 3 cycles of the target clock, for ENABLE propagation.
|
||||
* Note XOSC_COUNT is not helpful here because XOSC is not
|
||||
* necessarily running, nor is timer... so, 3 cycles per loop:
|
||||
*/
|
||||
|
||||
unsigned int delay_cyc = rp2040_clock_freq[RP2040_CLOCKS_NDX_SYS] /
|
||||
rp2040_clock_freq[clk_index] + 1;
|
||||
|
||||
__asm__ volatile (
|
||||
"1: \n\t"
|
||||
"sub %0, #1 \n\t"
|
||||
"bne 1b"
|
||||
: "+r" (delay_cyc)
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set aux mux first, and then glitchless mux if this clock has one */
|
||||
|
||||
modbits_reg32(auxsrc, RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_MASK,
|
||||
RP2040_CLOCKS_CLK_NDX_CTRL(clk_index));
|
||||
|
||||
if (has_glitchless_mux(clk_index))
|
||||
{
|
||||
modbits_reg32(src, RP2040_CLOCKS_CLK_REF_CTRL_SRC_MASK,
|
||||
RP2040_CLOCKS_CLK_NDX_CTRL(clk_index));
|
||||
while (!(getreg32(RP2040_CLOCKS_CLK_NDX_SELECTED(clk_index))
|
||||
& (1u << src)))
|
||||
;
|
||||
}
|
||||
|
||||
setbits_reg32(RP2040_CLOCKS_CLK_GPOUT0_CTRL_ENABLE,
|
||||
RP2040_CLOCKS_CLK_NDX_CTRL(clk_index));
|
||||
|
||||
/* Now that the source is configured, we can trust that the user-supplied
|
||||
* divisor is a safe value.
|
||||
*/
|
||||
|
||||
putreg32(div, RP2040_CLOCKS_CLK_NDX_DIV(clk_index));
|
||||
|
||||
/* Store the configured frequency */
|
||||
|
||||
rp2040_clock_freq[clk_index] = freq;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void clocks_init(void)
|
||||
{
|
||||
/* Start tick in watchdog */
|
||||
|
||||
putreg32((BOARD_XOSC_FREQ / MHZ) | RP2040_WATCHDOG_TICK_ENABLE,
|
||||
RP2040_WATCHDOG_TICK);
|
||||
|
||||
/* Disable resus that may be enabled from previous software */
|
||||
|
||||
putreg32(0, RP2040_CLOCKS_CLK_SYS_RESUS_CTRL);
|
||||
|
||||
/* Enable the xosc */
|
||||
|
||||
rp2040_xosc_init();
|
||||
|
||||
/* Before we touch PLLs, switch sys and ref cleanly away from their
|
||||
* aux sources.
|
||||
*/
|
||||
|
||||
clrbits_reg32(RP2040_CLOCKS_CLK_SYS_CTRL_SRC,
|
||||
RP2040_CLOCKS_CLK_SYS_CTRL);
|
||||
while (getreg32(RP2040_CLOCKS_CLK_SYS_SELECTED) != 1)
|
||||
;
|
||||
clrbits_reg32(RP2040_CLOCKS_CLK_REF_CTRL_SRC_MASK,
|
||||
RP2040_CLOCKS_CLK_REF_CTRL);
|
||||
while (getreg32(RP2040_CLOCKS_CLK_REF_SELECTED) != 1)
|
||||
;
|
||||
|
||||
/* Configure PLLs
|
||||
* REF FBDIV VCO POSTDIV
|
||||
* PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHZ / 6 / 2 = 125MHz
|
||||
* PLL USB: 12 / 1 = 12MHz * 40 = 480 MHz / 5 / 2 = 48MHz
|
||||
*/
|
||||
|
||||
setbits_reg32(RP2040_RESETS_RESET_PLL_SYS | RP2040_RESETS_RESET_PLL_USB,
|
||||
RP2040_RESETS_RESET);
|
||||
clrbits_reg32(RP2040_RESETS_RESET_PLL_SYS | RP2040_RESETS_RESET_PLL_USB,
|
||||
RP2040_RESETS_RESET);
|
||||
while (~getreg32(RP2040_RESETS_RESET_DONE) &
|
||||
(RP2040_RESETS_RESET_PLL_SYS | RP2040_RESETS_RESET_PLL_USB))
|
||||
;
|
||||
|
||||
rp2040_pll_init(RP2040_PLL_SYS_BASE, 1, 1500 * MHZ, 6, 2);
|
||||
rp2040_pll_init(RP2040_PLL_USB_BASE, 1, 480 * MHZ, 5, 2);
|
||||
|
||||
/* Configure clocks */
|
||||
|
||||
/* CLK_REF = XOSC (12MHz) / 1 = 12MHz */
|
||||
|
||||
rp2040_clock_configure(RP2040_CLOCKS_NDX_REF,
|
||||
RP2040_CLOCKS_CLK_REF_CTRL_SRC_XOSC_CLKSRC,
|
||||
0,
|
||||
BOARD_XOSC_FREQ,
|
||||
BOARD_REF_FREQ);
|
||||
|
||||
/* CLK SYS = PLL SYS (125MHz) / 1 = 125MHz */
|
||||
|
||||
rp2040_clock_configure(RP2040_CLOCKS_NDX_SYS,
|
||||
RP2040_CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX,
|
||||
RP2040_CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_PLL_SYS,
|
||||
BOARD_PLL_SYS_FREQ,
|
||||
BOARD_SYS_FREQ);
|
||||
|
||||
/* CLK USB = PLL USB (48MHz) / 1 = 48MHz */
|
||||
|
||||
rp2040_clock_configure(RP2040_CLOCKS_NDX_USB,
|
||||
0,
|
||||
RP2040_CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_PLL_USB,
|
||||
BOARD_PLL_USB_FREQ,
|
||||
BOARD_USB_FREQ);
|
||||
|
||||
/* CLK ADC = PLL USB (48MHZ) / 1 = 48MHz */
|
||||
|
||||
rp2040_clock_configure(RP2040_CLOCKS_NDX_ADC,
|
||||
0,
|
||||
RP2040_CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_PLL_USB,
|
||||
BOARD_PLL_USB_FREQ,
|
||||
BOARD_ADC_FREQ);
|
||||
|
||||
/* CLK RTC = PLL USB (48MHz) / 1024 = 46875Hz */
|
||||
|
||||
rp2040_clock_configure(RP2040_CLOCKS_NDX_RTC,
|
||||
0,
|
||||
RP2040_CLOCKS_CLK_RTC_CTRL_AUXSRC_CLKSRC_PLL_USB,
|
||||
BOARD_PLL_USB_FREQ,
|
||||
BOARD_RTC_FREQ);
|
||||
|
||||
/* CLK PERI = clk_sys. */
|
||||
|
||||
rp2040_clock_configure(RP2040_CLOCKS_NDX_PERI,
|
||||
0,
|
||||
RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLK_SYS,
|
||||
BOARD_SYS_FREQ,
|
||||
BOARD_PERI_FREQ);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp2040_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to establish the clock settings based on the values in board.h.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void rp2040_clockconfig(void)
|
||||
{
|
||||
/* Reset all peripherals to put system into a known state,
|
||||
* - except for QSPI pads and the XIP IO bank, as this is fatal if running
|
||||
* from flash
|
||||
* - and the PLLs, as this is fatal if clock muxing has not been reset on
|
||||
* this boot
|
||||
*/
|
||||
|
||||
setbits_reg32(RESETS_RESET_BITS & ~(RP2040_RESETS_RESET_IO_QSPI |
|
||||
RP2040_RESETS_RESET_PADS_QSPI |
|
||||
RP2040_RESETS_RESET_PLL_USB |
|
||||
RP2040_RESETS_RESET_PLL_SYS),
|
||||
RP2040_RESETS_RESET);
|
||||
|
||||
/* Remove reset from peripherals which are clocked only by clk_sys and
|
||||
* clk_ref. Other peripherals stay in reset until we've configured clocks.
|
||||
*/
|
||||
|
||||
clrbits_reg32(RESETS_RESET_BITS & ~(RP2040_RESETS_RESET_ADC |
|
||||
RP2040_RESETS_RESET_RTC |
|
||||
RP2040_RESETS_RESET_SPI0 |
|
||||
RP2040_RESETS_RESET_SPI1 |
|
||||
RP2040_RESETS_RESET_UART0 |
|
||||
RP2040_RESETS_RESET_UART1 |
|
||||
RP2040_RESETS_RESET_USBCTRL),
|
||||
RP2040_RESETS_RESET);
|
||||
|
||||
while (~getreg32(RP2040_RESETS_RESET_DONE) &
|
||||
(RESETS_RESET_BITS & ~(RP2040_RESETS_RESET_ADC |
|
||||
RP2040_RESETS_RESET_RTC |
|
||||
RP2040_RESETS_RESET_SPI0 |
|
||||
RP2040_RESETS_RESET_SPI1 |
|
||||
RP2040_RESETS_RESET_UART0 |
|
||||
RP2040_RESETS_RESET_UART1 |
|
||||
RP2040_RESETS_RESET_USBCTRL)))
|
||||
;
|
||||
|
||||
/* After calling preinit we have enough runtime to do the exciting maths
|
||||
* in clocks_init
|
||||
*/
|
||||
|
||||
clocks_init();
|
||||
|
||||
/* Peripheral clocks should now all be running */
|
||||
|
||||
clrbits_reg32(RESETS_RESET_BITS, RP2040_RESETS_RESET);
|
||||
while (~getreg32(RP2040_RESETS_RESET_DONE) & RESETS_RESET_BITS)
|
||||
;
|
||||
}
|
||||
64
arch/arm/src/rp2040/rp2040_clock.h
Normal file
64
arch/arm/src/rp2040/rp2040_clock.h
Normal file
@ -0,0 +1,64 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_clock.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_RP2040_CLOCK_H
|
||||
#define __ARCH_ARM_SRC_RP2040_RP2040_CLOCK_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
void rp2040_clockconfig(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_RP2040_CLOCK_H */
|
||||
97
arch/arm/src/rp2040/rp2040_config.h
Normal file
97
arch/arm/src/rp2040/rp2040_config.h
Normal file
@ -0,0 +1,97 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_config.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_RP2040_CONFIG_H
|
||||
#define __ARCH_ARM_SRC_RP2040_RP2040_CONFIG_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Required configuration settings */
|
||||
|
||||
/* Are any UARTs enabled? */
|
||||
|
||||
#undef HAVE_UART
|
||||
#if defined(CONFIG_RP2040_UART0) || defined(CONFIG_RP2040_UART1)
|
||||
# define HAVE_UART 1
|
||||
#endif
|
||||
|
||||
/* Make sure all features are disabled for diabled U[S]ARTs. This simplifies
|
||||
* checking later.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_RP2040_UART0
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART0_RS485MODE
|
||||
# undef CONFIG_UART0_RS485_DTRDIR
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RP2040_UART1
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_RS485MODE
|
||||
# undef CONFIG_UART1_RS485_DTRDIR
|
||||
#endif
|
||||
|
||||
/* Is there a serial console? There should be at most one defined. It could
|
||||
* be on any UARTn, n=0,1,2,3 - OR - there might not be any serial console at
|
||||
* all.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
# define HAVE_CONSOLE 1
|
||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
# define HAVE_CONSOLE 1
|
||||
#else
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART3_SERIAL_CONSOLE
|
||||
# undef HAVE_SERIAL_CONSOLE
|
||||
# undef HAVE_CONSOLE
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_RP2040_CONFIG_H */
|
||||
61
arch/arm/src/rp2040/rp2040_gpio.c
Normal file
61
arch/arm/src/rp2040/rp2040_gpio.c
Normal file
@ -0,0 +1,61 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_gpio.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "arm_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#include "rp2040_gpio.h"
|
||||
|
||||
#include "hardware/rp2040_pads_bank0.h"
|
||||
#include "hardware/rp2040_io_bank0.h"
|
||||
#include "hardware/rp2040_sio.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
void rp2040_gpio_set_function(uint32_t gpio, uint32_t func)
|
||||
{
|
||||
modbits_reg32(RP2040_PADS_BANK0_GPIO_IE,
|
||||
RP2040_PADS_BANK0_GPIO_IE | RP2040_PADS_BANK0_GPIO_OD,
|
||||
RP2040_PADS_BANK0_GPIO(gpio));
|
||||
|
||||
putreg32(func & RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_MASK,
|
||||
RP2040_IO_BANK0_GPIO_CTRL(gpio));
|
||||
}
|
||||
64
arch/arm/src/rp2040/rp2040_gpio.h
Normal file
64
arch/arm/src/rp2040/rp2040_gpio.h
Normal file
@ -0,0 +1,64 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_gpio.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_RP2040_GPIO_H
|
||||
#define __ARCH_ARM_SRC_RP2040_RP2040_GPIO_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
void rp2040_gpio_set_function(uint32_t gpio, uint32_t func);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_RP2040_GPIO_H */
|
||||
92
arch/arm/src/rp2040/rp2040_idle.c
Normal file
92
arch/arm/src/rp2040/rp2040_idle.c
Normal file
@ -0,0 +1,92 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_idle.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Does the board support an IDLE LED to indicate that the board is in the
|
||||
* IDLE state?
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
|
||||
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
|
||||
# define END_IDLE() board_autoled_off(LED_IDLE)
|
||||
#else
|
||||
# define BEGIN_IDLE()
|
||||
# define END_IDLE()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_idle
|
||||
*
|
||||
* Description:
|
||||
* up_idle() is the logic that will be executed when there is no other
|
||||
* ready-to-run task. This is processor idle time and will continue until
|
||||
* some interrupt occurs to cause a context switch from the idle task.
|
||||
*
|
||||
* Processing in this state may be processor-specific. e.g., this is where
|
||||
* power management operations might be performed.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_idle(void)
|
||||
{
|
||||
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
|
||||
/* If the system is idle and there are no timer interrupts, then process
|
||||
* "fake" timer interrupts. Hopefully, something will wake up.
|
||||
*/
|
||||
|
||||
nxsched_process_timer();
|
||||
#else
|
||||
|
||||
/* Sleep until an interrupt occurs to save power */
|
||||
|
||||
BEGIN_IDLE();
|
||||
asm("WFI");
|
||||
END_IDLE();
|
||||
#endif
|
||||
}
|
||||
414
arch/arm/src/rp2040/rp2040_irq.c
Normal file
414
arch/arm/src/rp2040/rp2040_irq.c
Normal file
@ -0,0 +1,414 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_irq.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/irq.h>
|
||||
|
||||
#include "nvic.h"
|
||||
#include "ram_vectors.h"
|
||||
#include "arm_arch.h"
|
||||
#include "arm_internal.h"
|
||||
|
||||
#include "rp2040_irq.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Get a 32-bit version of the default priority */
|
||||
|
||||
#define DEFPRIORITY32 \
|
||||
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
|
||||
NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/* g_current_regs[] holds a references to the current interrupt level
|
||||
* register storage structure. If is non-NULL only during interrupt
|
||||
* processing. Access to g_current_regs[] must be through the macro
|
||||
* CURRENT_REGS for portability.
|
||||
*/
|
||||
|
||||
volatile uint32_t *g_current_regs[1];
|
||||
|
||||
/* This is the address of the exception vector table (determined by the
|
||||
* linker script).
|
||||
*/
|
||||
|
||||
extern uint32_t _vectors[];
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp2040_dumpnvic
|
||||
*
|
||||
* Description:
|
||||
* Dump some interesting NVIC registers
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_DEBUG_IRQ_INFO)
|
||||
static void rp2040_dumpnvic(const char *msg, int irq)
|
||||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
|
||||
irqinfo(" ISER: %08x ICER: %08x\n",
|
||||
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
|
||||
irqinfo(" ISPR: %08x ICPR: %08x\n",
|
||||
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
|
||||
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
|
||||
getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
|
||||
getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
|
||||
irqinfo(" %08x %08x %08x %08x\n",
|
||||
getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
|
||||
getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
|
||||
|
||||
irqinfo("SYSCON:\n");
|
||||
irqinfo(" CPUID: %08x\n",
|
||||
getreg32(ARMV6M_SYSCON_CPUID));
|
||||
irqinfo(" ICSR: %08x AIRCR: %08x\n",
|
||||
getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
|
||||
irqinfo(" SCR: %08x CCR: %08x\n",
|
||||
getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
|
||||
irqinfo(" SHPR2: %08x SHPR3: %08x\n",
|
||||
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
#else
|
||||
# define rp2040_dumpnvic(msg, irq)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp2040_nmi, rp2040_busfault, rp2040_usagefault, rp2040_pendsv,
|
||||
* rp2040_dbgmonitor, rp2040_pendsv, rp2040_reserved
|
||||
*
|
||||
* Description:
|
||||
* Handlers for various exceptions. None are handled and all are fatal
|
||||
* error conditions. The only advantage these provided over the default
|
||||
* unexpected interrupt handler is that they provide a diagnostic output.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
static int rp2040_nmi(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
up_irq_save();
|
||||
_err("PANIC!!! NMI received\n");
|
||||
PANIC();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rp2040_pendsv(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
up_irq_save();
|
||||
_err("PANIC!!! PendSV received\n");
|
||||
PANIC();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rp2040_reserved(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
up_irq_save();
|
||||
_err("PANIC!!! Reserved interrupt\n");
|
||||
PANIC();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp2040_clrpend
|
||||
*
|
||||
* Description:
|
||||
* Clear a pending interrupt at the NVIC.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rp2040_clrpend(int irq)
|
||||
{
|
||||
/* This will be called on each interrupt exit whether the interrupt can be
|
||||
* enambled or not. So this assertion is necessarily lame.
|
||||
*/
|
||||
|
||||
DEBUGASSERT((unsigned)irq < NR_IRQS);
|
||||
|
||||
/* Check for an external interrupt */
|
||||
|
||||
if (irq >= RP2040_IRQ_EXTINT && irq < RP2040_IRQ_EXTINT + 32)
|
||||
{
|
||||
/* Set the appropriate bit in the ISER register to enable the
|
||||
* interrupt
|
||||
*/
|
||||
|
||||
putreg32((1 << (irq - RP2040_IRQ_EXTINT)), ARMV6M_NVIC_ICPR);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_irqinitialize
|
||||
****************************************************************************/
|
||||
|
||||
void up_irqinitialize(void)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
int i;
|
||||
|
||||
/* Disable all interrupts */
|
||||
|
||||
putreg32(0xffffffff, ARMV6M_NVIC_ICER);
|
||||
putreg32(0, ARMV6M_SYSTICK_CSR);
|
||||
|
||||
/* Set all interrupts (and exceptions) to the default priority */
|
||||
|
||||
putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR2);
|
||||
putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR3);
|
||||
|
||||
/* Make sure that we are using the correct vector table. The default
|
||||
* vector address is 0x0000:0000 but if we are executing code that is
|
||||
* positioned in SRAM or in external FLASH, then we may need to reset
|
||||
* the interrupt vector so that it refers to the table in SRAM or in
|
||||
* external FLASH.
|
||||
*/
|
||||
|
||||
putreg32((uint32_t)_vectors, ARMV6M_SYSCON_VECTAB);
|
||||
|
||||
#ifdef CONFIG_ARCH_RAMVECTORS
|
||||
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
|
||||
* vector table that requires special initialization.
|
||||
*/
|
||||
|
||||
arm_ramvec_initialize();
|
||||
#endif
|
||||
|
||||
/* Now set all of the interrupt lines to the default priority */
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
regaddr = ARMV6M_NVIC_IPR(i);
|
||||
putreg32(DEFPRIORITY32, regaddr);
|
||||
}
|
||||
|
||||
/* currents_regs is non-NULL only while processing an interrupt */
|
||||
|
||||
CURRENT_REGS = NULL;
|
||||
|
||||
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
|
||||
* exception is used for performing context switches; The Hard Fault
|
||||
* must also be caught because a SVCall may show up as a Hard Fault
|
||||
* under certain conditions.
|
||||
*/
|
||||
|
||||
irq_attach(RP2040_IRQ_SVCALL, arm_svcall, NULL);
|
||||
irq_attach(RP2040_IRQ_HARDFAULT, arm_hardfault, NULL);
|
||||
|
||||
/* Attach all other processor exceptions (except reset and sys tick) */
|
||||
|
||||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
irq_attach(RP2040_IRQ_NMI, rp2040_nmi, NULL);
|
||||
irq_attach(RP2040_IRQ_PENDSV, rp2040_pendsv, NULL);
|
||||
irq_attach(RP2040_IRQ_RESERVED, rp2040_reserved, NULL);
|
||||
#endif
|
||||
|
||||
rp2040_dumpnvic("initial", NR_IRQS);
|
||||
|
||||
/* And finally, enable interrupts */
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_INTERRUPTS
|
||||
up_irq_enable();
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_disable_irq
|
||||
*
|
||||
* Description:
|
||||
* Disable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_disable_irq(int irq)
|
||||
{
|
||||
DEBUGASSERT((unsigned)irq < NR_IRQS);
|
||||
|
||||
/* Check for an external interrupt */
|
||||
|
||||
if (irq >= RP2040_IRQ_EXTINT && irq < RP2040_IRQ_EXTINT + 32)
|
||||
{
|
||||
/* Set the appropriate bit in the ICER register to disable the
|
||||
* interrupt
|
||||
*/
|
||||
|
||||
putreg32((1 << (irq - RP2040_IRQ_EXTINT)), ARMV6M_NVIC_ICER);
|
||||
}
|
||||
|
||||
/* Handle processor exceptions. Only SysTick can be disabled */
|
||||
|
||||
else if (irq == RP2040_IRQ_SYSTICK)
|
||||
{
|
||||
modifyreg32(ARMV6M_SYSTICK_CSR, SYSTICK_CSR_ENABLE, 0);
|
||||
}
|
||||
|
||||
rp2040_dumpnvic("disable", irq);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_enable_irq
|
||||
*
|
||||
* Description:
|
||||
* Enable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_enable_irq(int irq)
|
||||
{
|
||||
/* This will be called on each interrupt exit whether the interrupt can be
|
||||
* enambled or not. So this assertion is necessarily lame.
|
||||
*/
|
||||
|
||||
DEBUGASSERT((unsigned)irq < NR_IRQS);
|
||||
|
||||
/* Check for external interrupt */
|
||||
|
||||
if (irq >= RP2040_IRQ_EXTINT && irq < RP2040_IRQ_EXTINT + 32)
|
||||
{
|
||||
/* Set the appropriate bit in the ISER register to enable the
|
||||
* interrupt
|
||||
*/
|
||||
|
||||
putreg32((1 << (irq - RP2040_IRQ_EXTINT)), ARMV6M_NVIC_ISER);
|
||||
}
|
||||
|
||||
/* Handle processor exceptions. Only SysTick can be disabled */
|
||||
|
||||
else if (irq == RP2040_IRQ_SYSTICK)
|
||||
{
|
||||
modifyreg32(ARMV6M_SYSTICK_CSR, 0, SYSTICK_CSR_ENABLE);
|
||||
}
|
||||
|
||||
rp2040_dumpnvic("enable", irq);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_ack_irq
|
||||
*
|
||||
* Description:
|
||||
* Acknowledge the IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void arm_ack_irq(int irq)
|
||||
{
|
||||
rp2040_clrpend(irq);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_prioritize_irq
|
||||
*
|
||||
* Description:
|
||||
* Set the priority of an IRQ.
|
||||
*
|
||||
* Since this API is not supported on all architectures, it should be
|
||||
* avoided in common implementations where possible.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
int up_prioritize_irq(int irq, int priority)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
DEBUGASSERT(irq == RP2040_IRQ_SVCALL ||
|
||||
irq == RP2040_IRQ_PENDSV ||
|
||||
irq == RP2040_IRQ_SYSTICK ||
|
||||
(irq >= RP2040_IRQ_EXTINT && irq < NR_IRQS));
|
||||
DEBUGASSERT(priority >= NVIC_SYSH_PRIORITY_MAX &&
|
||||
priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
|
||||
/* Check for external interrupt */
|
||||
|
||||
if (irq >= RP2040_IRQ_EXTINT && irq < RP2040_IRQ_EXTINT + 32)
|
||||
{
|
||||
/* ARMV6M_NVIC_IPR() maps register IPR0-IPR7 with four settings per
|
||||
* register.
|
||||
*/
|
||||
|
||||
regaddr = ARMV6M_NVIC_IPR(irq >> 2);
|
||||
shift = (irq & 3) << 3;
|
||||
}
|
||||
|
||||
/* Handle processor exceptions. Only SVCall, PendSV, and SysTick can be
|
||||
* reprioritized. And we will not permit modification of SVCall through
|
||||
* this function.
|
||||
*/
|
||||
|
||||
else if (irq == RP2040_IRQ_PENDSV)
|
||||
{
|
||||
regaddr = ARMV6M_SYSCON_SHPR2;
|
||||
shift = SYSCON_SHPR3_PRI_14_SHIFT;
|
||||
}
|
||||
else if (irq == RP2040_IRQ_SYSTICK)
|
||||
{
|
||||
regaddr = ARMV6M_SYSCON_SHPR2;
|
||||
shift = SYSCON_SHPR3_PRI_15_SHIFT;
|
||||
}
|
||||
else
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/* Set the priority */
|
||||
|
||||
regval = getreg32(regaddr);
|
||||
regval &= ~((uint32_t)0xff << shift);
|
||||
regval |= ((uint32_t)priority << shift);
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
rp2040_dumpnvic("prioritize", irq);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
50
arch/arm/src/rp2040/rp2040_irq.h
Normal file
50
arch/arm/src/rp2040/rp2040_irq.h
Normal file
@ -0,0 +1,50 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_irq.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_RP2040_IRQ_H
|
||||
#define __ARCH_ARM_SRC_RP2040_RP2040_IRQ_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_RP2040_IRQ_H */
|
||||
124
arch/arm/src/rp2040/rp2040_pll.c
Normal file
124
arch/arm/src/rp2040/rp2040_pll.c
Normal file
@ -0,0 +1,124 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_pll.c
|
||||
*
|
||||
* Based upon the software originally developed by
|
||||
* Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "arm_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#include "rp2040_pll.h"
|
||||
#include "hardware/rp2040_pll.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp2040_pll_init
|
||||
*
|
||||
* Description:
|
||||
* Initialize PLL.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void rp2040_pll_init(uint32_t base, uint32_t refdiv, uint32_t vco_freq,
|
||||
uint32_t post_div1, uint8_t post_div2)
|
||||
{
|
||||
/* Turn off PLL in case it is already running */
|
||||
|
||||
putreg32(0xffffffff, base + RP2040_PLL_PWR_OFFSET);
|
||||
putreg32(0, base + RP2040_PLL_FBDIV_INT_OFFSET);
|
||||
|
||||
uint32_t ref_mhz = BOARD_XOSC_FREQ / refdiv;
|
||||
putreg32(refdiv, base + RP2040_PLL_CS_OFFSET);
|
||||
|
||||
/* What are we multiplying the reference clock by to get the vco freq
|
||||
* (The regs are called div, because you divide the vco output and compare
|
||||
* it to the refclk)
|
||||
*/
|
||||
|
||||
uint32_t fbdiv = vco_freq / ref_mhz;
|
||||
|
||||
/* Check parameter ranges */
|
||||
|
||||
assert(fbdiv >= 16 && fbdiv <= 320);
|
||||
assert((post_div1 >= 1 && post_div1 <= 7) &&
|
||||
(post_div2 >= 1 && post_div2 <= 7));
|
||||
assert(post_div2 <= post_div1);
|
||||
assert(ref_mhz <= (vco_freq / 16));
|
||||
|
||||
/* Put calculated value into feedback divider */
|
||||
|
||||
putreg32(fbdiv, base + RP2040_PLL_FBDIV_INT_OFFSET);
|
||||
|
||||
/* Turn on PLL */
|
||||
|
||||
clrbits_reg32(RP2040_PLL_PWR_PD | RP2040_PLL_PWR_VCOPD,
|
||||
base + RP2040_PLL_PWR_OFFSET);
|
||||
|
||||
/* Wait for PLL to lock */
|
||||
|
||||
while (!(getreg32(base + RP2040_PLL_CS_OFFSET) & RP2040_PLL_CS_LOCK))
|
||||
;
|
||||
|
||||
/* Set up post dividers */
|
||||
|
||||
putreg32((post_div1 << RP2040_PLL_PRIM_POSTDIV1_SHIFT) |
|
||||
(post_div2 << RP2040_PLL_PRIM_POSTDIV2_SHIFT),
|
||||
base + RP2040_PLL_PRIM_OFFSET);
|
||||
|
||||
/* Turn on post divider */
|
||||
|
||||
clrbits_reg32(RP2040_PLL_PWR_POSTDIVPD, base + RP2040_PLL_PWR_OFFSET);
|
||||
}
|
||||
73
arch/arm/src/rp2040/rp2040_pll.h
Normal file
73
arch/arm/src/rp2040/rp2040_pll.h
Normal file
@ -0,0 +1,73 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_pll.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_RP2040_PLL_H
|
||||
#define __ARCH_ARM_SRC_RP2040_RP2040_PLL_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp2040_pll_init
|
||||
*
|
||||
* Description:
|
||||
* Initialize PLL.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void rp2040_pll_init(uint32_t base, uint32_t refdiv, uint32_t vco_freq,
|
||||
uint32_t post_div1, uint8_t post_div2);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_RP2040_PLL_H */
|
||||
1072
arch/arm/src/rp2040/rp2040_serial.c
Normal file
1072
arch/arm/src/rp2040/rp2040_serial.c
Normal file
File diff suppressed because it is too large
Load Diff
51
arch/arm/src/rp2040/rp2040_serial.h
Normal file
51
arch/arm/src/rp2040/rp2040_serial.h
Normal file
@ -0,0 +1,51 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_serial.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_RP2040_SERIAL_H
|
||||
#define __ARCH_ARM_SRC_RP2040_RP2040_SERIAL_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "rp2040_uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_RP2040_SERIAL_H */
|
||||
154
arch/arm/src/rp2040/rp2040_start.c
Normal file
154
arch/arm/src/rp2040/rp2040_start.c
Normal file
@ -0,0 +1,154 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_start.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/init.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "arm_arch.h"
|
||||
#include "arm_internal.h"
|
||||
|
||||
#include "rp2040_config.h"
|
||||
#include "rp2040_clock.h"
|
||||
#include "rp2040_uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define IDLE_STACK ((uint32_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
|
||||
#define HEAP_BASE ((uint32_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
const uintptr_t g_idle_topstack = IDLE_STACK;
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: showprogress
|
||||
*
|
||||
* Description:
|
||||
* Print a character on the UART to show boot status.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_DEBUG_FEATURES) && defined(HAVE_SERIAL_CONSOLE)
|
||||
# define showprogress(c) arm_lowputc((uint32_t)c)
|
||||
#else
|
||||
# define showprogress(c)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: _start
|
||||
*
|
||||
* Description:
|
||||
* This is the reset entry point.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void __start(void)
|
||||
{
|
||||
#ifdef CONFIG_RP2040_FLASH_BOOT
|
||||
const uint32_t *src;
|
||||
#endif
|
||||
uint32_t *dest;
|
||||
|
||||
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
|
||||
* certain that there are no issues with the state of global variables.
|
||||
*/
|
||||
|
||||
for (dest = &_sbss; dest < &_ebss; )
|
||||
{
|
||||
*dest++ = 0;
|
||||
}
|
||||
|
||||
/* Configure the uart so that we can get debug output as soon as possible */
|
||||
|
||||
rp2040_clockconfig();
|
||||
rp2040_boardearlyinitialize();
|
||||
rp2040_lowsetup();
|
||||
showprogress('A');
|
||||
|
||||
/* Move the initialized data section from his temporary holding spot in
|
||||
* FLASH into the correct place in SRAM. The correct place in SRAM is
|
||||
* give by _sdata and _edata. The temporary location is in FLASH at the
|
||||
* end of all of the other read-only data (.text, .rodata) at _eronly.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_RP2040_FLASH_BOOT
|
||||
for (src = &_eronly, dest = &_sdata; dest < &_edata; )
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
#endif
|
||||
|
||||
showprogress('B');
|
||||
|
||||
/* Perform early serial initialization */
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
arm_earlyserialinit();
|
||||
#endif
|
||||
showprogress('C');
|
||||
|
||||
/* For the case of the separate user-/kernel-space build, perform whatever
|
||||
* platform specific initialization of the user memory is required.
|
||||
* Normally this just means initializing the user space .data and .bss
|
||||
* segments.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
rp2040_userspace();
|
||||
showprogress('D');
|
||||
#endif
|
||||
|
||||
/* Initialize onboard resources */
|
||||
|
||||
rp2040_boardinitialize();
|
||||
showprogress('E');
|
||||
|
||||
/* Then start NuttX */
|
||||
|
||||
showprogress('\r');
|
||||
showprogress('\n');
|
||||
nx_start();
|
||||
|
||||
/* Shouldn't get here */
|
||||
|
||||
for (; ; );
|
||||
}
|
||||
126
arch/arm/src/rp2040/rp2040_timerisr.c
Normal file
126
arch/arm/src/rp2040/rp2040_timerisr.c
Normal file
@ -0,0 +1,126 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_timerisr.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <time.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "nvic.h"
|
||||
#include "clock/clock.h"
|
||||
#include "arm_internal.h"
|
||||
#include "arm_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* The SysTick is driven by watchdog tock clock. */
|
||||
|
||||
#define SYSTICK_CLOCK BOARD_TICK_CLOCK
|
||||
|
||||
/* The desired timer interrupt frequency is provided by the definition
|
||||
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
|
||||
* system clock ticks per second. That value is a user configurable setting
|
||||
* that defaults to 100 (100 ticks per second = 10 MS interval).
|
||||
*/
|
||||
|
||||
#define SYSTICK_RELOAD ((SYSTICK_CLOCK / CLK_TCK) - 1)
|
||||
|
||||
/* The size of the reload field is 24 bits. Verify that the reload value
|
||||
* will fit in the reload register.
|
||||
*/
|
||||
|
||||
#if SYSTICK_RELOAD > 0x00ffffff
|
||||
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Function: rp2040_timerisr
|
||||
*
|
||||
* Description:
|
||||
* The timer ISR will perform a variety of services for various portions
|
||||
* of the systems.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int rp2040_timerisr(int irq, uint32_t *regs, void *arg)
|
||||
{
|
||||
/* Process timer interrupt */
|
||||
|
||||
nxsched_process_timer();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Function: up_timer_initialize
|
||||
*
|
||||
* Description:
|
||||
* This function is called during start-up to initialize
|
||||
* the timer interrupt.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_timer_initialize(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the SysTick interrupt to the default priority */
|
||||
|
||||
regval = getreg32(ARMV6M_SYSCON_SHPR3);
|
||||
regval &= ~SYSCON_SHPR3_PRI_15_MASK;
|
||||
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << SYSCON_SHPR3_PRI_15_SHIFT);
|
||||
putreg32(regval, ARMV6M_SYSCON_SHPR3);
|
||||
|
||||
/* Configure SysTick to interrupt at the requested rate */
|
||||
|
||||
putreg32(SYSTICK_RELOAD, ARMV6M_SYSTICK_RVR);
|
||||
putreg32(0, ARMV6M_SYSTICK_CVR);
|
||||
|
||||
/* Attach the timer interrupt vector */
|
||||
|
||||
irq_attach(RP2040_IRQ_SYSTICK, (xcpt_t)rp2040_timerisr, NULL);
|
||||
|
||||
/* Enable SysTick interrupts. */
|
||||
|
||||
putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR);
|
||||
|
||||
/* And enable the timer interrupt */
|
||||
|
||||
up_enable_irq(RP2040_IRQ_SYSTICK);
|
||||
}
|
||||
212
arch/arm/src/rp2040/rp2040_uart.c
Normal file
212
arch/arm/src/rp2040/rp2040_uart.c
Normal file
@ -0,0 +1,212 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_uart.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
#include "arm_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
#include "rp2040_config.h"
|
||||
#include "rp2040_uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Select UART parameters for the selected console */
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||
#define CONSOLE_BASE RP2040_UART0_BASE
|
||||
#define CONSOLE_BASEFREQ BOARD_UART_BASEFREQ
|
||||
#define CONSOLE_BAUD CONFIG_UART0_BAUD
|
||||
#define CONSOLE_BITS CONFIG_UART0_BITS
|
||||
#define CONSOLE_PARITY CONFIG_UART0_PARITY
|
||||
#define CONSOLE_2STOP CONFIG_UART0_2STOP
|
||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
|
||||
#define CONSOLE_BASE RP2040_UART1_BASE
|
||||
#define CONSOLE_BASEFREQ BOARD_UART_BASEFREQ
|
||||
#define CONSOLE_BAUD CONFIG_UART1_BAUD
|
||||
#define CONSOLE_BITS CONFIG_UART1_BITS
|
||||
#define CONSOLE_PARITY CONFIG_UART1_PARITY
|
||||
#define CONSOLE_2STOP CONFIG_UART1_2STOP
|
||||
#elif defined(HAVE_CONSOLE)
|
||||
#error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
|
||||
#endif
|
||||
|
||||
/* Get word length setting for the console */
|
||||
|
||||
#if CONSOLE_BITS >= 5 && CONSOLE_BITS <= 8
|
||||
#define CONSOLE_LCR_WLS RP2040_UART_LCR_H_WLEN(CONSOLE_BITS)
|
||||
#elif defined(HAVE_CONSOLE)
|
||||
#error "Invalid CONFIG_UARTn_BITS setting for console "
|
||||
#endif
|
||||
|
||||
/* Get parity setting for the console */
|
||||
|
||||
#if CONSOLE_PARITY == 0
|
||||
#define CONSOLE_LCR_PAR 0
|
||||
#elif CONSOLE_PARITY == 1
|
||||
#define CONSOLE_LCR_PAR (RP2040_UART_UARTLCR_H_PEN)
|
||||
#elif CONSOLE_PARITY == 2
|
||||
#define CONSOLE_LCR_PAR (RP2040_UART_UARTLCR_H_PEN | RP2040_UART_UARTLCR_H_EPS)
|
||||
#elif defined(HAVE_CONSOLE)
|
||||
#error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE"
|
||||
#endif
|
||||
|
||||
/* Get stop-bit setting for the console and UART0/1/2 */
|
||||
|
||||
#if CONSOLE_2STOP != 0
|
||||
#define CONSOLE_LCR_STOP RP2040_UART_UARTLCR_H_STP2
|
||||
#else
|
||||
#define CONSOLE_LCR_STOP 0
|
||||
#endif
|
||||
|
||||
/* LCR and FCR values for the console */
|
||||
|
||||
#define CONSOLE_LCR_VALUE (CONSOLE_LCR_WLS | CONSOLE_LCR_PAR | CONSOLE_LCR_STOP)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_lowputc
|
||||
*
|
||||
* Description:
|
||||
* Output one byte on the serial console
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void arm_lowputc(char ch)
|
||||
{
|
||||
#if defined HAVE_UART && defined HAVE_CONSOLE
|
||||
/* Wait for the transmitter to be available */
|
||||
|
||||
while ((getreg32(CONSOLE_BASE + RP2040_UART_UARTFR_OFFSET) &
|
||||
RP2040_UART_UARTFR_TXFF))
|
||||
;
|
||||
|
||||
/* Send the character */
|
||||
|
||||
putreg32((uint32_t)ch, CONSOLE_BASE + RP2040_UART_UARTDR_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp2040_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* This performs basic initialization of the UART used for the serial
|
||||
* console. Its purpose is to get the console output available as soon
|
||||
* as possible.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void rp2040_lowsetup(void)
|
||||
{
|
||||
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
uint32_t cr;
|
||||
|
||||
cr = getreg32(CONSOLE_BASE + RP2040_UART_UARTCR_OFFSET);
|
||||
putreg32(cr & ~RP2040_UART_UARTCR_UARTEN,
|
||||
CONSOLE_BASE + RP2040_UART_UARTCR_OFFSET);
|
||||
|
||||
putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE + RP2040_UART_UARTLCR_H_OFFSET);
|
||||
rp2040_setbaud(CONSOLE_BASE, CONSOLE_BASEFREQ, CONSOLE_BAUD);
|
||||
putreg32(0, CONSOLE_BASE + RP2040_UART_UARTIFLS_OFFSET);
|
||||
putreg32(RP2040_UART_INTR_ALL, CONSOLE_BASE + RP2040_UART_UARTICR_OFFSET);
|
||||
|
||||
cr |= RP2040_UART_UARTCR_RXE | RP2040_UART_UARTCR_TXE |
|
||||
RP2040_UART_UARTCR_UARTEN;
|
||||
putreg32(cr, CONSOLE_BASE + RP2040_UART_UARTCR_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp2040_setbaud
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void rp2040_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
|
||||
{
|
||||
uint32_t ibrd;
|
||||
uint32_t fbrd;
|
||||
uint32_t div;
|
||||
uint32_t lcr_h;
|
||||
|
||||
irqstate_t flags = spin_lock_irqsave(NULL);
|
||||
|
||||
div = basefreq / (16 * baud / 100);
|
||||
ibrd = div / 100;
|
||||
|
||||
/* fbrd will be up to 63 ((99 * 64 + 50) / 100 = 6386 / 100 = 63) */
|
||||
|
||||
fbrd = (((div % 100) * 64) + 50) / 100;
|
||||
|
||||
/* Invalid baud rate divider setting combination */
|
||||
|
||||
if (ibrd == 0 || (ibrd == 65535 && fbrd != 0))
|
||||
{
|
||||
goto finish;
|
||||
}
|
||||
|
||||
putreg32(ibrd, uartbase + RP2040_UART_UARTIBRD_OFFSET);
|
||||
putreg32(fbrd, uartbase + RP2040_UART_UARTFBRD_OFFSET);
|
||||
|
||||
/* Baud rate is updated by writing to LCR_H */
|
||||
|
||||
lcr_h = getreg32(uartbase + RP2040_UART_UARTLCR_H_OFFSET);
|
||||
putreg32(lcr_h, uartbase + RP2040_UART_UARTLCR_H_OFFSET);
|
||||
|
||||
finish:
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
}
|
||||
56
arch/arm/src/rp2040/rp2040_uart.h
Normal file
56
arch/arm/src/rp2040/rp2040_uart.h
Normal file
@ -0,0 +1,56 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_uart.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_RP2040_UART_H
|
||||
#define __ARCH_ARM_SRC_RP2040_RP2040_UART_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
#include "hardware/rp2040_uart01.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
void rp2040_lowsetup(void);
|
||||
void rp2040_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_RP2040_UART_H */
|
||||
95
arch/arm/src/rp2040/rp2040_xosc.c
Normal file
95
arch/arm/src/rp2040/rp2040_xosc.c
Normal file
@ -0,0 +1,95 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_xosc.c
|
||||
*
|
||||
* Based upon the software originally developed by
|
||||
* Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "arm_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#include "rp2040_xosc.h"
|
||||
#include "hardware/rp2040_xosc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp2040_xosc_init
|
||||
*
|
||||
* Description:
|
||||
* Initialize Crystal Oscillator (XOSC).
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void rp2040_xosc_init(void)
|
||||
{
|
||||
/* Assumes 1-15 MHz input */
|
||||
|
||||
assert(BOARD_XOSC_FREQ <= (15 * MHZ));
|
||||
putreg32(RP2040_XOSC_CTRL_FREQ_RANGE_1_15MHZ, RP2040_XOSC_CTRL);
|
||||
|
||||
/* Set xosc startup delay */
|
||||
|
||||
uint32_t startup_delay = (((12 * MHZ) / 1000) + 128) / 256;
|
||||
putreg32(startup_delay, RP2040_XOSC_STARTUP);
|
||||
|
||||
/* Set the enable bit now that we have set freq range and startup delay */
|
||||
|
||||
setbits_reg32(RP2040_XOSC_CTRL_ENABLE_ENABLE, RP2040_XOSC_CTRL);
|
||||
|
||||
/* Wait for XOSC to be stable */
|
||||
|
||||
while (!(getreg32(RP2040_XOSC_STATUS) & RP2040_XOSC_STATUS_STABLE))
|
||||
;
|
||||
}
|
||||
72
arch/arm/src/rp2040/rp2040_xosc.h
Normal file
72
arch/arm/src/rp2040/rp2040_xosc.h
Normal file
@ -0,0 +1,72 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/rp2040/rp2040_xosc.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP2040_RP2040_XOSC_H
|
||||
#define __ARCH_ARM_SRC_RP2040_RP2040_XOSC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp2040_xosc_init
|
||||
*
|
||||
* Description:
|
||||
* Initialize Crystal Oscillator (XOSC).
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void rp2040_xosc_init(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_RP2040_XOSC_H */
|
||||
Loading…
Reference in New Issue
Block a user