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Replace explicit hex MMU value with definition

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This commit is contained in:
Gregory Nutt 2013-12-18 12:47:43 -06:00
parent e9d7ab1ba3
commit ed56d3aa83
3 changed files with 10 additions and 8 deletions
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2
arch/arm/src/a1x/a1x_irq.c
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@ -96,7 +96,7 @@ static void a1x_dumpintc(const char *msg, int irq)
lldbg("ARMv7 (%s, irq=%d):\n", msg, irq);
lldbg(" CPSR: %08x SCTLR: %08x\n", flags, cp15_rdsctlr());
/* Dump all of the (readable) register contents */
/* Dump all of the (readable) INTC register contents */
lldbg("INTC (%s, irq=%d):\n", msg, irq);
lldbg(" VECTOR: %08x BASE: %08x PROTECT: %08x NMICTRL: %08x\n",

2
arch/arm/src/armv7-a/arm_head.S
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@ -377,7 +377,7 @@ __start:
* r5 = Address of the base of the L1 table
*/
orr r1, r5, #0x48 /* Select cache properties */
orr r1, r5, #(TTBR0_RGN_WBWA | TTBR0_IRGN0) /* Select cache properties */
mcr CP15_TTBR0(r1)
mcr CP15_TTBR1(r1)

14
arch/arm/src/armv7-a/mmu.h
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@ -88,7 +88,8 @@
/* Translation Table Base Register 0 (TTBR0)*/
#define TTBR0_IRGN1 (1 << 0) /* Bit 0: Inner cacheability for table walk */
#define TTBR0_IRGN1 (1 << 0) /* Bit 0: Inner cacheability IRGN[1] (MP extensions) */
#define TTBR0_C (1 << 0) /* Bit 0: Inner cacheability for table walk */
#define TTBR0_S (1 << 1) /* Bit 1: Translation table walk */
/* Bit 2: Reserved */
#define TTBR0_RGN_SHIFT (3) /* Bits 3-4: Outer cacheable attributes for table walk */
@ -97,8 +98,8 @@
# define TTBR0_RGN_WBWA (1 << TTBR0_RGN_SHIFT) /* Write-Back cached + Write-Allocate */
# define TTBR0_RGN_WT (2 << TTBR0_RGN_SHIFT) /* Write-Through */
# define TTBR0_RGN_WB (3 << TTBR0_RGN_SHIFT) /* Write-Back */
/* Bit 5: Reserved */
#define TTBR0_IRGN0 (1 << 6) /* Bit 6: Inner cacheability (with IRGN0) */
#define TTBR0_NOS (1 << 5) /* Bit 5: Not Outer Shareable bit */
#define TTBR0_IRGN0 (1 << 6) /* Bit 6: Inner cacheability IRGN[0] (MP extensions) */
/* Bits 7-n: Reserved, n=7-13 */
#define _TTBR0_LOWER(n) (0xffffffff << (n))
/* Bits (n+1)-31: Translation table base 0 */
@ -106,7 +107,8 @@
/* Translation Table Base Register 1 (TTBR1) */
#define TTBR1_IRGN1 (1 << 0) /* Bit 0: Inner cacheability for table walk */
#define TTBR1_IRGN1 (1 << 0) /* Bit 0: Inner cacheability IRGN[1] (MP extensions) */
#define TTBR1_C (1 << 0) /* Bit 0: Inner cacheability for table walk */
#define TTBR1_S (1 << 1) /* Bit 1: Translation table walk */
/* Bit 2: Reserved */
#define TTBR1_RGN_SHIFT (3) /* Bits 3-4: Outer cacheable attributes for table walk */
@ -115,8 +117,8 @@
# define TTBR1_RGN_WBWA (1 << TTBR1_RGN_SHIFT) /* Write-Back cached + Write-Allocate */
# define TTBR1_RGN_WT (2 << TTBR1_RGN_SHIFT) /* Write-Through */
# define TTBR1_RGN_WB (3 << TTBR1_RGN_SHIFT) /* Write-Back */
/* Bit 5: Reserved */
#define TTBR1_IRGN0 (1 << 6) /* Bit 6: Inner cacheability (with IRGN0) */
#define TTBR1_NOS (1 << 5) /* Bit 5: Not Outer Shareable bit */
#define TTBR1_IRGN0 (1 << 6) /* Bit 6: Inner cacheability IRGN[0] (MP extensions) */
/* Bits 7-13: Reserved */
#define TTBR1_BASE_SHIFT (14) /* Bits 14-31: Translation table base 1 */
#define TTBR1_BASE_MASK (0xffffc000)