SAML21: Add DAC register definition header file
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Gregory Nutt
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arch/arm/src/samdl/chip/saml_dac.h
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arch/arm/src/samdl/chip/saml_dac.h
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/********************************************************************************************
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* arch/arm/src/samdl/chip/saml_dac.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAML_DAC_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAML_DAC_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#ifdef CONFIG_ARCH_FAMILY_SAML21
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* DAC register offsets ********************************************************************/
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#define SAM_DAC_CTRLA_OFFSET 0x0000 /* Control A Register */
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#define SAM_DAC_CTRLB_OFFSET 0x0001 /* Control B Register */
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#define SAM_DAC_EVCTRL_OFFSET 0x0002 /* Event Control Register */
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#define SAM_DAC_INTENCLR_OFFSET 0x0004 /* Interrupt Enable Clear Register */
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#define SAM_DAC_INTENSET_OFFSET 0x0005 /* Interrupt Enable Set Register */
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#define SAM_DAC_INTFLAG_OFFSET 0x0006 /* Interrupt Flag Status and Clear Register */
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#define SAM_DAC_STATUS_OFFSET 0x0007 /* Status Register */
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#define SAM_DAC_SYNCBUSY_OFFSET 0x0008 /* Synchronization Busy Register */
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#define SAM_DAC_DACCTRL0_OFFSET 0x000c /* DAC0 Control Register */
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#define SAM_DAC_DACCTRL1_OFFSET 0x000e /* DAC1 Control Register */
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#define SAM_DAC_DATA0_OFFSET 0x0010 /* Data DAC0 Register */
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#define SAM_DAC_DATA1_OFFSET 0x0012 /* Data DAC1 Register */
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#define SAM_DAC_DATABUF0_OFFSET 0x0014 /* Data Buffer DAC0 Register */
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#define SAM_DAC_DATABUF1_OFFSET 0x0016 /* Data Buffer DAC1 Register */
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#define SAM_DAC_DBCTRL_OFFSET 0x0017 /* Debug Control Register */
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/* DAC register addresses ******************************************************************/
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#define SAM_DAC_CTRLA (SAM_DAC_BASE+SAM_DAC_CTRLA_OFFSET)
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#define SAM_DAC_CTRLB (SAM_DAC_BASE+SAM_DAC_CTRLB_OFFSET)
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#define SAM_DAC_EVCTRL (SAM_DAC_BASE+SAM_DAC_EVCTRL_OFFSET)
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#define SAM_DAC_INTENCLR (SAM_DAC_BASE+SAM_DAC_INTENCLR_OFFSET)
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#define SAM_DAC_INTENSET (SAM_DAC_BASE+SAM_DAC_INTENSET_OFFSET)
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#define SAM_DAC_INTFLAG (SAM_DAC_BASE+SAM_DAC_INTFLAG_OFFSET)
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#define SAM_DAC_STATUS (SAM_DAC_BASE+SAM_DAC_STATUS_OFFSET)
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#define SAM_DAC_SYNCBUSY (SAM_DAC_BASE+SAM_DAC_SYNCBUSY_OFFSET)
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#define SAM_DAC_DACCTRL0 (SAM_DAC_BASE+SAM_DAC_DACCTRL0_OFFSET)
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#define SAM_DAC_DACCTRL1 (SAM_DAC_BASE+SAM_DAC_DACCTRL1_OFFSET)
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#define SAM_DAC_DATA0 (SAM_DAC_BASE+SAM_DAC_DATA0_OFFSET)
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#define SAM_DAC_DATA1 (SAM_DAC_BASE+SAM_DAC_DATA1_OFFSET)
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#define SAM_DAC_DATABUF0 (SAM_DAC_BASE+SAM_DAC_DATABUF0_OFFSET)
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#define SAM_DAC_DATABUF1 (SAM_DAC_BASE+SAM_DAC_DATABUF1_OFFSET)
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#define SAM_DAC_DBCTRL (SAM_DAC_BASE+SAM_DAC_DBCTRL_OFFSET)
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/* DAC register bit definitions ************************************************************/
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/* Control A Register */
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#define DAC_CTRLA_SWRTS (1 << 0) /* Bit 0: Software reset */
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#define DAC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable DAC controller */
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/* Control B Register */
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#define DAC_CTRLB_DIFF (1 << 0) /* Bit 0: Differential mode enable */
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#define DAC_CTRLB_REFSEL_SHIFT (1) /* Bit 1-2: Reference selection */
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#define DAC_CTRLB_REFSEL_MASK (3 << DAC_CTRLB_REFSEL_SHIFT)
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# define DAC_CTRLB_REFSEL_VREFAU (0 << DAC_CTRLB_REFSEL_SHIFT) /* Unbuffered external voltage reference */
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# define DAC_CTRLB_REFSEL_VDDANA (1 << DAC_CTRLB_REFSEL_SHIFT) /* Voltage supply */
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# define DAC_CTRLB_REFSEL_VREFAB (2 << DAC_CTRLB_REFSEL_SHIFT) /* Buffered external voltage reference */
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# define DAC_CTRLB_REFSEL_INTREF (3 << DAC_CTRLB_REFSEL_SHIFT) /* Internal bandgap reference */
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/* Event Control Register */
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#define DAC_EVCTRL_STARTEI0 (1 << 0) /* Bit 0: Start conversion event input DAC0 */
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#define DAC_EVCTRL_STARTEI1 (1 << 1) /* Bit 1: Start conversion event input DAC1 */
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#define DAC_EVCTRL_EMTPYEO0 (1 << 2) /* Bit 2: Data buffer empty event output DAC0 */
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#define DAC_EVCTRL_EMTPYEO1 (1 << 3) /* Bit 3: Data buffer empty event output DAC1 */
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#define DAC_EVCTRL_INVEI0 (1 << 4) /* Bit 4: Enable inversion of DAC0 input event */
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#define DAC_EVCTRL_INVEI1 (1 << 5) /* Bit 5: Enable inversion of DAC1 input event */
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/* Common bit definitions for Interrupt Enable Clear Register, Interrupt Enable Set
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* Register, and Interrupt Flag Status and Clear Register
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*/
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#define DAC_INT_UNDERRUN0 (1 << 0) /* Bit 0: Underrun interrupt for DAC2 */
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#define DAC_INT_UNDERRUN1 (1 << 1) /* Bit 1: Underrun interrupt for DAC1 */
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#define DAC_INT_EMPTY0 (1 << 2) /* Bit 2: Data buffer 0 empty interrupt */
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#define DAC_INT_EMPTY1 (1 << 3) /* Bit 3: Data buffer 1 empty interrupt */
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#define DAC_INT_ALL 0x0f
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/* Status Register */
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#define DAC_STATUS_READY0 (1 << 0) /* Bit 0: DAC0 startup ready */
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#define DAC_STATUS_READY1 (1 << 1) /* Bit 1: DAC1 startup ready */
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#define DAC_STATUS_EOC0 (1 << 2) /* Bit 2: DAC0 end of conversion */
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#define DAC_STATUS_EOC1 (1 << 3) /* Bit 3: DAC1 end of conversion */
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/* Synchronization Busy Register */
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#define DAC_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset */
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#define DAC_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: DAC enable status */
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#define DAC_SYNCBUSY_DATA0 (1 << 2) /* Bit 2: Data DAC0 */
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#define DAC_SYNCBUSY_DATA1 (1 << 3) /* Bit 3: Data DAC1 */
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#define DAC_SYNCBUSY_DATABUF0 (1 << 4) /* Bit 4: Data buffer DAC0 */
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#define DAC_SYNCBUSY_DATABUF1 (1 << 5) /* Bit 5: Data buffer DAC1 */
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/* DAC0/1 Control Register */
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#define DAC_DACCTRL_LEFTADJ (1 << 0) /* Bit 0: Left adjusted data */
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#define DAC_DACCTRL_ENABLE (1 << 1) /* Bit 1: Enable DAC */
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#define DAC_DACCTRL_CCTRL_SHIFT (2) /* Bit 2-3: Current control */
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#define DAC_DACCTRL_CCTRL_MASK (3 << DAC_DACCTRL_CCTRL_SHIFT)
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# define DAC_DACCTRL_CCTRL_CC100K (0 << DAC_DACCTRL_CCTRL_SHIFT) /* GCLK_DAC <= 1.2MHz */
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# define DAC_DACCTRL_CCTRL_CC1M (1 << DAC_DACCTRL_CCTRL_SHIFT) /* 1.2MHz < GCLK_DAC <= 6MHz */
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# define DAC_DACCTRL_CCTRL_CC2M (2 << DAC_DACCTRL_CCTRL_SHIFT) /* 6MHz < GCLK_DAC <= 12MHz */
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#define DAC_DACCTRL_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
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#define DAC_DACCTRL_DITHER (1 << 7) /* Bit 7: Dithering mode */
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#define DAC_DACCTRL_REFRESH_SHIFT (8) /* Bit 8-11: Refresh period */
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#define DAC_DACCTRL_REFRESH_MASK (15 << DAC_DACCTRL_REFRESH_SHIFT)
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# define DAC_DACCTRL_REFRESH(n) ((uin16_t)(n) << DAC_DACCTRL_REFRESH_SHIFT)
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/* Data DAC0/1 Register (16-bit data) */
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/* Data Buffer DAC0/1 Register (16-bit data) */
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/* Debug Control Register */
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#define DAC_DBCTRL_DBGRUN (1 << 0) /* Bit 0: Debug run */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAML21 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAML_DAC_H */
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