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Merged in raiden00/nuttx (pull request #405)

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stm32_hrtim

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Mateusz Szafoni 2017-06-17 20:30:40 +00:00 committed by Gregory Nutt
commit ede54bc4a0
3 changed files with 1281 additions and 115 deletions
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13
arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h
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@ -108,7 +108,7 @@
#define STM32_HRTIM_CMN_ICR_OFFSET 0x000C /* HRTIM Interrupt Clear Register */
#define STM32_HRTIM_CMN_IER_OFFSET 0x0010 /* HRTIM Interrupt Enable Register */
#define STM32_HRTIM_CMN_OENR_OFFSET 0x0014 /* HRTIM Output Enable Register */
#define STM32_HRTIM_CMN_DISR_OFFSET 0x0018 /* HRTIM Output Disable Register */
#define STM32_HRTIM_CMN_ODISR_OFFSET 0x0018 /* HRTIM Output Disable Register */
#define STM32_HRTIM_CMN_ODSR_OFFSET 0x001C /* HRTIM Output Disable Status Register */
#define STM32_HRTIM_CMN_BMCR_OFFSET 0x0020 /* HRTIM Burst Mode Control Register */
#define STM32_HRTIM_CMN_BMTRGR_OFFSET 0x0024 /* HRTIM Burst Mode Trigger Register */
@ -1136,11 +1136,12 @@
/* Timer X Fault Register */
#define HRTIM_TIMFLT_FLT1EN (1 << 0) /* Bit 0 */
#define HRTIM_TIMFLT_FLT2EN (1 << 1) /* Bit 1 */
#define HRTIM_TIMFLT_FLT3EN (1 << 2) /* Bit 2 */
#define HRTIM_TIMFLT_FLT4EN (1 << 3) /* Bit 3 */
#define HRTIM_TIMFLT_FLT5EN (1 << 4) /* Bit 4 */
#define HRTIM_TIMFLT_FLT1EN (1 << 0) /* Bit 0: Fault1 enable */
#define HRTIM_TIMFLT_FLT2EN (1 << 1) /* Bit 1: Fault 2 enable */
#define HRTIM_TIMFLT_FLT3EN (1 << 2) /* Bit 2: Fault 3 enable*/
#define HRTIM_TIMFLT_FLT4EN (1 << 3) /* Bit 3: Fault 4 enable */
#define HRTIM_TIMFLT_FLT5EN (1 << 4) /* Bit 4: Fault 5 enable */
#define HRTIM_TIMFLT_FLTLCK (1 << 31) /* Bit 31: Fault sources lock*/
/* Common Control Register 1 */

1140
arch/arm/src/stm32/stm32_hrtim.c
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File diff suppressed because it is too large Load Diff

243
arch/arm/src/stm32/stm32_hrtim.h
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@ -64,22 +64,23 @@
enum stm32_hrtim_tim_e
{
HRTIM_TIMER_MASTER,
HRTIM_TIMER_MASTER = 0,
#ifdef CONFIG_STM32_HRTIM_TIMA
HRTIM_TIMER_TIMA,
HRTIM_TIMER_TIMA = 1,
#endif
#ifdef CONFIG_STM32_HRTIM_TIMB
HRTIM_TIMER_TIMB,
HRTIM_TIMER_TIMB = 2,
#endif
#ifdef CONFIG_STM32_HRTIM_TIMC
HRTIM_TIMER_TIMC,
HRTIM_TIMER_TIMC = 3,
#endif
#ifdef CONFIG_STM32_HRTIM_TIMD
HRTIM_TIMER_TIMD,
HRTIM_TIMER_TIMD = 4,
#endif
#ifdef CONFIG_STM32_HRTIM_TIME
HRTIM_TIMER_TIME,
HRTIM_TIMER_TIME = 5,
#endif
HRTIM_TIMER_COMMON = 6
};
/* Source which can force the Tx1/Tx2 output to its inactive state */
@ -117,7 +118,7 @@ enum stm32_hrtim_out_rst_e
HRTIM_OUT_RST_CMP1 = (1 << 28),
HRTIM_OUT_RST_PER = (1 << 29),
HRTIM_OUT_RST_RESYNC = (1 << 30),
HRTIM_OUT_RST_SOFT = (1 << 31),
HRTIM_OUT_RST_SOFT = (1 << 31)
};
/* Source which can force the Tx1/Tx2 output to its active state */
@ -155,7 +156,7 @@ enum stm32_hrtim_out_set_e
HRTIM_OUT_SET_CMP1 = (1 << 28),
HRTIM_OUT_SET_PER = (1 << 29),
HRTIM_OUT_SET_RESYNC = (1 << 30),
HRTIM_OUT_SET_SOFT = (1 << 31),
HRTIM_OUT_SET_SOFT = (1 << 31)
};
/* Events that can reset TimerX Counter */
@ -205,7 +206,7 @@ enum stm32_hrtim_tim_rst_e
HRTIM_RST_EXTEVNT4,
HRTIM_RST_EXTEVNT3,
HRTIM_RST_EXTEVNT2,
HRTIM_RST_EXTEVNT1,
HRTIM_RST_EXTEVNT1
};
/* HRTIM Timer X prescaler */
@ -219,41 +220,243 @@ enum stm32_hrtim_tim_prescaler_e
HRTIM_PRESCALER_16,
HRTIM_PRESCALER_32,
HRTIM_PRESCALER_64,
HRTIM_PRESCALER_128,
HRTIM_PRESCALER_128
};
/* HRTIM Slave Timer fault sources Lock */
enum stm32_hrtim_tim_fault_lock_e
{
HRTIM_TIM_FAULT_RW = 0, /* Slave Timer fault source are read/write */
HRTIM_TIM_FAULT_LOCK = (1 << 7) /* Slave Timer fault source are read only */
};
/* HRTIM Slave Timer Fault configuration */
enum stm32_hrtim_tim_fault_src_e
{
HRTIM_TIM_FAULT1 = (1 << 0),
HRTIM_TIM_FAULT2 = (1 << 2),
HRTIM_TIM_FAULT3 = (1 << 3),
HRTIM_TIM_FAULT4 = (1 << 4),
HRTIM_TIM_FAULT5 = (1 << 5)
};
/* HRTIM Fault Source */
enum stm32_hrtim_fault_src_e
{
HRTIM_FAULT_SRC_PIN,
HRTIM_FAULT_SRC_INTERNAL
HRTIM_FAULT_SRC_PIN = 0,
HRTIM_FAULT_SRC_INTERNAL = 1
};
/* HRTIM External Event Source
* NOTE: according to Table 82 from STM32F334XX Manual
* NOTE: according to Table 82 from STM32F334XX Manual.
*/
enum stm32_hrtim_eev_src_e
{
HRTIM_EEV_SRC_PIN,
HRTIM_EEV_SRC_ANALOG,
HRTIM_EEV_SRC_TRGO,
HRTIM_EEV_SRC_ADC
HRTIM_EEV_SRC_PIN = 0,
HRTIM_EEV_SRC_ANALOG = 1,
HRTIM_EEV_SRC_TRGO = 2,
HRTIM_EEV_SRC_ADC = 3
};
/* HRTIM Fault Polarity */
enum stm32_hrtim_fault_pol_e
{
HRTIM_FAULT_POL_LOW = 0,
HRTIM_FAULT_POL_HIGH = 1
};
/* HRTIM External Event Polarity */
enum stm32_hrtim_eev_pol_e
{
HRTIM_EEV_POL_HIGH = 0, /* External Event is active high */
HRTIM_EEV_POL_LOW = 1 /* External Event is active low */
};
/* HRTIM External Event sensitivity */
enum stm32_hrtim_eev_sen_e
{
HRTIM_EEV_SEN_LEVEL = 0, /* On active level defined by polarity */
HRTIM_EEV_SEN_RISING = 1, /* Rising edgne */
HRTIM_EEV_SEN_FALLING = 2, /* Falling edge */
HRTIM_EEV_SEN_BOTH = 3 /* Both edges */
};
/* External Event Sampling clock division */
enum stm32_hrtim_eev_sampling_e
{
HRTIM_EEV_SAMPLING_d1 = 0,
HRTIM_EEV_SAMPLING_d2 = 1,
HRTIM_EEV_SAMPLING_d4 = 2,
HRTIM_EEV_SAMPLING_d8 = 3
};
/* HRTIM External Event Mode.
* NOTE: supported only for EEV1-5.
*/
enum stm32_hrtim_eev_mode_e
{
HRTIM_EEV_MODE_NORMAL = 0,
HRTIM_EEV_MODE_FAST = 1 /* low latency mode */
};
/* External Event filter.
* NOTE: supported only for EEV6-10.
*/
enum stm32_hrtim_eev_filter_e
{
HRTIM_EEV_DISABLE = 0,
HRTIM_EEV_HRT_N2 = 1,
HRTIM_EEV_HRT_N4 = 2,
HRTIM_EEV_HRT_N8 = 3,
HRTIM_EEV_EEVSd2_N6 = 4,
HRTIM_EEV_EEVSd2_N8 = 5,
HRTIM_EEV_EEVSd4_N6 = 6,
HRTIM_EEV_EEVSd4_N8 = 7,
HRTIM_EEV_EEVSd8_N6 = 8,
HRTIM_EEV_EEVSd8_N8 = 9,
HRTIM_EEV_EEVSd16_N5 = 10,
HRTIM_EEV_EEVSd16_N6 = 11,
HRTIM_EEV_EEVSd16_N8 = 12,
HRTIM_EEV_EEVSd32_N5 = 13,
HRTIM_EEV_EEVSd32_N6 = 14,
HRTIM_EEV_EEVSd32_N8 = 15
};
/* Compare register index */
enum stm32_hrtim_cmp_index_e
{
HRTIM_CMP1,
HRTIM_CMP2,
HRTIM_CMP3,
HRTIM_CMP4
};
/* HRTIM Slave Timer Outputs */
enum stm32_outputs_e
{
HRTIM_OUT_TIMA_CH1 = (1 << 0),
HRTIM_OUT_TIMA_CH2 = (1 << 1),
HRTIM_OUT_TIMB_CH1 = (1 << 2),
HRTIM_OUT_TIMB_CH2 = (1 << 3),
HRTIM_OUT_TIMC_CH1 = (1 << 4),
HRTIM_OUT_TIMC_CH2 = (1 << 5),
HRTIM_OUT_TIMD_CH1 = (1 << 6),
HRTIM_OUT_TIMD_CH2 = (1 << 7),
HRTIM_OUT_TIME_CH1 = (1 << 8),
HRTIM_OUT_TIME_CH2 = (1 << 9)
};
/* DAC synchronization event */
enum stm32_hrtim_dacsync_e
{
HRTIM_DACSYNC_DIS,
HRTIM_DACSYNC_1,
HRTIM_DACSYNC_2,
HRTIM_DACSYNC_3
};
/* HRTIM Deadtime Locks */
enum stm32_deadtime_lock_e
{
HRTIM_DT_VALUE_LOCK = (1 << 0), /* Lock Deadtime value */
HRTIM_DT_SIGN_LOCK = (1 << 1) /* Lock Deadtime sign */
};
/* HRTIM Deadtime types */
enum stm32_deadtime_edge_e
{
HRTIM_DT_RISING = 0,
HRTIM_DT_FALLING = 1
};
/* Chopper start pulsewidth */
enum stm32_chopper_start_e
{
HRTIM_CHP_START_16,
HRTIM_CHP_START_32,
HRTIM_CHP_START_48,
HRTIM_CHP_START_64,
HRTIM_CHP_START_80,
HRTIM_CHP_START_96,
HRTIM_CHP_START_112,
HRTIM_CHP_START_128,
HRTIM_CHP_START_144,
HRTIM_CHP_START_160,
HRTIM_CHP_START_176,
HRTIM_CHP_START_192,
HRTIM_CHP_START_208,
HRTIM_CHP_START_224,
HRTIM_CHP_START_256
};
/* Chopper duty cycle */
enum stm32_chopper_duty_e
{
HRTIM_CHP_DUTY_0,
HRTIM_CHP_DUTY_1,
HRTIM_CHP_DUTY_2,
HRTIM_CHP_DUTY_3,
HRTIM_CHP_DUTY_4,
HRTIM_CHP_DUTY_5,
HRTIM_CHP_DUTY_6,
HRTIM_CHP_DUTY_7
};
/* Chopper carrier frequency */
enum stm32_chopper_freq_e
{
HRTIM_CHP_FREQ_d16,
HRTIM_CHP_FREQ_d32,
HRTIM_CHP_FREQ_d48,
HRTIM_CHP_FREQ_d64,
HRTIM_CHP_FREQ_d80,
HRTIM_CHP_FREQ_d96,
HRTIM_CHP_FREQ_d112,
HRTIM_CHP_FREQ_d128,
HRTIM_CHP_FREQ_d144,
HRTIM_CHP_FREQ_d160,
HRTIM_CHP_FREQ_d176,
HRTIM_CHP_FREQ_d192,
HRTIM_CHP_FREQ_d208,
HRTIM_CHP_FREQ_d224,
HRTIM_CHP_FREQ_d240,
HRTIM_CHP_FREQ_d256
};
/* */
struct hrtim_dev_s
{
#ifdef CONFIG_HRTIM
/* Fields managed by common upper half HRTIM logic */
uint8_t hd_ocount; /* The number of times the device has been opened */
sem_t hd_closesem; /* Locks out new opens while close is in progress */
uint8_t hd_ocount; /* The number of times the device has been opened */
sem_t hd_closesem; /* Locks out new opens while close is in progress */
#endif
/* Fields provided by lower half HRTIM logic */
FAR void *hd_priv; /* Used by the arch-specific logic */
FAR void *hd_priv; /* Used by the arch-specific logic */
bool initialized; /* true: HRTIM driver has been initialized */
};
/************************************************************************************