From 96d40dec4066f5e174ad43f0ec7b875f2e958977 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 15 Jun 2017 11:20:40 +0200 Subject: [PATCH 1/5] stm32_hrtim: cosmetic --- arch/arm/src/stm32/stm32_hrtim.c | 75 ++++++++++++++++---------------- 1 file changed, 38 insertions(+), 37 deletions(-) diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c index a99f37fc5f..c2b65b023f 100644 --- a/arch/arm/src/stm32/stm32_hrtim.c +++ b/arch/arm/src/stm32/stm32_hrtim.c @@ -168,7 +168,7 @@ #ifdef HRTIM_HAVE_PWM -/* HRTIM TimerX Single Output Set/Reset Configuration */ +/* HRTIM Slave Timer Single Output Set/Reset Configuration */ struct stm32_hrtim_timout_s { @@ -176,7 +176,7 @@ struct stm32_hrtim_timout_s uint32_t rst; /* Reset events*/ }; -/* HRTIM TimerX Output Chopper Configuration */ +/* HRTIM Slave Timer Chopper Configuration */ #ifdef HRTIM_HAVE_CHOPPER struct stm32_hrtim_chopper_s @@ -185,7 +185,7 @@ struct stm32_hrtim_chopper_s }; #endif -/* HRTIM TimerX Output Deadtime Configuration*/ +/* HRTIM Slave Timer Deadtime Configuration */ #ifdef HRTIM_HAVE_DEADTIME struct stm32_hrtim_deadtime_s @@ -251,6 +251,7 @@ struct stm32_hrtim_master_priv_s struct stm32_hrtim_slave_priv_s { + uint16_t update; /* Update configuration */ uint32_t reset; /* Timer reset events */ #ifdef HRTIM_HAVE_PWM struct stm32_hrtim_pwm_s pwm; /* PWM configuration */ @@ -396,22 +397,22 @@ static void hrtim_putreg(FAR struct stm32_hrtim_s *priv, int offset, uint32_t value); static void hrtim_modifyreg(FAR struct stm32_hrtim_s *priv, int offset, uint32_t clrbits, uint32_t setbits); -static void hrtim_tim_putreg(FAR struct stm32_hrtim_s *priv, uint8_t index, +static void hrtim_tim_putreg(FAR struct stm32_hrtim_s *priv, uint8_t timer, int offset, uint32_t value); -static void hrtim_tim_modifyreg(FAR struct stm32_hrtim_s *priv, uint8_t index, +static void hrtim_tim_modifyreg(FAR struct stm32_hrtim_s *priv, uint8_t timer, int offset, uint32_t clrbits, uint32_t setbits); /* HRTIM helper */ -static uint32_t hrtim_tim_getreg(FAR struct stm32_hrtim_s *priv, uint8_t index, +static uint32_t hrtim_tim_getreg(FAR struct stm32_hrtim_s *priv, uint8_t timer, int offset); static FAR struct stm32_hrtim_tim_s *hrtim_tim_get(FAR struct stm32_hrtim_s *priv, - uint8_t index); + uint8_t timer); /* Configuration */ static int hrtim_dll_cal(FAR struct stm32_hrtim_s *priv); -static int hrtim_tim_clock_config(FAR struct stm32_hrtim_s *priv, uint8_t index, +static int hrtim_tim_clock_config(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint8_t pre); static int hrtim_tim_clocks_config(FAR struct stm32_hrtim_s *priv); #if defined(HRTIM_HAVE_CAPTURE) || defined(HRTIM_HAVE_PWM) || defined(HRTIM_HAVE_SYNC) @@ -753,18 +754,18 @@ static void hrtim_modifyreg(FAR struct stm32_hrtim_s *priv, int offset, * * Input Parameters: * priv - A reference to the HRTIM block - * index - An HRTIM Timer index to get + * timer - An HRTIM Timer index to get * * Returned Value: - * Base adress offset for given timer index + * Base adress offset for given Timer index * ****************************************************************************/ -static FAR struct stm32_hrtim_tim_s *hrtim_tim_get(FAR struct stm32_hrtim_s *priv, uint8_t index) +static FAR struct stm32_hrtim_tim_s *hrtim_tim_get(FAR struct stm32_hrtim_s *priv, uint8_t timer) { FAR struct stm32_hrtim_tim_s *tim; - switch (index) + switch (timer) { case HRTIM_TIMER_MASTER: { @@ -814,7 +815,7 @@ static FAR struct stm32_hrtim_tim_s *hrtim_tim_get(FAR struct stm32_hrtim_s *pri default: { - tmrerr("ERROR: No such timerx index: %d\n", index); + tmrerr("ERROR: No such timer index: %d\n", timer); tim = NULL; } } @@ -830,19 +831,19 @@ static FAR struct stm32_hrtim_tim_s *hrtim_tim_get(FAR struct stm32_hrtim_s *pri * * Input Parameters: * priv - A reference to the HRTIM block - * index - An HRTIM Timer index to get + * timer - An HRTIM Timer index to get * * Returned Value: - * Base adress offset for given timer index + * Base adress offset for given Timer index * ****************************************************************************/ -static uint32_t hrtim_base_get(FAR struct stm32_hrtim_s* priv, uint8_t index) +static uint32_t hrtim_base_get(FAR struct stm32_hrtim_s* priv, uint8_t timer) { FAR struct stm32_hrtim_tim_s* tim; uint32_t base; - tim = hrtim_tim_get(priv,index); + tim = hrtim_tim_get(priv,timer); if (tim == NULL) { base = 0; @@ -871,12 +872,12 @@ errout: * ****************************************************************************/ -static uint32_t hrtim_tim_getreg(FAR struct stm32_hrtim_s *priv, uint8_t index, +static uint32_t hrtim_tim_getreg(FAR struct stm32_hrtim_s *priv, uint8_t timer, int offset) { uint32_t base; - base = hrtim_base_get(priv, index); + base = hrtim_base_get(priv, timer); if (base < 0) { return 0; @@ -893,7 +894,7 @@ static uint32_t hrtim_tim_getreg(FAR struct stm32_hrtim_s *priv, uint8_t index, * * Input Parameters: * priv - A reference to the HRTIM block - * index - An HRTIM timer index + * timer - An HRTIM Timer index * offset - The offset to the register to write to * value - The value to write to the register * @@ -902,12 +903,12 @@ static uint32_t hrtim_tim_getreg(FAR struct stm32_hrtim_s *priv, uint8_t index, * ****************************************************************************/ -static void hrtim_tim_putreg(FAR struct stm32_hrtim_s *priv, uint8_t index, +static void hrtim_tim_putreg(FAR struct stm32_hrtim_s *priv, uint8_t timer, int offset, uint32_t value) { uint32_t base; - base = hrtim_base_get(priv, index); + base = hrtim_base_get(priv, timer); if (base > 0) { putreg32(value, base + offset); @@ -922,7 +923,7 @@ static void hrtim_tim_putreg(FAR struct stm32_hrtim_s *priv, uint8_t index, * * Input Parameters: * priv - A reference to the HRTIM block - * index - An HRTIM timer index + * timer - An HRTIM Timer index * offset - The offset to the register to modify * clrbits - The bits to clear * setbits - The bits to set @@ -932,11 +933,11 @@ static void hrtim_tim_putreg(FAR struct stm32_hrtim_s *priv, uint8_t index, * ****************************************************************************/ -static void hrtim_tim_modifyreg(FAR struct stm32_hrtim_s *priv, uint8_t index, +static void hrtim_tim_modifyreg(FAR struct stm32_hrtim_s *priv, uint8_t timer, int offset, uint32_t clrbits, uint32_t setbits) { - hrtim_tim_putreg(priv, index, offset, - (hrtim_tim_getreg(priv, index, offset) & ~clrbits) | setbits); + hrtim_tim_putreg(priv, timer, offset, + (hrtim_tim_getreg(priv, timer, offset) & ~clrbits) | setbits); } /**************************************************************************** @@ -990,19 +991,19 @@ static int hrtim_dll_cal(FAR struct stm32_hrtim_s *priv) * * Input Parameters: * priv - A reference to the HRTIM structure - * index - An HRTIM timer index + * timer - An HRTIM Timer index * * Returned Value: * 0 on success, a negated errno value on failure * ****************************************************************************/ -static int hrtim_tim_clock_config(FAR struct stm32_hrtim_s *priv, uint8_t index, uint8_t pre) +static int hrtim_tim_clock_config(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint8_t pre) { int ret = OK; uint32_t regval = 0; - regval = hrtim_tim_getreg(priv, index, STM32_HRTIM_TIM_CR_OFFSET); + regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET); switch (pre) { @@ -1048,7 +1049,7 @@ static int hrtim_tim_clock_config(FAR struct stm32_hrtim_s *priv, uint8_t index, } default: { - tmrerr("ERROR: invalid prescaler value %d for timer %d\n", index, + tmrerr("ERROR: invalid prescaler value %d for timer %d\n", timer, pre); ret = -EINVAL; goto errout; @@ -1404,7 +1405,7 @@ static int hrtim_synch_config(FAR struct stm32_hrtim_s *priv) ****************************************************************************/ #if defined(HRTIM_HAVE_PWM) -static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t index) +static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t timer) { FAR struct stm32_hrtim_tim_s* tim; FAR struct stm32_hrtim_slave_priv_s* slave; @@ -1414,7 +1415,7 @@ static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t inde /* Master Timer has no outputs */ - if (index == HRTIM_TIMER_MASTER) + if (timer == HRTIM_TIMER_MASTER) { ret = -EINVAL; goto errout; @@ -1422,7 +1423,7 @@ static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t inde /* Get Timer data strucutre */ - tim = hrtim_tim_get(priv, index); + tim = hrtim_tim_get(priv, timer); if (tim == NULL) { ret = -EINVAL; @@ -1434,22 +1435,22 @@ static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t inde /* Configure CH1 SET events */ regval = slave->pwm.ch1.set; - hrtim_tim_putreg(priv, index, STM32_HRTIM_TIM_SET1R_OFFSET, regval); + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_SET1R_OFFSET, regval); /* Configure CH1 RESET events */ regval = slave->pwm.ch1.rst; - hrtim_tim_putreg(priv, index, STM32_HRTIM_TIM_RST1R_OFFSET, regval); + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RST1R_OFFSET, regval); /* Configure CH2 SET events */ regval = slave->pwm.ch2.set; - hrtim_tim_putreg(priv, index, STM32_HRTIM_TIM_SET2R_OFFSET, regval); + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_SET2R_OFFSET, regval); /* Configure CH2 RESET events */ regval = slave->pwm.ch2.rst; - hrtim_tim_putreg(priv, index, STM32_HRTIM_TIM_RST2R_OFFSET, regval); + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RST2R_OFFSET, regval); errout: return ret; From 268c6d0b7d53fef8ae3aab0552c73b9ab2e5c4e7 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 15 Jun 2017 16:45:21 +0200 Subject: [PATCH 2/5] stm32_hrtim: outputs enable, period and compare functions, cosmetics --- arch/arm/src/stm32/stm32_hrtim.c | 237 +++++++++++++++++++++++++++++-- arch/arm/src/stm32/stm32_hrtim.h | 40 +++++- 2 files changed, 256 insertions(+), 21 deletions(-) diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c index c2b65b023f..bb96c53274 100644 --- a/arch/arm/src/stm32/stm32_hrtim.c +++ b/arch/arm/src/stm32/stm32_hrtim.c @@ -222,9 +222,7 @@ struct stm32_hrtim_capture_s struct stm32_hrtim_timcmn_s { - uint16_t cmp[4]; /* Compare registers */ uint32_t base; /* The base adress of the timer */ - uint32_t frequency; /* Current frequency setting */ uint32_t pclk; /* The frequency of the peripheral clock * that drives the timer module */ #ifdef CONFIG_STM32_HRTIM_DMA @@ -408,6 +406,7 @@ static uint32_t hrtim_tim_getreg(FAR struct stm32_hrtim_s *priv, uint8_t timer, int offset); static FAR struct stm32_hrtim_tim_s *hrtim_tim_get(FAR struct stm32_hrtim_s *priv, uint8_t timer); +static uint32_t hrtim_base_get(FAR struct stm32_hrtim_s* priv, uint8_t timer); /* Configuration */ @@ -440,6 +439,14 @@ static int hrtim_eev_config(FAR struct stm32_hrtim_s *priv); #ifdef HRTIM_HAVE_INTERRUPTS static int hrtim_irq_config(FAR struct stm32_hrtim_s *priv); #endif +static int hrtim_cmp_update(FAR struct stm32_hrtim_s *priv, uint8_t timer, + uint8_t index, uint16_t cmp); +static int hrtim_per_update(FAR struct stm32_hrtim_s *priv, uint8_t timer, + uint16_t per); +static uint16_t hrtim_per_get(FAR struct stm32_hrtim_s *priv, uint8_t timer); +static uint16_t hrtim_cmp_get(FAR struct stm32_hrtim_s *priv, uint8_t timer, + uint8_t index); + /* Initialization */ @@ -941,7 +948,7 @@ static void hrtim_tim_modifyreg(FAR struct stm32_hrtim_s *priv, uint8_t timer, } /**************************************************************************** - * Name: stm32_dll_cal + * Name: hrtim_dll_cal * * Description: * Calibrate HRTIM DLL @@ -984,7 +991,7 @@ static int hrtim_dll_cal(FAR struct stm32_hrtim_s *priv) } /**************************************************************************** - * Name: stm32_tim_clock_config + * Name: hrtim_tim_clock_config * * Description: * Configure HRTIM Timer clock @@ -1061,7 +1068,7 @@ errout: } /**************************************************************************** - * Name: stm32_tim_clocks_config + * Name: hrtim_tim_clocks_config * * Description: * Configure HRTIM Timers Clocks @@ -1141,7 +1148,7 @@ errout: } /**************************************************************************** - * Name: stm32_gpios_config + * Name: hrtim_gpios_config * * Description: * Configure HRTIM GPIO @@ -1339,7 +1346,7 @@ static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv) #endif /**************************************************************************** - * Name: stm32_inputs_config + * Name: hrtim_inputs_config * * Description: * Configure HRTIM Inputs @@ -1369,7 +1376,7 @@ static int hrtim_inputs_config(FAR struct stm32_hrtim_s *priv) /**************************************************************************** - * Name: stm32_synch_config + * Name: hrtim_synch_config * * Description: * Configure HRTIM Synchronization Input/Output @@ -1391,7 +1398,7 @@ static int hrtim_synch_config(FAR struct stm32_hrtim_s *priv) #endif /**************************************************************************** - * Name: stm32_tim_outputs_config + * Name: hrtim_tim_outputs_config * * Description: * Configure HRTIM Slave Timer Outputs (CH1 and CH2) @@ -1458,7 +1465,7 @@ errout: #endif /**************************************************************************** - * Name: stm32_outputs_config + * Name: hrtim_outputs_config * * Description: * Configure HRTIM Outputs @@ -1529,10 +1536,50 @@ static int hrtim_outputs_config(FAR struct stm32_hrtim_s *priv) errout: return ret; } + +/**************************************************************************** + * Name: hrtim_outputs_enable + * + * Description: + * Enable/disable HRTIM outputs (bulk operation) + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * outputs - outputs to set + * state - Enable/disable operation + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_outputs_enable(FAR struct stm32_hrtim_s *priv, uint16_t outputs, + bool state) +{ + uint32_t reg = 0; + + /* Get register offset */ + + if (state == true) + { + reg = STM32_HRTIM_CMN_OENR_OFFSET; + } + else + { + reg = STM32_HRTIM_CMN_ODISR_OFFSET; + } + + /* Write register */ + + hrtim_putreg(priv, reg, outputs); + + return OK; +} + #endif /**************************************************************************** - * Name: stm32_adc_config + * Name: hrtim_adc_config * * Description: * Configure HRTIM ADC triggers @@ -1554,7 +1601,7 @@ static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv) #endif /**************************************************************************** - * Name: stm32_faults_config + * Name: hrtim_faults_config * * Description: * Configure HRTIM Faults @@ -1576,7 +1623,7 @@ static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv) #endif /**************************************************************************** - * Name: stm32_eev_config + * Name: hrtim_eev_config * * Description: * Configure HRTIM External Events @@ -1598,7 +1645,7 @@ static int hrtim_eev_config(FAR struct stm32_hrtim_s *priv) #endif /**************************************************************************** - * Name: stm32_irq_config + * Name: hrtim_irq_config * * Description: * Configure HRTIM interrupts @@ -1620,7 +1667,7 @@ static int hrtim_irq_config(FAR struct stm32_hrtim_s *priv) #endif /**************************************************************************** - * Name: stm32_preload_config + * Name: hrtim_preload_config * * Description: * Configure HRTIM preload registers @@ -1668,6 +1715,165 @@ static void hrtim_preload_config(FAR struct stm32_hrtim_s *priv) } +/**************************************************************************** + * Name: hrtim_cmp_update + * + * Description: + * Try update HRTIM Timer compare register. + * + * Input parameters: + * priv - A reference to the HRTIM block + * timer - HRTIM Timer timer + * index - Compare register timer + * cmp - New compare register value + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_cmp_update(FAR struct stm32_hrtim_s *priv, uint8_t timer, + uint8_t index, uint16_t cmp) +{ + int ret = OK; + uint32_t offset = 0; + + switch (cmp) + { + case HRTIM_CMP1: + { + offset = STM32_HRTIM_TIM_CMP1R_OFFSET; + break; + } + case HRTIM_CMP2: + { + offset = STM32_HRTIM_TIM_CMP2R_OFFSET; + break; + } + case HRTIM_CMP3: + { + offset = STM32_HRTIM_TIM_CMP3R_OFFSET; + break; + } + case HRTIM_CMP4: + { + offset = STM32_HRTIM_TIM_CMP4R_OFFSET; + break; + } + default: + { + ret = -EINVAL; + goto errout; + } + } + + hrtim_tim_putreg(priv, timer, offset, cmp); + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_per_update + * + * Description: + * Try update HRTIM Timer period register. + * + * Input parameters: + * priv - A reference to the HRTIM block + * timer - HRTIM Timer timer + * per - New period register value + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_per_update(FAR struct stm32_hrtim_s *priv, uint8_t timer, + uint16_t per) +{ + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET, per); + + return OK; +} + +/**************************************************************************** + * Name: hrtim_per_get + * + * Description: + * Get HRTIM Timer period value + * + * Input parameters: + * priv - A reference to the HRTIM block + * timer - HRTIM Timer timer + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static uint16_t hrtim_per_get(FAR struct stm32_hrtim_s *priv, uint8_t timer) +{ + return (uint16_t)hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_PER_OFFSET); +} + +/**************************************************************************** + * Name: hrtim_cmp_update + * + * Description: + * Get HRTIM Timer compare register + * + * Input parameters: + * priv - A reference to the HRTIM block + * timer - HRTIM Timer timer + * index - Compare register timer + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static uint16_t hrtim_cmp_get(FAR struct stm32_hrtim_s *priv, uint8_t timer, + uint8_t index) +{ + uint16_t cmpx = 0; + uint32_t offset = 0; + + switch (index) + { + case HRTIM_CMP1: + { + offset = STM32_HRTIM_TIM_CMP1R_OFFSET; + break; + } + case HRTIM_CMP2: + { + offset = STM32_HRTIM_TIM_CMP2R_OFFSET; + break; + } + case HRTIM_CMP3: + { + offset = STM32_HRTIM_TIM_CMP3R_OFFSET; + break; + } + case HRTIM_CMP4: + { + offset = STM32_HRTIM_TIM_CMP4R_OFFSET; + break; + } + default: + { + cmpx = 0; + goto errout; + } + } + + cmpx = (uint16_t)hrtim_tim_getreg(priv, timer, offset); + +errout: + return cmpx; +} + /**************************************************************************** * Name: stm32_hrtimconfig * @@ -1856,6 +2062,7 @@ errout: * ****************************************************************************/ + FAR struct hrtim_dev_s* stm32_hrtiminitialize(void) { FAR struct hrtim_dev_s *dev; diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/stm32/stm32_hrtim.h index e20d71e630..8fa0864d47 100644 --- a/arch/arm/src/stm32/stm32_hrtim.h +++ b/arch/arm/src/stm32/stm32_hrtim.h @@ -64,21 +64,21 @@ enum stm32_hrtim_tim_e { - HRTIM_TIMER_MASTER, + HRTIM_TIMER_MASTER = 0, #ifdef CONFIG_STM32_HRTIM_TIMA - HRTIM_TIMER_TIMA, + HRTIM_TIMER_TIMA = 1, #endif #ifdef CONFIG_STM32_HRTIM_TIMB - HRTIM_TIMER_TIMB, + HRTIM_TIMER_TIMB = 2, #endif #ifdef CONFIG_STM32_HRTIM_TIMC - HRTIM_TIMER_TIMC, + HRTIM_TIMER_TIMC = 3, #endif #ifdef CONFIG_STM32_HRTIM_TIMD - HRTIM_TIMER_TIMD, + HRTIM_TIMER_TIMD = 4, #endif #ifdef CONFIG_STM32_HRTIM_TIME - HRTIM_TIMER_TIME, + HRTIM_TIMER_TIME = 5, #endif }; @@ -242,6 +242,34 @@ enum stm32_hrtim_eev_src_e HRTIM_EEV_SRC_ADC }; +/* Compare register index */ + +enum stm32_hrtim_cmp_index_e +{ + HRTIM_CMP1, + HRTIM_CMP2, + HRTIM_CMP3, + HRTIM_CMP4 +}; + +/* HRTIM Slave Timer Outputs */ + +enum stm32_outputs_e +{ + HRTIM_OUT_TIMA_CH1 = (1 << 0), + HRTIM_OUT_TIMA_CH2 = (1 << 1), + HRTIM_OUT_TIMB_CH1 = (1 << 2), + HRTIM_OUT_TIMB_CH2 = (1 << 3), + HRTIM_OUT_TIMC_CH1 = (1 << 4), + HRTIM_OUT_TIMC_CH2 = (1 << 5), + HRTIM_OUT_TIMD_CH1 = (1 << 6), + HRTIM_OUT_TIMD_CH2 = (1 << 7), + HRTIM_OUT_TIME_CH1 = (1 << 8), + HRTIM_OUT_TIME_CH2 = (1 << 9), +}; + +/* */ + struct hrtim_dev_s { #ifdef CONFIG_HRTIM From bd7bee5db0bac6fbb53e06b256c6da2b077cb110 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 16 Jun 2017 10:58:03 +0200 Subject: [PATCH 3/5] stm32_hrtim: structures for deadtime and chopper, cosmetics --- arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h | 2 +- arch/arm/src/stm32/stm32_hrtim.c | 49 +++++++---- arch/arm/src/stm32/stm32_hrtim.h | 90 ++++++++++++++++++++- 3 files changed, 123 insertions(+), 18 deletions(-) diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h index 31438fe30e..65e84afab4 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h @@ -108,7 +108,7 @@ #define STM32_HRTIM_CMN_ICR_OFFSET 0x000C /* HRTIM Interrupt Clear Register */ #define STM32_HRTIM_CMN_IER_OFFSET 0x0010 /* HRTIM Interrupt Enable Register */ #define STM32_HRTIM_CMN_OENR_OFFSET 0x0014 /* HRTIM Output Enable Register */ -#define STM32_HRTIM_CMN_DISR_OFFSET 0x0018 /* HRTIM Output Disable Register */ +#define STM32_HRTIM_CMN_ODISR_OFFSET 0x0018 /* HRTIM Output Disable Register */ #define STM32_HRTIM_CMN_ODSR_OFFSET 0x001C /* HRTIM Output Disable Status Register */ #define STM32_HRTIM_CMN_BMCR_OFFSET 0x0020 /* HRTIM Burst Mode Control Register */ #define STM32_HRTIM_CMN_BMTRGR_OFFSET 0x0024 /* HRTIM Burst Mode Trigger Register */ diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c index bb96c53274..d9f48d31ca 100644 --- a/arch/arm/src/stm32/stm32_hrtim.c +++ b/arch/arm/src/stm32/stm32_hrtim.c @@ -61,6 +61,10 @@ # error HRTIM ADC Triggering not supported yet #endif +#ifdef CONFIG_STM32_HRTIM_DAC +# error HRTIM DAC Triggering not supported yet +#endif + #ifdef CONFIG_STM32_HRTIM_FAULT # error HRTIM Faults not supported yet #endif @@ -181,7 +185,10 @@ struct stm32_hrtim_timout_s #ifdef HRTIM_HAVE_CHOPPER struct stm32_hrtim_chopper_s { - uint32_t reserved; /* reserved for future use */ + uint16_t start:4; /* Chopper start pulsewidth */ + uint16_t duty:3; /* Chopper duty cycle */ + uint16_t freq:4; /* Chopper carrier frequency value */ + uint16_t _res:5; /* Reserved */ }; #endif @@ -190,7 +197,10 @@ struct stm32_hrtim_chopper_s #ifdef HRTIM_HAVE_DEADTIME struct stm32_hrtim_deadtime_s { - uint32_t reserved; /* reserved for future use */ + uint8_t falling_lock:2; /* Deadtime falling value and sign lock */ + uint8_t rising_lock:2; /* Deadtime rising value and sign lock */ + uint8_t prescaler:3; /* Deadtime Prescaler */ + uint8_t _res:1; /* Reserved */ }; #endif @@ -447,7 +457,6 @@ static uint16_t hrtim_per_get(FAR struct stm32_hrtim_s *priv, uint8_t timer); static uint16_t hrtim_cmp_get(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint8_t index); - /* Initialization */ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv); @@ -508,13 +517,17 @@ static struct stm32_hrtim_slave_priv_s g_tima_priv = #ifdef CONFIG_STM32_HRTIM_TIMA_CHOP .chp = { - .reserved = 0 + .start_pulse = HRTIM_TIMA_CHOP_START, + .duty = HRTIM_TIMA_CHOP_DUTY, + .freq = HRTIM_TIMA_CHOP_FREQ }, #endif #ifdef CONFIG_STM32_HRTIM_TIMA_DT .dt = { - .reserved = 0 + .falling_lock = HRTIM_TIMA_DT_FLOCK, + .rising_lock = HRTIM_TIMA_DT_RLOCK, + .prescaler = HRTIM_TIMA_DT_PRESCALER, } #endif }, @@ -590,6 +603,7 @@ static struct stm32_hrtim_s g_hrtim1priv = struct hrtim_dev_s g_hrtim1dev = { .hd_priv = &g_hrtim1priv, + .initialized = false, }; /**************************************************************************** @@ -1723,7 +1737,7 @@ static void hrtim_preload_config(FAR struct stm32_hrtim_s *priv) * * Input parameters: * priv - A reference to the HRTIM block - * timer - HRTIM Timer timer + * timer - HRTIM Timer index * index - Compare register timer * cmp - New compare register value * @@ -1781,7 +1795,7 @@ errout: * * Input parameters: * priv - A reference to the HRTIM block - * timer - HRTIM Timer timer + * timer - HRTIM Timer index * per - New period register value * * Returned Value: @@ -1805,7 +1819,7 @@ static int hrtim_per_update(FAR struct stm32_hrtim_s *priv, uint8_t timer, * * Input parameters: * priv - A reference to the HRTIM block - * timer - HRTIM Timer timer + * timer - HRTIM Timer index * * Returned Value: * Zero on success; a negated errno value on failure @@ -1825,7 +1839,7 @@ static uint16_t hrtim_per_get(FAR struct stm32_hrtim_s *priv, uint8_t timer) * * Input parameters: * priv - A reference to the HRTIM block - * timer - HRTIM Timer timer + * timer - HRTIM Timer index * index - Compare register timer * * Returned Value: @@ -2073,12 +2087,19 @@ FAR struct hrtim_dev_s* stm32_hrtiminitialize(void) hrtim = dev->hd_priv; - ret = stm32_hrtimconfig(hrtim); - if (ret < 0) + /* configure HRTIM only once */ + + if (dev->initialized) { - tmrerr("ERROR: Failed to initialize HRTIM1: %d\n", ret); - errno = -ret; - return NULL; + ret = stm32_hrtimconfig(hrtim); + if (ret < 0) + { + tmrerr("ERROR: Failed to initialize HRTIM1: %d\n", ret); + errno = -ret; + return NULL; + } + + dev->initialized = true; } return dev; diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/stm32/stm32_hrtim.h index 8fa0864d47..7cd0620641 100644 --- a/arch/arm/src/stm32/stm32_hrtim.h +++ b/arch/arm/src/stm32/stm32_hrtim.h @@ -268,6 +268,89 @@ enum stm32_outputs_e HRTIM_OUT_TIME_CH2 = (1 << 9), }; +/* DAC synchronization event */ + +enum stm32_hrtim_dacsync_e +{ + HRTIM_DACSYNC_DIS, + HRTIM_DACSYNC_1, + HRTIM_DACSYNC_2, + HRTIM_DACSYNC_3, +}; + +/* HRTIM Deadtime Locks */ + +enum stm32_deadtime_lock_e +{ + HRTIM_DT_VALUE_LOCK = (1 << 0), /* Lock Deadtime value */ + HRTIM_DT_SIGN_LOCK = (1 << 1) /* Lock Deadtime sign */ +}; + +/* HRTIM Deadtime types */ + +enum stm32_deadtime_edge_e +{ + HRTIM_DT_RISING = 0, + HRTIM_DT_FALLING = 1 +}; + +/* Chopper start pulsewidth */ + +enum stm32_chopper_start_e +{ + HRTIM_CHP_START_16, + HRTIM_CHP_START_32, + HRTIM_CHP_START_48, + HRTIM_CHP_START_64, + HRTIM_CHP_START_80, + HRTIM_CHP_START_96, + HRTIM_CHP_START_112, + HRTIM_CHP_START_128, + HRTIM_CHP_START_144, + HRTIM_CHP_START_160, + HRTIM_CHP_START_176, + HRTIM_CHP_START_192, + HRTIM_CHP_START_208, + HRTIM_CHP_START_224, + HRTIM_CHP_START_256 +}; + +/* Chopper duty cycle */ + +enum stm32_chopper_duty_e +{ + HRTIM_CHP_DUTY_0, + HRTIM_CHP_DUTY_1, + HRTIM_CHP_DUTY_2, + HRTIM_CHP_DUTY_3, + HRTIM_CHP_DUTY_4, + HRTIM_CHP_DUTY_5, + HRTIM_CHP_DUTY_6, + HRTIM_CHP_DUTY_7 , +}; + +/* Chopper carrier frequency */ + +enum stm32_chopper_freq_e +{ + HRTIM_CHP_FREQ_d16, + HRTIM_CHP_FREQ_d32, + HRTIM_CHP_FREQ_d48, + HRTIM_CHP_FREQ_d64, + HRTIM_CHP_FREQ_d80, + HRTIM_CHP_FREQ_d96, + HRTIM_CHP_FREQ_d112, + HRTIM_CHP_FREQ_d128, + HRTIM_CHP_FREQ_d144, + HRTIM_CHP_FREQ_d160, + HRTIM_CHP_FREQ_d176, + HRTIM_CHP_FREQ_d192, + HRTIM_CHP_FREQ_d208, + HRTIM_CHP_FREQ_d224, + HRTIM_CHP_FREQ_d240, + HRTIM_CHP_FREQ_d256 +}; + /* */ struct hrtim_dev_s @@ -275,13 +358,14 @@ struct hrtim_dev_s #ifdef CONFIG_HRTIM /* Fields managed by common upper half HRTIM logic */ - uint8_t hd_ocount; /* The number of times the device has been opened */ - sem_t hd_closesem; /* Locks out new opens while close is in progress */ + uint8_t hd_ocount; /* The number of times the device has been opened */ + sem_t hd_closesem; /* Locks out new opens while close is in progress */ #endif /* Fields provided by lower half HRTIM logic */ - FAR void *hd_priv; /* Used by the arch-specific logic */ + FAR void *hd_priv; /* Used by the arch-specific logic */ + bool initialized; /* true: HRTIM driver has been initialized */ }; /************************************************************************************ From 5e3360b8b9bf56dfeb16c88c935b260d3a1b5db7 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sat, 17 Jun 2017 21:56:11 +0200 Subject: [PATCH 4/5] stm32_hrtim: faults and events configuration --- arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h | 11 +- arch/arm/src/stm32/stm32_hrtim.c | 801 +++++++++++++++++++- arch/arm/src/stm32/stm32_hrtim.h | 103 ++- 3 files changed, 871 insertions(+), 44 deletions(-) diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h index 65e84afab4..0bc6b93c5e 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h @@ -1136,11 +1136,12 @@ /* Timer X Fault Register */ -#define HRTIM_TIMFLT_FLT1EN (1 << 0) /* Bit 0 */ -#define HRTIM_TIMFLT_FLT2EN (1 << 1) /* Bit 1 */ -#define HRTIM_TIMFLT_FLT3EN (1 << 2) /* Bit 2 */ -#define HRTIM_TIMFLT_FLT4EN (1 << 3) /* Bit 3 */ -#define HRTIM_TIMFLT_FLT5EN (1 << 4) /* Bit 4 */ +#define HRTIM_TIMFLT_FLT1EN (1 << 0) /* Bit 0: Fault1 enable */ +#define HRTIM_TIMFLT_FLT2EN (1 << 1) /* Bit 1: Fault 2 enable */ +#define HRTIM_TIMFLT_FLT3EN (1 << 2) /* Bit 2: Fault 3 enable*/ +#define HRTIM_TIMFLT_FLT4EN (1 << 3) /* Bit 3: Fault 4 enable */ +#define HRTIM_TIMFLT_FLT5EN (1 << 4) /* Bit 4: Fault 5 enable */ +#define HRTIM_TIMFLT_FLTLCK (1 << 31) /* Bit 31: Fault sources lock*/ /* Common Control Register 1 */ diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c index d9f48d31ca..cebfd9870f 100644 --- a/arch/arm/src/stm32/stm32_hrtim.c +++ b/arch/arm/src/stm32/stm32_hrtim.c @@ -57,6 +57,8 @@ #if defined(CONFIG_STM32_STM32F33XX) +#warning "HRTIM UNDER DEVELOPMENT !" + #ifdef CONFIG_STM32_HRTIM_ADC # error HRTIM ADC Triggering not supported yet #endif @@ -65,14 +67,6 @@ # error HRTIM DAC Triggering not supported yet #endif -#ifdef CONFIG_STM32_HRTIM_FAULT -# error HRTIM Faults not supported yet -#endif - -#ifdef CONFIG_STM32_HRTIM_EEV -# error HRTIM External Events not supported yet -#endif - #ifdef CONFIG_STM32_HRTIM_BURST # error HRTIM Burst mode not supported yet #endif @@ -95,6 +89,42 @@ # define HRTIM_MASTER_PRESCALER HRTIM_PRESCALER_2 #endif +#ifndef HRTIM_TIMA_UPDATE +# define HRTIM_TIMA_UPDATE 0 +#endif +#ifndef HRTIM_TIMB_UPDATE +# define HRTIM_TIMB_UPDATE 0 +#endif +#ifndef HRTIM_TIMC_UPDATE +# define HRTIM_TIMC_UPDATE 0 +#endif +#ifndef HRTIM_TIMD_UPDATE +# define HRTIM_TIMD_UPDATE 0 +#endif +#ifndef HRTIM_TIME_UPDATE +# define HRTIM_TIME_UPDATE 0 +#endif + +#ifndef HRTIM_TIMA_RESET +# define HRTIM_TIMA_RESET 0 +#endif +#ifndef HRTIM_TIMB_RESET +# define HRTIM_TIMB_RESET 0 +#endif +#ifndef HRTIM_TIMC_RESET +# define HRTIM_TIMC_RESET 0 +#endif +#ifndef HRTIM_TIMD_RESET +# define HRTIM_TIMD_RESET 0 +#endif +#ifndef HRTIM_TIME_RESET +# define HRTIM_TIME_RESET 0 +#endif + +#ifndef HRTIM_IRQ_COMMON +# define HRTIM_IRQ_COMMON 0 +#endif + /* HRTIM clock source configuration */ #ifdef CONFIG_STM32_HRTIM_CLK_FROM_PLL @@ -166,6 +196,13 @@ # define HRTIM_HAVE_EEV 1 #endif +#if defined(CONFIG_STM32_HRTIM_MASTER_IRQ) || defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || \ + defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || defined(CONFIG_STM32_HRTIM_TIME_IRQ) || \ + defined(CONFIG_STM32_HRTIM_CMN_IRQ) +# defined HRTIM_HAVE_INTERRUPTS +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -234,7 +271,11 @@ struct stm32_hrtim_timcmn_s { uint32_t base; /* The base adress of the timer */ uint32_t pclk; /* The frequency of the peripheral clock - * that drives the timer module */ + * that drives the timer module + */ +#ifdef HRTIM_HAVE_INTERRUPTS + uint16_t irq; /* interrupts configuration */ +#endif #ifdef CONFIG_STM32_HRTIM_DMA uint32_t dmaburst; #endif @@ -259,7 +300,13 @@ struct stm32_hrtim_master_priv_s struct stm32_hrtim_slave_priv_s { - uint16_t update; /* Update configuration */ +#ifdef HRTIM_HAVE_FAULTS + uint8_t flt; /* Faults configuration. + * First five bits are fault sources, + * last bit is lock configuration + */ +#endif + uint16_t update; /* Update configuration */ uint32_t reset; /* Timer reset events */ #ifdef HRTIM_HAVE_PWM struct stm32_hrtim_pwm_s pwm; /* PWM configuration */ @@ -275,10 +322,9 @@ struct stm32_hrtim_slave_priv_s struct stm32_hrtim_fault_cfg_s { - uint8_t pol:1; /* Fault poalrity */ + uint8_t pol:1; /* Fault polarity */ uint8_t src:1; /* Fault source */ uint8_t filter:4; /* Fault filter */ - uint8_t flts:1; /* Fault Sampling clock division */ uint8_t lock:1; /* Fault lock */ }; @@ -382,6 +428,9 @@ struct stm32_hrtim_s #ifdef HRTIM_HAVE_EEV struct stm32_hrtim_eev_s *eev; #endif +#ifdef CONFIG_STM32_HRTIM_CMN_IRQ + uint32_t irq; /* Common interrupts configuration */ +#endif }; /**************************************************************************** @@ -436,15 +485,21 @@ static int hrtim_synch_config(FAR struct stm32_hrtim_s *priv); #endif #if defined(HRTIM_HAVE_PWM) static int hrtim_outputs_config(FAR struct stm32_hrtim_s *priv); +static int hrtim_outputs_enable(FAR struct stm32_hrtim_s *priv, uint16_t outputs, + bool state); #endif #ifdef HRTIM_HAVE_ADC static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv); #endif #ifdef HRTIM_HAVE_FAULTS static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv); +static int hrtim_flt_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index); +static int hrtim_tim_flts_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer); #endif #ifdef HRTIM_HAVE_EEV -static int hrtim_eev_config(FAR struct stm32_hrtim_s *priv); +static int hrtim_events_config(FAR struct stm32_hrtim_s *priv); +static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index); + #endif #ifdef HRTIM_HAVE_INTERRUPTS static int hrtim_irq_config(FAR struct stm32_hrtim_s *priv); @@ -456,6 +511,7 @@ static int hrtim_per_update(FAR struct stm32_hrtim_s *priv, uint8_t timer, static uint16_t hrtim_per_get(FAR struct stm32_hrtim_s *priv, uint8_t timer); static uint16_t hrtim_cmp_get(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint8_t index); +static int hrtim_reset_set(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint32_t reset); /* Initialization */ @@ -488,7 +544,10 @@ static struct stm32_hrtim_tim_s g_master = .tim = { .base = STM32_HRTIM1_MASTER_BASE, - .pclk = HRTIM_CLOCK/HRTIM_MASTER_PRESCALER + .pclk = HRTIM_CLOCK/HRTIM_MASTER_PRESCALER, +#ifdef CONFIG_STM32_HRTIM_MASTER_IRQ + .irq = HRTIM_IRQ_MASTER +#endif }, .priv = NULL, }; @@ -501,6 +560,8 @@ static struct stm32_hrtim_tim_s g_master = static struct stm32_hrtim_slave_priv_s g_tima_priv = { + .update = HRTIM_TIMA_UPDATE, + .reset = HRTIM_TIMA_RESET, #ifdef CONFIG_STM32_HRTIM_TIMA_PWM .pwm = { @@ -548,6 +609,9 @@ static struct stm32_hrtim_tim_s g_tima = { .base = STM32_HRTIM1_TIMERA_BASE, .pclk = HRTIM_CLOCK/HRTIM_TIMA_PRESCALER +#ifdef CONFIG_STM32_HRTIM_MASTER_IRQ + .irq = HRTIM_IRQ_TIMA, +#endif }, .priv = &g_tima_priv }; @@ -558,7 +622,51 @@ static struct stm32_hrtim_tim_s g_tima = #ifdef HRTIM_HAVE_FAULTS struct stm32_hrtim_faults_s g_flt = { -#warning "missing faults data" +#ifdef CONFIG_STM32_HRTIM_FAULT1 + .flt1 = + { + .pol = HRTIM_FAULT1_POL, + .src = HRTIM_FAULT1_SRC, + .filter = HRTIM_FAULT1_FILTER, + .lock = HRTIM_FAULT1_LOCK, + }, +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT2 + .flt2 = + { + .pol = HRTIM_FAULT2_POL, + .src = HRTIM_FAULT2_SRC, + .filter = HRTIM_FAULT2_FILTER, + .lock = HRTIM_FAULT2_LOCK, + }, +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT3 + .flt3 = + { + .pol = HRTIM_FAULT3_POL, + .src = HRTIM_FAULT3_SRC, + .filter = HRTIM_FAULT3_FILTER, + .lock = HRTIM_FAULT3_LOCK, + }, +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT4 + .flt2 = + { + .pol = HRTIM_FAULT4_POL, + .src = HRTIM_FAULT4_SRC, + .filter = HRTIM_FAULT4_FILTER, + .lock = HRTIM_FAULT4_LOCK, + }, +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT5 + .flt2 = + { + .pol = HRTIM_FAULT5_POL, + .src = HRTIM_FAULT5_SRC, + .filter = HRTIM_FAULT5_FILTER, + .lock = HRTIM_FAULT5_LOCK, + }, +#endif }; #endif @@ -567,7 +675,106 @@ struct stm32_hrtim_faults_s g_flt = #ifdef HRTIM_HAVE_EEV struct stm32_hrtim_eev_s g_eev = { -#warning "missing eev data" +#ifdef CONFIG_STM32_HRTIM_EEV1 + .eev1 = + { + .filter = HRTIM_EEV1_FILTER, + .src = HRTIM_EEV1_SRC, + .pol = HRTIM_EEV1_POL, + .sen = HRTIM_EEV1_SEN, + .mode = HRTIM_EEV1_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV2 + .eev2 = + { + .filter = HRTIM_EEV2_FILTER, + .src = HRTIM_EEV2_SRC, + .pol = HRTIM_EEV2_POL, + .sen = HRTIM_EEV2_SEN, + .mode = HRTIM_EEV2_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV3 + .eev3 = + { + .filter = HRTIM_EEV3_FILTER, + .src = HRTIM_EEV3_SRC, + .pol = HRTIM_EEV3_POL, + .sen = HRTIM_EEV3_SEN, + .mode = HRTIM_EEV3_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV4 + .eev4 = + { + .filter = HRTIM_EEV4_FILTER, + .src = HRTIM_EEV4_SRC, + .pol = HRTIM_EEV4_POL, + .sen = HRTIM_EEV4_SEN, + .mode = HRTIM_EEV4_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV5 + .eev5 = + { + .filter = HRTIM_EEV5_FILTER, + .src = HRTIM_EEV5_SRC, + .pol = HRTIM_EEV5_POL, + .sen = HRTIM_EEV5_SEN, + .mode = HRTIM_EEV5_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV6 + .eev6 = + { + .filter = HRTIM_EEV6_FILTER, + .src = HRTIM_EEV6_SRC, + .pol = HRTIM_EEV6_POL, + .sen = HRTIM_EEV6_SEN, + .mode = HRTIM_EEV6_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV7 + .eev7 = + { + .filter = HRTIM_EEV7_FILTER, + .src = HRTIM_EEV7_SRC, + .pol = HRTIM_EEV7_POL, + .sen = HRTIM_EEV7_SEN, + .mode = HRTIM_EEV7_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV8 + .eev8 = + { + .filter = HRTIM_EEV8_FILTER, + .src = HRTIM_EEV8_SRC, + .pol = HRTIM_EEV8_POL, + .sen = HRTIM_EEV8_SEN, + .mode = HRTIM_EEV8_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV9 + .eev9 = + { + .filter = HRTIM_EEV9_FILTER, + .src = HRTIM_EEV9_SRC, + .pol = HRTIM_EEV9_POL, + .sen = HRTIM_EEV9_SEN, + .mode = HRTIM_EEV9_MODE, + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV10 + .eev10 = + { + .filter = HRTIM_EEV10_FILTER, + .src = HRTIM_EEV10_SRC, + .pol = HRTIM_EEV10_POL, + .sen = HRTIM_EEV10_SEN, + .mode = HRTIM_EEV10_MODE, + } +#endif }; #endif @@ -593,10 +800,13 @@ static struct stm32_hrtim_s g_hrtim1priv = .time = &g_time, #endif #ifdef HRTIM_HAVE_FAULTS - .flt = &g_flt; + .flt = &g_flt, #endif #ifdef HRTIM_HAVE_EEV - .flt = &g_eev; + .eev = &g_eev, +#endif +#ifdef CONFIG_STM32_HRTIM_CMN_IRQ + .irq = HRTIM_IRQ_COMMON, #endif }; @@ -1249,35 +1459,35 @@ static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv) /* Configure Faults Inputs */ #ifdef CONFIG_STM32_HRTIM_FAULT1 - if (flt->flt1.src == HRTIM_FAULT_PIN) + if (flt->flt1.src == HRTIM_FAULT_SRC_PIN) { stm32_configgpio(GPIO_HRTIM1_FLT1); } #endif #ifdef CONFIG_STM32_HRTIM_FAULT2 - if (flt->flt2.src == HRTIM_FAULT_PIN) + if (flt->flt2.src == HRTIM_FAULT_SRC_PIN) { stm32_configgpio(GPIO_HRTIM1_FLT2); } #endif #ifdef CONFIG_STM32_HRTIM_FAULT3 - if (flt->flt3.src == HRTIM_FAULT_PIN) + if (flt->flt3.src == HRTIM_FAULT_SRC_PIN) { stm32_configgpio(GPIO_HRTIM1_FLT3); } #endif #ifdef CONFIG_STM32_HRTIM_FAULT4 - if (flt->flt4.src == HRTIM_FAULT_PIN) + if (flt->flt4.src == HRTIM_FAULT_SRC_PIN) { stm32_configgpio(GPIO_HRTIM1_FLT4); } #endif #ifdef CONFIG_STM32_HRTIM_FAULT5 - if (flt->flt5.src == HRTIM_FAULT_PIN) + if (flt->flt5.src == HRTIM_FAULT_SRC_PIN) { stm32_configgpio(GPIO_HRTIM1_FLT5); } @@ -1614,30 +1824,445 @@ static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv) } #endif +#ifdef HRTIM_HAVE_FAULTS + /**************************************************************************** - * Name: hrtim_faults_config + * Name: hrtim_tim_flts_cfg * * Description: - * Configure HRTIM Faults + * Configure HRTIM Slave Timer faults sources. * * Input Parameters: * priv - A reference to the HRTIM structure + * timer - timer index + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_tim_flts_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer) +{ + FAR struct stm32_hrtim_tim_s *tim; + FAR struct stm32_hrtim_slave_priv_s *slave_priv; + uint32_t regval = 0; + + tim = hrtim_tim_get(priv, timer); + + slave_priv = tim->priv; + + /* Get lock configuration */ + + regval = ((slave_priv->flt & HRTIM_TIM_FAULT_LOCK) ? HRTIM_TIMFLT_FLTLCK : 0); + + /* Get sources configuration */ + + regval |= slave_priv->flt & 0x1f; + + /* Write register */ + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_FLTR_OFFSET, regval); + + return OK; +} + +/**************************************************************************** + * Name: hrtim_faults_config + * + * Description: + * Configure single HRTIM Fault + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * index - Fault index + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_flt_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index) +{ + FAR struct stm32_hrtim_fault_cfg_s *flt; + int ret = OK; + uint32_t regval = 0; + + /* Get fault configuration */ + + switch (index) + { +#ifdef CONFIG_STM32_HRTIM_FAULT1 + case 1: + { + flt = &priv->flt->flt1; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT2 + case 2: + { + flt = &priv->flt->flt2; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT3 + case 3: + { + flt = &priv->flt->flt3; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT4 + case 4: + { + flt = &priv->flt->flt4; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_FAULT5 + case 5: + { + flt = &priv->flt->flt5; + break; + } +#endif + default: + { + ret = -EINVAL; + goto errout; + } + } + + /* Configure fault */ + + switch (index) + { + /* Fault 1-4 Configuration is located in first common fault register */ + + case 1: + case 2: + case 3: + case 4: + { + regval = hrtim_getreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET); + + /* Configure polarity */ + + regval |= (((flt->pol & HRTIM_FAULT_POL_HIGH) ? HRTIM_FLTINR1_FLT1P : 0) << (index-1)*8); + + /* Config source */ + + regval |= (((flt->src & HRTIM_FAULT_SRC_PIN) ? HRTIM_FLTINR1_FLT1SRC : 0) << (index-1)*8); + + /* Config filter */ + + regval |= ((flt->filter << HRTIM_FLTINR1_FLT1F_SHIFT) << (index-1)*8); + + /* Fault enable */ + + regval |= (HRTIM_FLTINR1_FLT1E << (index-1)*8); + + /* Write register */ + + hrtim_putreg(priv, STM32_HRTIM_CMN_FLTINR1_OFFSET, regval); + + break; + } + + /* Fault 5 configuration is located in second common fault register */ + + case 5: + { + regval = hrtim_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET); + + /* Configure polarity */ + + regval |= ((flt->pol & HRTIM_FAULT_POL_HIGH) ? HRTIM_FLTINR2_FLT5P : 0); + + /* Config source */ + + regval |= ((flt->src & HRTIM_FAULT_SRC_PIN) ? HRTIM_FLTINR2_FLT5SRC : 0); + + /* Config filter */ + + regval |= ((flt->filter << HRTIM_FLTINR2_FLT5F_SHIFT)); + + /* Fault enable */ + + regval |= HRTIM_FLTINR2_FLT5E; + + /* Write register */ + + hrtim_putreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET, regval); + + break; + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_faults_config + * + * Description: + * Configure HRTIM Faults + * + * Input Parameters: + * priv - A reference to the HRTIM structure * * Returned Value: * 0 on success, a negated errno value on failure * ****************************************************************************/ -#ifdef HRTIM_HAVE_FAULTS static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv) { -#warning "hrtim_faults_config: missing logic" + uint32_t regval = 0; + + /* Configure faults */ + +#ifdef CONFIG_STM32_HRTIM_FAULT1 + hrtim_flt_cfg(priv, 1); +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT2 + hrtim_flt_cfg(priv, 2); +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT3 + hrtim_flt_cfg(priv, 3); +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT4 + hrtim_flt_cfg(priv, 4); +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULT5 + hrtim_flt_cfg(priv, 5); +#endif + + /* Configure fault sources in Slave Timers */ + +#ifdef CONFIG_STM32_HRTIM_TIMA_FLT + hrtim_tim_flts_cfg(priv, HRTIM_TIMER_TIMA); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMB_FLT + hrtim_tim_flts_cfg(priv, HRTIM_TIMER_TIMA); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMC_FLT + hrtim_tim_flts_cfg(priv, HRTIM_TIMER_TIMA); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIMD_FLT + hrtim_tim_flts_cfg(priv, HRTIM_TIMER_TIMA); +#endif + +#ifdef CONFIG_STM32_HRTIM_TIME_FLT + hrtim_tim_flts_cfg(priv, HRTIM_TIMER_TIMA); +#endif + + /* Configure fault sampling clock division */ + + regval = hrtim_getreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET); + regval |= HRTIM_FAULT_SAMPLING << HRTIM_FLTINR1_FLT1F_SHIFT; + hrtim_putreg(priv, STM32_HRTIM_CMN_FLTINR2_OFFSET, regval); + return OK; } #endif +#ifdef HRTIM_HAVE_EEV + /**************************************************************************** - * Name: hrtim_eev_config + * Name: hrtim_eev_cfg + * + * Description: + * Configure single HRTIM External Event + * + * Input Parameters: + * priv - A reference to the HRTIM structure + * index - External Event index + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index) +{ + struct stm32_hrtim_eev_cfg_s* eev; + int ret = OK; + uint32_t regval = 0; + + /* Get External Event configuration */ + + switch (index) + { +#ifdef CONFIG_STM32_HRTIM_EEV1 + case 1: + { + eev = &priv->eev->eev1; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV2 + case 2: + { + eev = &priv->eev->eev2; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV3 + case 3: + { + eev = &priv->eev->eev3; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV4 + case 4: + { + eev = &priv->eev->eev4; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV5 + case 5: + { + eev = &priv->eev->eev5; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV6 + case 6: + { + eev = &priv->eev->eev6; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV7 + case 7: + { + eev = &priv->eev->eev7; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV8 + case 8: + { + eev = &priv->eev->eev8; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV8 + case 9: + { + eev = &priv->eev->eev9; + break; + } +#endif +#ifdef CONFIG_STM32_HRTIM_EEV10 + case 10: + { + eev = &priv->eev->eev10; + break; + } +#endif + default: + { + ret = -EINVAL; + goto errout; + } + } + + switch (index) + { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + { + regval = hrtim_getreg(priv, STM32_HRTIM_CMN_EECR1_OFFSET); + + /* Configure source */ + + regval |= ((eev->src << HRTIM_EECR1_EE1SRC_SHIFT) << (index-1)*6); + + /* Configure polarity */ + + regval |= ((eev->pol & HRTIM_FAULT_POL_HIGH ? HRTIM_EECR1_EE1POL : 0) << (index-1)*6); + + /* Configure sensitivity */ + + regval |= (((eev->sen) << HRTIM_EECR1_EE1SNS_SHIFT) << (index-1)*6); + + /* Configure mode */ + + regval |= (((eev->mode & HRTIM_EEV_MODE_FAST) ? HRTIM_EECR1_EE1FAST : 0) << (index-1)*6); + + /* Write register */ + + hrtim_putreg(priv, STM32_HRTIM_CMN_EECR1_OFFSET, regval); + + break; + } + case 7: + case 8: + case 9: + case 10: + { + regval = hrtim_getreg(priv, STM32_HRTIM_CMN_EECR2_OFFSET); + + /* Configure source */ + + regval |= ((eev->src << HRTIM_EECR2_EE6SRC_SHIFT) << (index-6)*6); + + /* Configure polarity */ + + regval |= ((eev->pol & HRTIM_FAULT_POL_HIGH ? HRTIM_EECR2_EE6POL : 0) << (index-6)*6); + + /* Configure sensitivity */ + + regval |= (((eev->sen) << HRTIM_EECR2_EE6SNS_SHIFT) << (index-6)*6); + + /* Configure External Event filter, only EEV6-10 */ + + regval |= (((eev->filter) << HRTIM_EECR2_EE6SNS_SHIFT) << (index-6)*6); + + /* Write register */ + + hrtim_putreg(priv, STM32_HRTIM_CMN_EECR2_OFFSET, regval); + + break; + } + + default: + { + ret = -EINVAL; + goto errout; + } + } + + + +errout: + return ret; +} + +/**************************************************************************** + * Name: hrtim_events_config * * Description: * Configure HRTIM External Events @@ -1650,10 +2275,58 @@ static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv) * ****************************************************************************/ -#ifdef HRTIM_HAVE_EEV -static int hrtim_eev_config(FAR struct stm32_hrtim_s *priv) +static int hrtim_events_config(FAR struct stm32_hrtim_s *priv) { -#warning "hrtim_eev_confi: missing logic" + uint32_t regval = 0; + + /* Configure Events sources */ + +#ifdef CONFIG_STM32_HRTIM_EEV1 + hrtim_eev_cfg(priv, 1); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV2 + hrtim_eev_cfg(priv, 2); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV3 + hrtim_eev_cfg(priv, 3); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV4 + hrtim_eev_cfg(priv, 4); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV5 + hrtim_eev_cfg(priv, 5); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV6 + hrtim_eev_cfg(priv, 6); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV7 + hrtim_eev_cfg(priv, 7); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV8 + hrtim_eev_cfg(priv, 8); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV9 + hrtim_eev_cfg(priv, 9); +#endif + +#ifdef CONFIG_STM32_HRTIM_EEV10 + hrtim_eev_cfg(priv, 10); +#endif + + /* External Event Sampling clock */ + + regval = hrtim_getreg(priv, STM32_HRTIM_CMN_EECR3_OFFSET); + regval |= (HRTIM_EEV_SAMPLING << HRTIM_EECR3_EEVSD_SHIFT); + hrtim_putreg(priv, STM32_HRTIM_CMN_EECR3_OFFSET, regval); + return OK; } #endif @@ -1888,6 +2561,64 @@ errout: return cmpx; } +/**************************************************************************** + * Name: hrtim_reset_set + * + * Description: + * Set HRTIM Timer Reset events + * + * Input parameters: + * priv - A reference to the HRTIM block + * timer - HRTIM Timer index + * reset - Reset configuration + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int hrtim_reset_set(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint32_t reset) +{ + int ret = OK; + + if (timer == HRTIM_TIMER_MASTER) + { + ret = -EINVAL; + goto errout; + } + + hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RSTR_OFFSET, reset); + +errout: + return ret; +} + +static int hrtim_reset_config(FAR struct stm32_hrtim_s *priv) +{ + +#ifdef CONFIG_ST32_HRTIM_TIMA + hrtim_reset_set(priv, HRTIM_TIMER_TIMA, priv->tima->reset); +#endif + +#ifdef CONFIG_ST32_HRTIM_TIMB + hrtim_reset_set(priv, HRTIM_TIMER_TIMB, priv->timb->reset); +#endif + +#ifdef CONFIG_ST32_HRTIM_TIMC + hrtim_reset_set(priv, HRTIM_TIMER_TIMC, priv->timc->reset); +#endif + +#ifdef CONFIG_ST32_HRTIM_TIMD + hrtim_reset_set(priv, HRTIM_TIMER_TIMD, priv->timd->reset); +#endif + +#ifdef CONFIG_ST32_HRTIM_TIME + hrtim_reset_set(priv, HRTIM_TIMER_TIME, priv->time->reset); +#endif + + return OK; +} + /**************************************************************************** * Name: stm32_hrtimconfig * @@ -1931,6 +2662,10 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) goto errout; } + /* Configure reset events */ + + hrtim_reset_config(priv); + /* Configure HRTIM GPIOs */ #if defined(HRTIM_HAVE_CAPTURE) || defined(HRTIM_HAVE_PWM) || defined(HRTIM_HAVE_SYNC) @@ -1997,10 +2732,10 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) } #endif - /* Configure Events */ + /* Configure External Events */ #ifdef HRTIM_HAVE_EEV - ret = hrtim_eev_config(priv); + ret = hrtim_events_config(priv); if (ret != OK) { tmrerr("ERROR: HRTIM EEV configuration failed!\n"); diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/stm32/stm32_hrtim.h index 7cd0620641..a9c0af5c42 100644 --- a/arch/arm/src/stm32/stm32_hrtim.h +++ b/arch/arm/src/stm32/stm32_hrtim.h @@ -80,6 +80,7 @@ enum stm32_hrtim_tim_e #ifdef CONFIG_STM32_HRTIM_TIME HRTIM_TIMER_TIME = 5, #endif + HRTIM_TIMER_COMMON = 6 }; /* Source which can force the Tx1/Tx2 output to its inactive state */ @@ -222,12 +223,31 @@ enum stm32_hrtim_tim_prescaler_e HRTIM_PRESCALER_128, }; +/* HRTIM Slave Timer fault sources Lock */ + +enum stm32_hrtim_tim_fault_lock_e +{ + HRTIM_TIM_FAULT_RW = 0, /* Slave Timer fault source are read/write */ + HRTIM_TIM_FAULT_LOCK = (1 << 7), /* Slave Timer fault source are read only */ +}; + +/* HRTIM Slave Timer Fault configuration */ + +enum stm32_hrtim_tim_fault_src_e +{ + HRTIM_TIM_FAULT1 = (1 << 0), + HRTIM_TIM_FAULT2 = (1 << 2), + HRTIM_TIM_FAULT3 = (1 << 3), + HRTIM_TIM_FAULT4 = (1 << 4), + HRTIM_TIM_FAULT5 = (1 << 5), +}; + /* HRTIM Fault Source */ enum stm32_hrtim_fault_src_e { - HRTIM_FAULT_SRC_PIN, - HRTIM_FAULT_SRC_INTERNAL + HRTIM_FAULT_SRC_PIN = 0, + HRTIM_FAULT_SRC_INTERNAL = 1 }; /* HRTIM External Event Source @@ -236,10 +256,81 @@ enum stm32_hrtim_fault_src_e enum stm32_hrtim_eev_src_e { - HRTIM_EEV_SRC_PIN, - HRTIM_EEV_SRC_ANALOG, - HRTIM_EEV_SRC_TRGO, - HRTIM_EEV_SRC_ADC + HRTIM_EEV_SRC_PIN = 0, + HRTIM_EEV_SRC_ANALOG = 1, + HRTIM_EEV_SRC_TRGO = 2, + HRTIM_EEV_SRC_ADC = 3 +}; + +/* HRTIM Fault Polarity */ + +enum stm32_hrtim_fault_pol_e +{ + HRTIM_FAULT_POL_LOW = 0, + HRTIM_FAULT_POL_HIGH = 1 +}; + +/* HRTIM External Event Polarity */ + +enum stm32_hrtim_eev_pol_e +{ + HRTIM_EEV_POL_HIGH = 0, /* External Event is active high */ + HRTIM_EEV_POL_LOW = 1 /* External Event is active low */ +}; + +/* HRTIM External Event sensitivity */ + +enum stm32_hrtim_eev_sen_e +{ + HRTIM_EEV_SEN_LEVEL = 0, /* On active level defined by polarity */ + HRTIM_EEV_SEN_RISING = 1, /* Rising edgne */ + HRTIM_EEV_SEN_FALLING = 2, /* Falling edge */ + HRTIM_EEV_SEN_BOTH = 3 /* Both edges */ +}; + +/* External Event Sampling clock division */ + +enum stm32_hrtim_eev_sampling_e +{ + HRTIM_EEV_SAMPLING_d1 = 0, + HRTIM_EEV_SAMPLING_d2 = 1, + HRTIM_EEV_SAMPLING_d4 = 2, + HRTIM_EEV_SAMPLING_d8 = 3 +}; + +/* HRTIM External Event Mode. + * NOTE: supported only for EEV1-5 + */ + +enum stm32_hrtim_eev_mode_e +{ + HRTIM_EEV_MODE_NORMAL, + HRTIM_EEV_MODE_FAST /* low latency mode */ +}; + + +/* External Event filter. + * NOTE: supported only for EEV6-10 + */ + +enum stm32_hrtim_eev_filter_e +{ + HRTIM_EEV_DISABLE = 0, + HRTIM_EEV_HRT_N2 = 1, + HRTIM_EEV_HRT_N4 = 2, + HRTIM_EEV_HRT_N8 = 3, + HRTIM_EEV_EEVSd2_N6 = 4, + HRTIM_EEV_EEVSd2_N8 = 5, + HRTIM_EEV_EEVSd4_N6 = 6, + HRTIM_EEV_EEVSd4_N8 = 7, + HRTIM_EEV_EEVSd8_N6 = 8, + HRTIM_EEV_EEVSd8_N8 = 9, + HRTIM_EEV_EEVSd16_N5 = 10, + HRTIM_EEV_EEVSd16_N6 = 11, + HRTIM_EEV_EEVSd16_N8 = 12, + HRTIM_EEV_EEVSd32_N5 = 13, + HRTIM_EEV_EEVSd32_N6 = 14, + HRTIM_EEV_EEVSd32_N8 = 15, }; /* Compare register index */ From 4d9d3c4a9cba04f95f18e59d1f34a0d1b274a555 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sat, 17 Jun 2017 22:12:56 +0200 Subject: [PATCH 5/5] stm32_hrtim: cosmetics --- arch/arm/src/stm32/stm32_hrtim.c | 12 +++++------ arch/arm/src/stm32/stm32_hrtim.h | 36 ++++++++++++++++---------------- 2 files changed, 23 insertions(+), 25 deletions(-) diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c index cebfd9870f..de0036d154 100644 --- a/arch/arm/src/stm32/stm32_hrtim.c +++ b/arch/arm/src/stm32/stm32_hrtim.c @@ -223,8 +223,8 @@ struct stm32_hrtim_timout_s struct stm32_hrtim_chopper_s { uint16_t start:4; /* Chopper start pulsewidth */ - uint16_t duty:3; /* Chopper duty cycle */ uint16_t freq:4; /* Chopper carrier frequency value */ + uint16_t duty:3; /* Chopper duty cycle */ uint16_t _res:5; /* Reserved */ }; #endif @@ -271,10 +271,10 @@ struct stm32_hrtim_timcmn_s { uint32_t base; /* The base adress of the timer */ uint32_t pclk; /* The frequency of the peripheral clock - * that drives the timer module + * that drives the timer module. */ #ifdef HRTIM_HAVE_INTERRUPTS - uint16_t irq; /* interrupts configuration */ + uint16_t irq; /* interrupts configuration */ #endif #ifdef CONFIG_STM32_HRTIM_DMA uint32_t dmaburst; @@ -303,7 +303,7 @@ struct stm32_hrtim_slave_priv_s #ifdef HRTIM_HAVE_FAULTS uint8_t flt; /* Faults configuration. * First five bits are fault sources, - * last bit is lock configuration + * last bit is lock configuration. */ #endif uint16_t update; /* Update configuration */ @@ -326,6 +326,7 @@ struct stm32_hrtim_fault_cfg_s uint8_t src:1; /* Fault source */ uint8_t filter:4; /* Fault filter */ uint8_t lock:1; /* Fault lock */ + uint8_t _res:1; /* Reserved */ }; /* Structure describes HRTIM Faults configuration */ @@ -2255,8 +2256,6 @@ static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index) } } - - errout: return ret; } @@ -2811,7 +2810,6 @@ errout: * ****************************************************************************/ - FAR struct hrtim_dev_s* stm32_hrtiminitialize(void) { FAR struct hrtim_dev_s *dev; diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/stm32/stm32_hrtim.h index a9c0af5c42..3919932d2c 100644 --- a/arch/arm/src/stm32/stm32_hrtim.h +++ b/arch/arm/src/stm32/stm32_hrtim.h @@ -118,7 +118,7 @@ enum stm32_hrtim_out_rst_e HRTIM_OUT_RST_CMP1 = (1 << 28), HRTIM_OUT_RST_PER = (1 << 29), HRTIM_OUT_RST_RESYNC = (1 << 30), - HRTIM_OUT_RST_SOFT = (1 << 31), + HRTIM_OUT_RST_SOFT = (1 << 31) }; /* Source which can force the Tx1/Tx2 output to its active state */ @@ -156,7 +156,7 @@ enum stm32_hrtim_out_set_e HRTIM_OUT_SET_CMP1 = (1 << 28), HRTIM_OUT_SET_PER = (1 << 29), HRTIM_OUT_SET_RESYNC = (1 << 30), - HRTIM_OUT_SET_SOFT = (1 << 31), + HRTIM_OUT_SET_SOFT = (1 << 31) }; /* Events that can reset TimerX Counter */ @@ -206,7 +206,7 @@ enum stm32_hrtim_tim_rst_e HRTIM_RST_EXTEVNT4, HRTIM_RST_EXTEVNT3, HRTIM_RST_EXTEVNT2, - HRTIM_RST_EXTEVNT1, + HRTIM_RST_EXTEVNT1 }; /* HRTIM Timer X prescaler */ @@ -220,7 +220,7 @@ enum stm32_hrtim_tim_prescaler_e HRTIM_PRESCALER_16, HRTIM_PRESCALER_32, HRTIM_PRESCALER_64, - HRTIM_PRESCALER_128, + HRTIM_PRESCALER_128 }; /* HRTIM Slave Timer fault sources Lock */ @@ -228,7 +228,7 @@ enum stm32_hrtim_tim_prescaler_e enum stm32_hrtim_tim_fault_lock_e { HRTIM_TIM_FAULT_RW = 0, /* Slave Timer fault source are read/write */ - HRTIM_TIM_FAULT_LOCK = (1 << 7), /* Slave Timer fault source are read only */ + HRTIM_TIM_FAULT_LOCK = (1 << 7) /* Slave Timer fault source are read only */ }; /* HRTIM Slave Timer Fault configuration */ @@ -239,7 +239,7 @@ enum stm32_hrtim_tim_fault_src_e HRTIM_TIM_FAULT2 = (1 << 2), HRTIM_TIM_FAULT3 = (1 << 3), HRTIM_TIM_FAULT4 = (1 << 4), - HRTIM_TIM_FAULT5 = (1 << 5), + HRTIM_TIM_FAULT5 = (1 << 5) }; /* HRTIM Fault Source */ @@ -251,7 +251,7 @@ enum stm32_hrtim_fault_src_e }; /* HRTIM External Event Source - * NOTE: according to Table 82 from STM32F334XX Manual + * NOTE: according to Table 82 from STM32F334XX Manual. */ enum stm32_hrtim_eev_src_e @@ -270,12 +270,12 @@ enum stm32_hrtim_fault_pol_e HRTIM_FAULT_POL_HIGH = 1 }; -/* HRTIM External Event Polarity */ +/* HRTIM External Event Polarity */ enum stm32_hrtim_eev_pol_e { - HRTIM_EEV_POL_HIGH = 0, /* External Event is active high */ - HRTIM_EEV_POL_LOW = 1 /* External Event is active low */ + HRTIM_EEV_POL_HIGH = 0, /* External Event is active high */ + HRTIM_EEV_POL_LOW = 1 /* External Event is active low */ }; /* HRTIM External Event sensitivity */ @@ -299,18 +299,18 @@ enum stm32_hrtim_eev_sampling_e }; /* HRTIM External Event Mode. - * NOTE: supported only for EEV1-5 + * NOTE: supported only for EEV1-5. */ enum stm32_hrtim_eev_mode_e { - HRTIM_EEV_MODE_NORMAL, - HRTIM_EEV_MODE_FAST /* low latency mode */ + HRTIM_EEV_MODE_NORMAL = 0, + HRTIM_EEV_MODE_FAST = 1 /* low latency mode */ }; /* External Event filter. - * NOTE: supported only for EEV6-10 + * NOTE: supported only for EEV6-10. */ enum stm32_hrtim_eev_filter_e @@ -330,7 +330,7 @@ enum stm32_hrtim_eev_filter_e HRTIM_EEV_EEVSd16_N8 = 12, HRTIM_EEV_EEVSd32_N5 = 13, HRTIM_EEV_EEVSd32_N6 = 14, - HRTIM_EEV_EEVSd32_N8 = 15, + HRTIM_EEV_EEVSd32_N8 = 15 }; /* Compare register index */ @@ -356,7 +356,7 @@ enum stm32_outputs_e HRTIM_OUT_TIMD_CH1 = (1 << 6), HRTIM_OUT_TIMD_CH2 = (1 << 7), HRTIM_OUT_TIME_CH1 = (1 << 8), - HRTIM_OUT_TIME_CH2 = (1 << 9), + HRTIM_OUT_TIME_CH2 = (1 << 9) }; /* DAC synchronization event */ @@ -366,7 +366,7 @@ enum stm32_hrtim_dacsync_e HRTIM_DACSYNC_DIS, HRTIM_DACSYNC_1, HRTIM_DACSYNC_2, - HRTIM_DACSYNC_3, + HRTIM_DACSYNC_3 }; /* HRTIM Deadtime Locks */ @@ -417,7 +417,7 @@ enum stm32_chopper_duty_e HRTIM_CHP_DUTY_4, HRTIM_CHP_DUTY_5, HRTIM_CHP_DUTY_6, - HRTIM_CHP_DUTY_7 , + HRTIM_CHP_DUTY_7 }; /* Chopper carrier frequency */