From edecfc2daca60b3bdca230311ec95ba8bb0c934e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 14 Dec 2015 08:42:39 -0600 Subject: [PATCH] ARMv7-A: Cosmetic changes --- arch/arm/src/armv7-a/arm_coherent_dcache.c | 2 +- arch/arm/src/armv7-a/arm_head.S | 9 ++++++--- arch/arm/src/armv7-a/arm_pghead.S | 2 +- arch/arm/src/armv7-a/arm_undefinedinsn.c | 2 +- arch/arm/src/armv7-a/l2cc.h | 1 - arch/arm/src/armv7-a/mmu.h | 2 +- 6 files changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_coherent_dcache.c b/arch/arm/src/armv7-a/arm_coherent_dcache.c index b85f2be0ff..363e88f804 100644 --- a/arch/arm/src/armv7-a/arm_coherent_dcache.c +++ b/arch/arm/src/armv7-a/arm_coherent_dcache.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/armv7/up_coherent_dcache.c + * arch/arm/src/armv7-a/up_coherent_dcache.c * * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S index 1f29f83f2f..d176289bfb 100644 --- a/arch/arm/src/armv7-a/arm_head.S +++ b/arch/arm/src/armv7-a/arm_head.S @@ -54,10 +54,13 @@ * Configuration **********************************************************************************/ -#undef ALIGNMENT_TRAP +/* Hard-coded options */ + +#undef CPU_ALIGNMENT_TRAP #undef CPU_CACHE_ROUND_ROBIN #undef CPU_DCACHE_DISABLE #undef CPU_ICACHE_DISABLE +#undef CPU_AFE_ENABLE /* There are three operational memory configurations: * @@ -465,7 +468,7 @@ __start: orr r0, r0, #(SCTLR_I) #endif -#ifdef ALIGNMENT_TRAP +#ifdef CPU_ALIGNMENT_TRAP /* Alignment abort enable * * SCTLR_A Bit 1: Strict alignment enabled @@ -474,7 +477,7 @@ __start: orr r0, r0, #(SCTLR_A) #endif -#ifdef CONFIG_AFE_ENABLE +#ifdef CPU_AFE_ENABLE /* AP[0:2] Permissions model * * SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value). diff --git a/arch/arm/src/armv7-a/arm_pghead.S b/arch/arm/src/armv7-a/arm_pghead.S index e7d72951c1..e785360dfe 100644 --- a/arch/arm/src/armv7-a/arm_pghead.S +++ b/arch/arm/src/armv7-a/arm_pghead.S @@ -461,7 +461,7 @@ __start: orr r0, r0, #(SCTLR_A) #endif -#ifdef CONFIG_AFE_ENABLE +#ifdef CPU_AFE_ENABLE /* AP[0:2] Permissions model * * SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value). diff --git a/arch/arm/src/armv7-a/arm_undefinedinsn.c b/arch/arm/src/armv7-a/arm_undefinedinsn.c index 392cfb9740..c0af4cae72 100644 --- a/arch/arm/src/armv7-a/arm_undefinedinsn.c +++ b/arch/arm/src/armv7-a/arm_undefinedinsn.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/armv7/arm_undefinedinsn.c + * arch/arm/src/armv7-a/arm_undefinedinsn.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/armv7-a/l2cc.h b/arch/arm/src/armv7-a/l2cc.h index 1c09f81fd6..f43ae9b653 100644 --- a/arch/arm/src/armv7-a/l2cc.h +++ b/arch/arm/src/armv7-a/l2cc.h @@ -1,6 +1,5 @@ /**************************************************************************** * arch/arm/src/armv7-a/l2cc.h - * Non-CP15 Registers * * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h index 869299c861..9ce8280b73 100644 --- a/arch/arm/src/armv7-a/mmu.h +++ b/arch/arm/src/armv7-a/mmu.h @@ -342,7 +342,7 @@ * PL2 - Software executing in Hyp mode */ -#ifdef CONFIG_AFE_ENABLE +#ifdef CPU_AFE_ENABLE /* AP[2:1] access permissions model. AP[0] is used as an access flag: * * AP[2] AP[1] PL1 PL0 Description