From ee1330ed5e036463af0eacc3d4de28fb64ec18f8 Mon Sep 17 00:00:00 2001 From: Mattias Edlund Date: Thu, 19 Oct 2017 07:00:55 -0600 Subject: [PATCH] =?UTF-8?q?The=20timer=20frequencies=20(BOARD=5FTIMx=5FFRE?= =?UTF-8?q?QUENCY)=20are=20incorrectly=20defined=20in=C2=A0configs/stm3240?= =?UTF-8?q?g-eval/include/board.h.=20=20Since=20the=20APB=20prescalers=20a?= =?UTF-8?q?re=20set=20to=20divide=20by=204=20and=202=20respectively,=20the?= =?UTF-8?q?=20frequencies=20should=20be=20"2xAPBx"=20as=20said=20in=20the?= =?UTF-8?q?=20comment.=C2=A0=20The=20correct=20frequencies=20are=20already?= =?UTF-8?q?=20defined=20but=20as=20STM32=5FAPBx=5FTIMx=5FCLKIN.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- configs/stm3240g-eval/include/board.h | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/configs/stm3240g-eval/include/board.h b/configs/stm3240g-eval/include/board.h index 14294aa737..153dbc4157 100644 --- a/configs/stm3240g-eval/include/board.h +++ b/configs/stm3240g-eval/include/board.h @@ -158,19 +158,26 @@ #define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx +/* Timer Frequencies, if APBx is set to 1, frequency is same as APBx * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 + * Note: TIM1,8-11 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY    STM32_APB1_TIM2_CLKIN +#define BOARD_TIM3_FREQUENCY    STM32_APB1_TIM3_CLKIN +#define BOARD_TIM4_FREQUENCY    STM32_APB1_TIM4_CLKIN +#define BOARD_TIM5_FREQUENCY    STM32_APB1_TIM5_CLKIN +#define BOARD_TIM6_FREQUENCY    STM32_APB1_TIM6_CLKIN +#define BOARD_TIM7_FREQUENCY    STM32_APB1_TIM7_CLKIN +#define BOARD_TIM12_FREQUENCY   STM32_APB1_TIM12_CLKIN +#define BOARD_TIM13_FREQUENCY   STM32_APB1_TIM13_CLKIN +#define BOARD_TIM14_FREQUENCY   STM32_APB1_TIM14_CLKIN + +#define BOARD_TIM1_FREQUENCY    STM32_APB2_TIM1_CLKIN +#define BOARD_TIM8_FREQUENCY    STM32_APB2_TIM8_CLKIN +#define BOARD_TIM9_FREQUENCY    STM32_APB2_TIM9_CLKIN +#define BOARD_TIM10_FREQUENCY   STM32_APB2_TIM10_CLKIN +#define BOARD_TIM11_FREQUENCY   STM32_APB2_TIM11_CLKIN /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses