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Add support for STM32 Potentiometer via ADC3

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4252 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-01-02 18:22:19 +00:00
parent 9e608fb472
commit ee27993c58
2 changed files with 16 additions and 7 deletions
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2
arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
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@ -111,7 +111,7 @@
#define GPIO_ADC3_IN4 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN6) #define GPIO_ADC3_IN4 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN6)
#define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN7) #define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN7)
#define GPIO_ADC3_IN6 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN8) #define GPIO_ADC3_IN6 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN8)
#define GPIO_ADC3_IN7 (GPIO_ANALOG|GPIO_PORT |GPIO_PIN9) #define GPIO_ADC3_IN7 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN9)
#define GPIO_ADC3_IN9 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN3) #define GPIO_ADC3_IN9 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN3)
#define GPIO_ADC3_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) #define GPIO_ADC3_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
#define GPIO_ADC3_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) #define GPIO_ADC3_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)

19
arch/arm/src/stm32/stm32_adc.c
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@ -960,7 +960,6 @@ static void adc_reset(FAR struct adc_dev_s *dev)
irqstate_t flags; irqstate_t flags;
uint32_t regval; uint32_t regval;
int offset; int offset;
int ret;
int i; int i;
avdbg("intf: ADC%d\n", priv->intf); avdbg("intf: ADC%d\n", priv->intf);
@ -1008,7 +1007,9 @@ static void adc_reset(FAR struct adc_dev_s *dev)
/* Set mode configuration (Independent mode) */ /* Set mode configuration (Independent mode) */
#ifdef CONFIG_STM32_STM32F10XX
regval |= ADC_CR1_IND; regval |= ADC_CR1_IND;
#endif
/* Initialize the Analog watchdog enable */ /* Initialize the Analog watchdog enable */
@ -1017,10 +1018,19 @@ static void adc_reset(FAR struct adc_dev_s *dev)
/* Enable interrupt flags */ /* Enable interrupt flags */
regval |= ADC_CR1_ALLINTS; regval |= ADC_CR1_ALLINTS;
adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval);
/* ADC1 CR2 Configuration */ /* ADC CCR configuration */
#ifdef CONFIG_STM32_STM32F40XX
regval |= adc_getreg(priv, STM32_ADC_CCR_OFFSET);
regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | ADC_CCR_DMA_MASK |
ADC_CCR_ADCPRE_MASK | ADC_CCR_VBATE | ADC_CCR_TSVREFE);
regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED | ADC_CCR_ADCPRE_DIV2);
adc_putreg(priv, STM32_ADC_CCR_OFFSET, regval);
#endif
/* ADC CR2 Configuration */
regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
@ -1028,7 +1038,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
regval &= ~ADC_CR2_CONT; regval &= ~ADC_CR2_CONT;
/*Set ALIGN (Right = 0) */ /* Set ALIGN (Right = 0) */
regval &= ~ADC_CR2_ALIGN; regval &= ~ADC_CR2_ALIGN;
adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
@ -1239,7 +1249,6 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
{ {
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
uint32_t adcsr; uint32_t adcsr;
uint32_t regval;
int32_t value; int32_t value;
/* Identifies the interruption AWD or EOC */ /* Identifies the interruption AWD or EOC */