Some HC12 start-up logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2302 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
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@ -47,6 +47,8 @@
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* Definitions
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************************************************************************************/
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#define HC12_MODULE_BASE 0x0000\
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/************************************************************************************
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* Public Types
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************************************************************************************/
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141
arch/hc/src/mc9s12ne64/mc9s12ne64_crg.h
Executable file
141
arch/hc/src/mc9s12ne64/mc9s12ne64_crg.h
Executable file
@ -0,0 +1,141 @@
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/************************************************************************************
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* arch/hc/src/mc9s12ne64/mc9s12ne64_crg.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
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||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_CRG_H
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#define __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_CRG_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include "chip.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* CRG Module Register Offsets */
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#define HC12_CRG_SYNR_OFFSET 0x34 /* CRG Synthesizer Register */
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#define HC12_CRG_REFDV_OFFSET 0x35 /* CRG Reference Divider Register */
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#define HC12_CRG_CTFLG_OFFSET 0x36 /* CRG Test Flags Register */
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#define HC12_CRG_CRGFLG_OFFSET 0x37 /* CRG Flags Register */
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#define HC12_CRG_CRGINT_OFFSET 0x38 /* CRG Interrupt Enable Register */
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#define HC12_CRG_CLKSEL_OFFSET 0x39 /* CRG Clock Select Register */
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#define HC12_CRG_PLLCTL_OFFSET 0x3a /* CRG PLL Control Register */
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#define HC12_CRG_RTICTL_OFFSET 0x3b /* CRG RTI Control Register */
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#define HC12_CRG_COPCTL_OFFSET 0x3c /* CRG COP Control Register */
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#define HC12_CRG_FORBYP_OFFSET 0x3d /* CRG Force and Bypass Test Register */
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#define HC12_CRG_CTCTL_OFFSET 0x3e /* CRG Test Control Register */
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#define HC12_CRG_ARMCOP_OFFSET 0x3f /* CRG COP Arm/Timer Reset */
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/* CRG Module Register Addresses */
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#define HC12_CRG_SYNR (HC12_MODULE_BASE+HC12_CRG_SYNR_OFFSET)
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#define HC12_CRG_REFDV (HC12_MODULE_BASE+HC12_CRG_REFDV_OFFSET)
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#define HC12_CRG_CTFLG (HC12_MODULE_BASE+HC12_CRG_CTFLG_OFFSET)
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#define HC12_CRG_CRGFLG (HC12_MODULE_BASE+HC12_CRG_CRGFLG_OFFSET)
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#define HC12_CRG_CRGINT (HC12_MODULE_BASE+HC12_CRG_CRGINT_OFFSET)
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#define HC12_CRG_CLKSEL (HC12_MODULE_BASE+HC12_CRG_CLKSEL_OFFSET)
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#define HC12_CRG_PLLCTL (HC12_MODULE_BASE+HC12_CRG_PLLCTL_OFFSET)
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#define HC12_CRG_RTICTL (HC12_MODULE_BASE+HC12_CRG_RTICTL_OFFSET)
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#define HC12_CRG_COPCTL (HC12_MODULE_BASE+HC12_CRG_COPCTL_OFFSET)
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#define HC12_CRG_FORBYP (HC12_MODULE_BASE+HC12_CRG_FORBYP_OFFSET)
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#define HC12_CRG_CTCTL (HC12_MODULE_BASE+HC12_CRG_CTCTL_OFFSET)
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#define HC12_CRG_ARMCOP (HC12_MODULE_BASE+HC12_CRG_ARMCOP_OFFSET)
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/* CRG Module Register Bit Definitions */
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#define CRG_SYNR_SHIFT (0) /* Bits 0-5: CRG synthesizer value */
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#define CRG_SYNR_MASK (0x3f << CRG_SYNR_SHIFT)
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#define CRG_REFDV_SHIFT (0) /* Bit 0-3: Reference divider */
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#define CRG_REFDV_MASK (15 << CRG_REFDV_SHIFT)
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#define CRG_CRGFLG_SCM (1 << 0) /* Bit 0: Self-Clock Mode Status Bit */
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#define CRG_CRGFLG_SCMIF (1 << 1) /* Bit 1: Self-Clock Mode Interrupt Flag */
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#define CRG_CRGFLG_TRACK (1 << 2) /* Bit 2: Track Status Bit */
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#define CRG_CRGFLG_LOCK (1 << 3) /* Bit 3: Lock Status Bit */
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#define CRG_CRGFLG_LOCKIF (1 << 4) /* Bit 4: PLL Lock Interrupt Flag */
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#define CRG_CRGFLG_LVRF (1 << 5) /* Bit 5: Low Voltage Reset Flag */
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#define CRG_CRGFLG_PORF (1 << 6) /* Bit 6: Power-on Reset Flag */
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#define CRG_CRGFLG_RTIF (1 << 7) /* Bit 7: Real-Time Interrupt Flag */
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#define CRG_CRGINT_SCMIE (1 << 1) /* Bit 1: Self-Clock Mode Status Bit */
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#define CRG_CRGINT_LOCKIE (1 << 4) /* Bit 4: Lock Interrupt Enable Bit */
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#define CRG_CRGINT_RTIE (1 << 7) /* Bit 7: Lock Interrupt Enable Bit */
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#define CRG_CLKSEL_COPWAI (1 << 0) /* Bit 0: COP stops in Wait Mode Bit */
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#define CRG_CLKSEL_RTIWAI (1 << 1) /* Bit 1: RTI stops in Wait Mode Bit */
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#define CRG_CLKSEL_CWAI (1 << 2) /* Bit 2: Core stops in Wait Mode Bit */
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#define CRG_CLKSEL_PLLWAI (1 << 3) /* Bit 3: PLL stops in Wait Mode Bit */
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#define CRG_CLKSEL_ROAWAI (1 << 4) /* Bit 4: Reduced Oscillator Amplitude in Wait Mode Bit */
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#define CRG_CLKSEL_SYSWAI (1 << 5) /* Bit 5: System clocks stop in wait mode bit */
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#define CRG_CLKSEL_PSTP (1 << 6) /* Bit 6: Pseudo-Stop Bit */
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#define CRG_CLKSEL_PLLSEL (1 << 7) /* Bit 7: PLL Select Bit */
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#define CRG_PLLCTL_SCME (1 << 0) /* Bit 0: Self-Clock Mode Enable Bit */
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#define CRG_PLLCTL_PCE (1 << 1) /* Bit 1: COP Enable during Pseudo-Stop Bit */
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#define CRG_PLLCTL_PRE (1 << 2) /* Bit 2: RTI Enable during Pseudo-Stop Bit */
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#define CRG_PLLCTL_ACQ (1 << 4) /* Bit 4: Acquisition Bit */
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#define CRG_PLLCTL_AUTO (1 << 5) /* Bit 5: Automatic Bandwidth Control Bit */
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#define CRG_PLLCTL_PLLON (1 << 6) /* Bit 6: Phase Lock Loop On Bit */
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#define CRG_PLLCTL_CME (1 << 7) /* Bit 7: Clock Monitor Enable Bit */
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#define CRG_RTICTL_MODCNT_SHIFT (0) /* Bits 0-3: Real-Time Interrupt Modulus Counter Select Bits */
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#define CRG_RTICTL_MODCNT_MASK (15 << CRG_RTICTL_MODCNT_SHIFT)
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#define CRG_RTICTL_PRER_SHIFT (4) /* Bits 4-6: Real-Time Interrupt Prescale Rate Select Bits */
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#define CRG_RTICTL_PRER_MASK (7 << CRG_RTICTL_PRE_SHIFT)
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#define CRG_COPCTL_CR_SHIFT (0) /* Bits 0-2: COP Watchdog Timer Rate select */
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#define CRG_COPCTL_CR_MASK (7 << CRG_COPCTL_CR_SHIFT)
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#define CRG_COPCTL_RSBCK (1 << 6) /* Bit 6: COP and RTI stop in Active BDM mode B */
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#define CRG_COPCTL_WCOP (1 << 7) /* Bit 7: Window COP Mode Bit */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_CRG_H */
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129
arch/hc/src/mc9s12ne64/mc9s12ne64_mmc.h
Executable file
129
arch/hc/src/mc9s12ne64/mc9s12ne64_mmc.h
Executable file
@ -0,0 +1,129 @@
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/************************************************************************************
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* arch/hc/src/mc9s12ne64/mc9s12ne64_mmc.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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||||
* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
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* distribution.
|
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* 3. Neither the name NuttX nor the names of its contributors may be
|
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* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_MMC_H
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#define __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_MMC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include "chip.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* MMC Sub-block */
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#define HC12_MMC_INITRM 0x0010 /* Internal RAM Position Register */
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# define MMC_INITRM_RAMHAL (1 << 0) /* Bit 0: RAM High-Align */
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# define MMC_INITRM_RAM_SHIFT (3) /* Bits 3-7: Internal RAM Map Position */
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# define MMC_INITRM_RAM_MASK (0x1f << MMC_INITRM_RAM_SHIFT)
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#define HC12_MMC_INITRG 0x0011 /* Internal Registers Position Register */
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# define MMC_INITRG_REG_SHIFT (3) /* Bits 3-6: Internal RAM Map Position */
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# define MMC_INITRG_REG_MASK (0x0f << MMC_INITRG_REG_SHIFT)
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#define HC12_MMC_INITEE 0x0012 /* Internal EEPROM Position Register */
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# define MMC_INITEE_EEON (1 << 0) /* Bit 0: Enable EEPROM */
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# define MMC_INITEE_EE_SHIFT (3) /* Bits 3-7: Internal EEPROM Map Position */
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# define MMC_INITEE_EE_MASK (0x1f << MMC_INITEE_EE_SHIFT)
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#define HC12_MMC_MISC 0x0013 /* Miscellaneous System Control Register */
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# define MMC_MISC_ROMON (1 << 0) /* Bit 0: Enable FLASH EEPROM or ROM */
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# define MMC_MISC_ROMHM (1 << 1) /* Bit 1: FLASH EEPROM or ROM Only in Second Half of Memory Map */
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# define MMC_MISC_EXSTR_SHIFT (3) /* Bits 3-7: External Access Stretch Bits */
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# define MMC_MISC_EXSTR_MASK (0x1f << MMC_MISC_EXSTR_SHIFT)
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# define MISC_EXSTR_CLKS0 (0 << MMC_MISC_EXSTR_SHIFT)
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# define MISC_EXSTR_CLKS1 (1 << MMC_MISC_EXSTR_SHIFT)
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# define MISC_EXSTR_CLKS2 (2 << MMC_MISC_EXSTR_SHIFT)
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# define MISC_EXSTR_CLKS3 (3 << MMC_MISC_EXSTR_SHIFT)
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#define HC12_MMC_TESTREG0 0x0014 /* Reserved Test Register 0 */
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#define HC12_MMC_TESTREG1 0x0017 /* Reserved Test Register 1 */
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#define HC12_MMC_MEMSIZ0 0x001c /* Memory Size Register 0 */
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# define MMC_MEMSIZ0_RAMSW_SHIFT (0) /* Bits 0-2: Allocated System RAM Memory Space */
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# define MMC_MEMSIZ0_RAMSW_MASK (7 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_2KB (0 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_4KB (1 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_6KB (2 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_8KB (3 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_10KB (4 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_12KB (5 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_14KB (6 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_16KB (7 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MMC_MEMSIZ0_EEPSW_SHIFT (4) /* Bits 4-5: Allocated EEPROM Memory Space */
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# define MMC_MEMSIZ0_EEPSW_MASK (3 << MMC_MEMSIZ0_EEPSW_SHIFT)
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# define MEMSIZ0_EEPSW_OKB (0 << MMC_MEMSIZ0_EEPSW_MASK)
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# define MEMSIZ0_EEPSW_2KB (1 << MMC_MEMSIZ0_EEPSW_MASK)
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# define MEMSIZ0_EEPSW_4KB (2 << MMC_MEMSIZ0_EEPSW_MASK)
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# define MEMSIZ0_EEPSW_5KB (3 << MMC_MEMSIZ0_EEPSW_MASK)
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# define MMC_MEMSIZ0_REGSW (1 << 7) /* Bits 7: Allocated System Register Space */
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#define HC12_MMC_MEMSIZ1 0x001d /* Memory Size Register 1 */
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# define MMC_MEMSIZ1_PAGSW_SHIFT (0) /* Bits 0-1: Allocated System RAM Memory Space */
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# define MMC_MEMSIZ1_PAGSW_MASK (3 << MMC_MEMSIZ1_PAGSW_SHIFT)
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# define MEMSIZ1_PAGSW_128KB (0 << MMC_MEMSIZ1_PAGSW_SHIFT)
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# define MEMSIZ1_PAGSW_256KB (1 << MMC_MEMSIZ1_PAGSW_SHIFT)
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# define MEMSIZ1_PAGSW_512KB (2 << MMC_MEMSIZ1_PAGSW_SHIFT)
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# define MEMSIZ1_PAGSW_1MB (3 << MMC_MEMSIZ1_PAGSW_SHIFT)
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# define MMC_MEMSIZ1_ROMSW_SHIFT (6) /* Bits 6-7: Allocated System RAM Memory Space */
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# define MMC_MEMSIZ1_ROMSW_MASK (3 << MMC_MEMSIZ1_ROMSW_SHIFT)
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# define MEMSIZ1_ROMSW_0KB (0 << MMC_MEMSIZ1_ROMSW_SHIFT)
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# define MEMSIZ1_ROMSW_16KB (1 << MMC_MEMSIZ1_ROMSW_SHIFT)
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# define MEMSIZ1_ROMSW_48KB (2 << MMC_MEMSIZ1_ROMSW_SHIFT)
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# define MEMSIZ1_ROMSW_64KB (3 << MMC_MEMSIZ1_ROMSW_SHIFT)
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#define HC12_MMC_PPAGE 0x0030 /* Program Page Index Register */
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# define MMC_PPAGE_PIX_SHIFT (0) /* Bits 0-5 Program Page Index Bits 5–0 */
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# define MMC_PPAGE_PIX_MASK (0x3f << MMC_PPAGE_PIX_SHIFT)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_MMC_H */
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@ -2,22 +2,22 @@
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* arch/hc/src/mc9s12ne64/mc9s12ne64_start.S
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* arch/hc/src/chip/mc9s12ne64_start.S
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
@ -41,6 +41,9 @@
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include "mc9s12ne64_mmc.h"
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#include "mc9s12ne64_crg.h"
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/****************************************************************************
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* Private Definitions
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****************************************************************************/
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@ -52,6 +55,50 @@
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.globl __start
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.file "mc9s12ne64_start.S"
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/****************************************************************************
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* Macros
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****************************************************************************/
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/* Memory map initialization */
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.macro MMCINIT
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movb #0, HC12_MMC_INITRG /* Set the register map position */
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nop
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movb #32, HC12_MMC_INITRM /* Set the RAM map position */
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movb #1, HC12_MMC_MISC /* MISC: EXSTR1=0 EXSTR0=0 ROMHM=0 ROMON=1 */
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.endm
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/* System clock initialization */
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.macro PLLINIT
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/* Select the clock source from crystal */
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movb #0, HC12_CRG_CLKSEL
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movb #CRG_CRGSEL_PLLSEL, HC12_CRG_CLKSEL
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|
||||
/* Set the multipler and divider and enable the PLL */
|
||||
|
||||
movb #0, HC12_CRG_PLLCTL
|
||||
movb #15, HC12_CRG_SYNR
|
||||
movb #15, HC12_CRG_REFDV
|
||||
movb #(CRG_PLLCTL_CME|CRG_PLLCTL_PLLON), HC12_CRG_PLLCTL
|
||||
|
||||
/* Wait for the PLL to lock on */
|
||||
|
||||
.Lpll_lock:
|
||||
ldab HC12_CRG_CRGFLG
|
||||
clra
|
||||
andb #CRG_CRGFLG_LOCK
|
||||
ldx #0
|
||||
bne .Lpll_lock
|
||||
tbne d,.Lpll_lock
|
||||
|
||||
/* The select the PLL clock source */
|
||||
|
||||
bset HC12_CRG_CLKSEL_OFFSET, #CRG_CLKSEL_PLLSEL
|
||||
.endm
|
||||
|
||||
/****************************************************************************
|
||||
* .text
|
||||
****************************************************************************/
|
||||
@ -60,9 +107,11 @@
|
||||
* Name: __start
|
||||
*
|
||||
* Description:
|
||||
* Power-up reset entry point
|
||||
* Power-up reset entry point
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
__start:
|
||||
MMCINIT /* Initialize the MMC */
|
||||
PLLINIT /* Initialize the PLL */
|
||||
.end
|
||||
|
||||
Loading…
Reference in New Issue
Block a user