From eecaa6e2e12a32807061e906028eae6305ce7325 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sat, 29 May 2010 14:39:13 +0000 Subject: [PATCH] Add more LPC17 header files git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2708 42af7a65-404d-4744-a932-0658087f49c3 --- arch/arm/src/lpc17xx/lpc17_ethernet.h | 279 ++++++++++++++++++++++++++ arch/arm/src/lpc17xx/lpc17_usb.h | 99 +++++---- 2 files changed, 327 insertions(+), 51 deletions(-) create mode 100755 arch/arm/src/lpc17xx/lpc17_ethernet.h diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.h b/arch/arm/src/lpc17xx/lpc17_ethernet.h new file mode 100755 index 0000000000..583a89d7a7 --- /dev/null +++ b/arch/arm/src/lpc17xx/lpc17_ethernet.h @@ -0,0 +1,279 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_ethernet.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_ETHERNET_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_ETHERNET_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "lp17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* MAC registers */ + +#define LPC17_ETH_MAC1_OFFSET 0x0000 /* MAC configuration register 1 */ +#define LPC17_ETH_MAC2_OFFSET 0x0004 /* MAC configuration register 2 */ +#define LPC17_ETH_IPGT_OFFSET 0x0008 /* Back-to-Back Inter-Packet-Gap register */ +#define LPC17_ETH_IPGR_OFFSET 0x000c /* Non Back-to-Back Inter-Packet-Gap register */ +#define LPC17_ETH_CLRT_OFFSET 0x0010 /* Collision window / Retry register */ +#define LPC17_ETH_MAXF_OFFSET 0x0014 /* Maximum Frame register */ +#define LPC17_ETH_SUPP_OFFSET 0x0018 /* PHY Support register */ +#define LPC17_ETH_TEST_OFFSET 0x001c /* Test register */ +#define LPC17_ETH_MCFG_OFFSET 0x0020 /* MII Mgmt Configuration register */ +#define LPC17_ETH_MCMD_OFFSET 0x0024 /* MII Mgmt Command register */ +#define LPC17_ETH_MADR_OFFSET 0x0028 /* MII Mgmt Address register */ +#define LPC17_ETH_MWTD_OFFSET 0x002c /* MII Mgmt Write Data register */ +#define LPC17_ETH_MRDD_OFFSET 0x0030 /* MII Mgmt Read Data register */ +#define LPC17_ETH_MIND_OFFSET 0x0034 /* MII Mgmt Indicators register */ +#define LPC17_ETH_SA0_OFFSET 0x0040 /* Station Address 0 register */ +#define LPC17_ETH_SA1_OFFSET 0x0044 /* Station Address 1 register */ +#define LPC17_ETH_SA2_OFFSET 0x0048 /* Station Address 2 register */ + +/* Control registers */ + +#define LPC17_ETH_COMMAND_OFFSET 0x0100 /* Command register */ +#define LPC17_ETH_STAT_OFFSET 0x0104 /* Status register */ +#define LPC17_ETH_RXDESC_OFFSET 0x0108 /* Receive descriptor base address register */ +#define LPC17_ETH_RXSTAT_OFFSET 0x010c /* Receive status base address register */ +#define LPC17_ETH_RXDESCNO_OFFSET 0x0110 /* Receive number of descriptors register */ +#define LPC17_ETH_RXPRODIDX_OFFSET 0x0114 /* Receive produce index register */ +#define LPC17_ETH_RXCONSIDX_OFFSET 0x0118 /* Receive consume index register */ +#define LPC17_ETH_TXDESC_OFFSET 0x011c /* Transmit descriptor base address register */ +#define LPC17_ETH_TXSTAT_OFFSET 0x0120 /* Transmit status base address register */ +#define LPC17_ETH_TXDESCRNO_OFFSET 0x0124 /* Transmit number of descriptors register */ +#define LPC17_ETH_TXPRODIDX_OFFSET 0x0128 /* Transmit produce index register */ +#define LPC17_ETH_TXCONSIDX_OFFSET 0x012c /* Transmit consume index register */ +#define LPC17_ETH_TSV0_OFFSET 0x0158 /* Transmit status vector 0 register */ +#define LPC17_ETH_TSV1_OFFSET 0x015c /* Transmit status vector 1 register */ +#define LPC17_ETH_RSV_OFFSET 0x0160 /* Receive status vector register */ +#define LPC17_ETH_FCCNTR_OFFSET 0x0170 /* Flow control counter register */ +#define LPC17_ETH_FCSTAT_OFFSET 0x0174 /* Flow control status register */ + +/* Rx filter registers */ + +#define LPC17_ETH_RXFLCTRL_OFFSET 0x0200 /* Receive filter control register */ +#define LPC17_ETH_RXFLWOLST_OFFSET 0x0204 /* Receive filter WoL status register */ +#define LPC17_ETH_RXFLWOLCLR_OFFSET 0x0208 /* Receive filter WoL clear register */ +#define LPC17_ETH_HASHFLL_OFFSET 0x0210 /* Hash filter table LSBs register */ +#define LPC17_ETH_HASHFLH_OFFSET 0x0214 /* Hash filter table MSBs register */ + +/* Module control registers */ + +#define LPC17_ETH_INTST_OFFSET 0x0fe0 /* Interrupt status register */ +#define LPC17_ETH_INTEN_OFFSET 0x0fe4 /* Interrupt enable register */ +#define LPC17_ETH_INTCLR_OFFSET 0x0fe8 /* Interrupt clear register */ +#define LPC17_ETH_INTSET_OFFSET 0x0fec /* Interrupt set register */ +#define LPC17_ETH_PWRDOWN_OFFSET 0x0ff4 /* Power-down register */ + +/* Register addresses ***************************************************************/ +/* MAC registers */ + +#define LPC17_ETH_MAC1 (LPC17_ETH_BASE+LPC17_ETH_MAC1_OFFSET) +#define LPC17_ETH_MAC2 (LPC17_ETH_BASE+LPC17_ETH_MAC2_OFFSET) +#define LPC17_ETH_IPGT (LPC17_ETH_BASE+LPC17_ETH_IPGT_OFFSET) +#define LPC17_ETH_IPGR (LPC17_ETH_BASE+LPC17_ETH_IPGR_OFFSET) +#define LPC17_ETH_CLRT (LPC17_ETH_BASE+LPC17_ETH_CLRT_OFFSET) +#define LPC17_ETH_MAXF (LPC17_ETH_BASE+LPC17_ETH_MAXF_OFFSET) +#define LPC17_ETH_SUPP (LPC17_ETH_BASE+LPC17_ETH_SUPP_OFFSET) +#define LPC17_ETH_TEST (LPC17_ETH_BASE+LPC17_ETH_TEST_OFFSET) +#define LPC17_ETH_MCFG (LPC17_ETH_BASE+LPC17_ETH_MCFG_OFFSET) +#define LPC17_ETH_MCMD (LPC17_ETH_BASE+LPC17_ETH_MCMD_OFFSET) +#define LPC17_ETH_MADR (LPC17_ETH_BASE+LPC17_ETH_MADR_OFFSET) +#define LPC17_ETH_MWTD (LPC17_ETH_BASE+LPC17_ETH_MWTD_OFFSET) +#define LPC17_ETH_MRDD (LPC17_ETH_BASE+LPC17_ETH_MRDD_OFFSET) +#define LPC17_ETH_MIND (LPC17_ETH_BASE+LPC17_ETH_MIND_OFFSET) +#define LPC17_ETH_SA0 (LPC17_ETH_BASE+LPC17_ETH_SA0_OFFSET) +#define LPC17_ETH_SA1 (LPC17_ETH_BASE+LPC17_ETH_SA1_OFFSET) +#define LPC17_ETH_SA2 (LPC17_ETH_BASE+LPC17_ETH_SA2_OFFSET) + +/* Control registers */ + +#define LPC17_ETH_COMMAND (LPC17_ETH_BASE+LPC17_ETH_COMMAND_OFFSET) +#define LPC17_ETH_STAT (LPC17_ETH_BASE+LPC17_ETH_STAT_OFFSET) +#define LPC17_ETH_RXDESC (LPC17_ETH_BASE+LPC17_ETH_RXDESC_OFFSET) +#define LPC17_ETH_RXSTAT (LPC17_ETH_BASE+LPC17_ETH_RXSTAT_OFFSET) +#define LPC17_ETH_RXDESCNO (LPC17_ETH_BASE+LPC17_ETH_RXDESCNO_OFFSET) +#define LPC17_ETH_RXPRODIDX (LPC17_ETH_BASE+LPC17_ETH_RXPRODIDX_OFFSET) +#define LPC17_ETH_RXCONSIDX (LPC17_ETH_BASE+LPC17_ETH_RXCONSIDX_OFFSET) +#define LPC17_ETH_TXDESC (LPC17_ETH_BASE+LPC17_ETH_TXDESC_OFFSET) +#define LPC17_ETH_TXSTAT (LPC17_ETH_BASE+LPC17_ETH_TXSTAT_OFFSET) +#define LPC17_ETH_TXDESCRNO (LPC17_ETH_BASE+LPC17_ETH_TXDESCRNO_OFFSET) +#define LPC17_ETH_TXPRODIDX (LPC17_ETH_BASE+LPC17_ETH_TXPRODIDX_OFFSET) +#define LPC17_ETH_TXCONSIDX (LPC17_ETH_BASE+LPC17_ETH_TXCONSIDX_OFFSET) +#define LPC17_ETH_TSV0 (LPC17_ETH_BASE+LPC17_ETH_TSV0_OFFSET) +#define LPC17_ETH_TSV1 (LPC17_ETH_BASE+LPC17_ETH_TSV1_OFFSET) +#define LPC17_ETH_RSV (LPC17_ETH_BASE+LPC17_ETH_RSV_OFFSET) +#define LPC17_ETH_FCCNTR (LPC17_ETH_BASE+LPC17_ETH_FCCNTR_OFFSET) +#define LPC17_ETH_FCSTAT (LPC17_ETH_BASE+LPC17_ETH_FCSTAT_OFFSET) + +/* Rx filter registers */ + +#define LPC17_ETH_RXFLCTRL (LPC17_ETH_BASE+LPC17_ETH_RXFLCTRL_OFFSET) +#define LPC17_ETH_RXFLWOLST (LPC17_ETH_BASE+LPC17_ETH_RXFLWOLST_OFFSET) +#define LPC17_ETH_RXFLWOLCLR (LPC17_ETH_BASE+LPC17_ETH_RXFLWOLCLR_OFFSET) +#define LPC17_ETH_HASHFLL (LPC17_ETH_BASE+LPC17_ETH_HASHFLL_OFFSET) +#define LPC17_ETH_HASHFLH (LPC17_ETH_BASE+LPC17_ETH_HASHFLH_OFFSET) + +/* Module control registers */ + +#define LPC17_ETH_INTST (LPC17_ETH_BASE+LPC17_ETH_INTST_OFFSET) +#define LPC17_ETH_INTEN (LPC17_ETH_BASE+LPC17_ETH_INTEN_OFFSET) +#define LPC17_ETH_INTCLR (LPC17_ETH_BASE+LPC17_ETH_INTCLR_OFFSET) +#define LPC17_ETH_INTSET (LPC17_ETH_BASE+LPC17_ETH_INTSET_OFFSET) +#define LPC17_ETH_PWRDOWN (LPC17_ETH_BASE+LPC17_ETH_PWRDOWN_OFFSET) + +/* Register bit definitions *********************************************************/ +/* MAC registers */ + +/* MAC configuration register 1 */ +#define ETH_MAC1_ +/* MAC configuration register 2 */ +#define ETH_MAC2_ +/* Back-to-Back Inter-Packet-Gap register */ +#define ETH_IPGT_ +/* Non Back-to-Back Inter-Packet-Gap register */ +#define ETH_IPGR_ +/* Collision window / Retry register */ +#define ETH_CLRT_ +/* Maximum Frame register */ +#define ETH_MAXF_ +/* PHY Support register */ +#define ETH_SUPP_ +/* Test register */ +#define ETH_TEST_ +/* MII Mgmt Configuration register */ +#define ETH_MCFG_ +/* MII Mgmt Command register */ +#define ETH_MCMD_ +/* MII Mgmt Address register */ +#define ETH_MADR_ +/* MII Mgmt Write Data register */ +#define ETH_MWTD_ +/* MII Mgmt Read Data register */ +#define ETH_MRDD_ +/* MII Mgmt Indicators register */ +#define ETH_MIND_ +/* Station Address 0 register */ +#define ETH_SA0_ +/* Station Address 1 register */ +#define ETH_SA1_ +/* Station Address 2 register */ +#define ETH_SA2_ + +/* Control registers */ + +/* Command register */ +#define ETH_COMMAND_ +/* Status register */ +#define ETH_STAT_ +/* Receive descriptor base address register */ +#define ETH_RXDESC_ +/* Receive status base address register */ +#define ETH_RXSTAT_ +/* Receive number of descriptors register */ +#define ETH_RXDESCNO_ +/* Receive produce index register */ +#define ETH_RXPRODIDX_ +/* Receive consume index register */ +#define ETH_RXCONSIDX_ +/* Transmit descriptor base address register */ +#define ETH_TXDESC_ +/* Transmit status base address register */ +#define ETH_TXSTAT_ +/* Transmit number of descriptors register */ +#define ETH_TXDESCRNO_ +/* Transmit produce index register */ +#define ETH_TXPRODIDX_ +/* Transmit consume index register */ +#define ETH_TXCONSIDX_ +/* Transmit status vector 0 register */ +#define ETH_TSV0_ +/* Transmit status vector 1 register */ +#define ETH_TSV1_ +/* Receive status vector register */ +#define ETH_RSV_ +/* Flow control counter register */ +#define ETH_FCCNTR_ +/* Flow control status register */ +#define ETH_FCSTAT_ + +/* Rx filter registers */ + +/* Receive filter control register */ +#define ETH_RXFLCTRL_ +/* Receive filter WoL status register */ +#define ETH_RXFLWOLST_ +/* Receive filter WoL clear register */ +#define ETH_RXFLWOLCLR_ +/* Hash filter table LSBs register */ +#define ETH_HASHFLL_ +/* Hash filter table MSBs register */ +#define ETH_HASHFLH_ + +/* Module control registers */ + +/* Interrupt status register */ +#define ETH_INTST_ +/* Interrupt enable register */ +#define ETH_INTEN_ +/* Interrupt clear register */ +#define ETH_INTCLR_ +/* Interrupt set register */ +#define ETH_INTSET_ +/* Power-down register */ +#define ETH_PWRDOWN_ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_ETHERNET_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_usb.h b/arch/arm/src/lpc17xx/lpc17_usb.h index b061c8f5da..4026c7a029 100755 --- a/arch/arm/src/lpc17xx/lpc17_usb.h +++ b/arch/arm/src/lpc17xx/lpc17_usb.h @@ -41,6 +41,7 @@ ************************************************************************************/ #include +#include #include "chip.h" #include "lp17_memorymap.h" @@ -51,30 +52,8 @@ /* Register offsets *****************************************************************/ /* USB Host Controller (OHCI) *******************************************************/ +/* See include/nuttx/ohci.h */ -#define LPC17_USBHOST_HCIREV_OFFSET 0x0000 /* HcRevision: Version of HCI specification */ -#define LPC17_USBHOST_CTRL_OFFSET 0x0004 /* HcControl: HC control */ -#define LPC17_USBHOST_CMDST_OFFSET 0x0008 /* HcCommandStatus: HC command status */ -#define LPC17_USBHOST_INTST_OFFSET 0x000c /* HcInterruptStatus: HC interrupt status */ -#define LPC17_USBHOST_INTEN_OFFSET 0x0010 /* HcInterruptEnable: HC interrupt enable */ -#define LPC17_USBHOST_INTDIS_OFFSET 0x0014 /* HcInterruptDisable: HC interrupt disable */ -#define LPC17_USBHOST_HCCA_OFFSET 0x0018 /* HcHCCA: HC communication area */ -#define LPC17_USBHOST_IIED_OFFSET 0x001c /* HcPeriodCurrentED: Current isoc or int endpoint desc */ -#define LPC17_USBHOST_CTRLHEADED_OFFSET 0x0020 /* HcControlHeadED: First EP desc in the control list */ -#define LPC17_USBHOST_CTRLED_OFFSET 0x0024 /* HcControlCurrentED: Current EP desc in the control list */ -#define LPC17_USBHOST_BULKHEADED_OFFSET 0x0028 /* HcBulkHeadED: First EP desc in the bulk list */ -#define LPC17_USBHOST_BULKED_OFFSET 0x002c /* HcBulkCurrentED: Current EP desc in the bulk list */ -#define LPC17_USBHOST_DONEHEAD_OFFSET 0x0030 /* HcDoneHead: Last transfer desc added to DONE queue */ -#define LPC17_USBHOST_FMINT_OFFSET 0x0034 /* HcFmInterval: Bit time interval that would not cause overrun */ -#define LPC17_USBHOST_FMREM_OFFSET 0x0038 /* HcFmRemaining: Bit time remaining in current frame */ -#define LPC17_USBHOST_FMNO_OFFSET 0x003c /* HcFmNumber: Frame number counter */ -#define LPC17_USBHOST_PERSTART_OFFSET 0x0040 /* HcPeriodicStart: Time to start processing periodic list */ -#define LPC17_USBHOST_LSTHRES_OFFSET 0x0044 /* HcLSThreshold: Commit to transfer threshold */ -#define LPC17_USBHOST_RHDESCA_OFFSET 0x0048 /* HcRhDescriptorA: Describes root hub (part A) */ -#define LPC17_USBHOST_RHDESCB_OFFSET 0x004c /* HcRhDescriptorB: Describes root hub (part B) */ -#define LPC17_USBHOST_RHSTATUS_OFFSET 0x0050 /* HcRhStatus: Root hub status */ -#define LPC17_USBHOST_RHPORTST1_OFFSET 0x0054 /* HcRhPort1Status: Root hub port status 1 */ -#define LPC17_USBHOST_RHPORTST2_OFFSET 0x0058 /* HcRhPort2Status: Root hub port status 2 */ #define LPC17_USBHOST_MODID_OFFSET 0x00fc /* Module ID/Revision ID */ /* USB OTG Controller ***************************************************************/ @@ -166,30 +145,40 @@ /* Register addresses ***************************************************************/ /* USB Host Controller (OHCI) *******************************************************/ +/* Control and status registers (section 7.1) */ -#define LPC17_USBHOST_HCIREV (LPC17_USB_BASE+LPC17_USBHOST_HCIREV_OFFSET) -#define LPC17_USBHOST_CTRL (LPC17_USB_BASE+LPC17_USBHOST_CTRL_OFFSET) -#define LPC17_USBHOST_CMDST (LPC17_USB_BASE+LPC17_USBHOST_CMDST_OFFSET) -#define LPC17_USBHOST_INTST (LPC17_USB_BASE+LPC17_USBHOST_INTST_OFFSET) -#define LPC17_USBHOST_INTEN (LPC17_USB_BASE+LPC17_USBHOST_INTEN_OFFSET) -#define LPC17_USBHOST_INTDIS (LPC17_USB_BASE+LPC17_USBHOST_INTDIS_OFFSET) -#define LPC17_USBHOST_HCCA (LPC17_USB_BASE+LPC17_USBHOST_HCCA_OFFSET) -#define LPC17_USBHOST_IIED (LPC17_USB_BASE+LPC17_USBHOST_IIED_OFFSET) -#define LPC17_USBHOST_CTRLHEADED (LPC17_USB_BASE+LPC17_USBHOST_CTRLHEADED_OFFSET) -#define LPC17_USBHOST_CTRLED (LPC17_USB_BASE+LPC17_USBHOST_CTRLED_OFFSET) -#define LPC17_USBHOST_BULKHEADED (LPC17_USB_BASE+LPC17_USBHOST_BULKHEADED_OFFSET) -#define LPC17_USBHOST_BULKED (LPC17_USB_BASE+LPC17_USBHOST_BULKED_OFFSET) -#define LPC17_USBHOST_DONEHEAD (LPC17_USB_BASE+LPC17_USBHOST_DONEHEAD_OFFSET) -#define LPC17_USBHOST_FMINT (LPC17_USB_BASE+LPC17_USBHOST_FMINT_OFFSET) -#define LPC17_USBHOST_FMREM (LPC17_USB_BASE+LPC17_USBHOST_FMREM_OFFSET) -#define LPC17_USBHOST_FMNO (LPC17_USB_BASE+LPC17_USBHOST_FMNO_OFFSET) -#define LPC17_USBHOST_PERSTART (LPC17_USB_BASE+LPC17_USBHOST_PERSTART_OFFSET) -#define LPC17_USBHOST_LSTHRES (LPC17_USB_BASE+LPC17_USBHOST_LSTHRES_OFFSET) -#define LPC17_USBHOST_RHDESCA (LPC17_USB_BASE+LPC17_USBHOST_RHDESCA_OFFSET) -#define LPC17_USBHOST_RHDESCB (LPC17_USB_BASE+LPC17_USBHOST_RHDESCB_OFFSET) -#define LPC17_USBHOST_RHSTATUS (LPC17_USB_BASE+LPC17_USBHOST_RHSTATUS_OFFSET) -#define LPC17_USBHOST_RHPORTST1 (LPC17_USB_BASE+LPC17_USBHOST_RHPORTST1_OFFSET) -#define LPC17_USBHOST_RHPORTST2 (LPC17_USB_BASE+LPC17_USBHOST_RHPORTST2_OFFSET) +#define LPC17_USBHOST_HCIREV (LPC17_USB_BASE+OHCI_HCIREV_OFFSET) +#define LPC17_USBHOST_CTRL (LPC17_USB_BASE+OHCI_CTRL_OFFSET) +#define LPC17_USBHOST_CMDST (LPC17_USB_BASE+OHCI_CMDST_OFFSET) +#define LPC17_USBHOST_INTST (LPC17_USB_BASE+OHCI_INTST_OFFSET) +#define LPC17_USBHOST_INTEN (LPC17_USB_BASE+OHCI_INTEN_OFFSET) +#define LPC17_USBHOST_INTDIS (LPC17_USB_BASE+OHCI_INTDIS_OFFSET) + +/* Memory pointers (section 7.2) */ + +#define LPC17_USBHOST_HCCA (LPC17_USB_BASE+OHCI_HCCA_OFFSET) +#define LPC17_USBHOST_PERED (LPC17_USB_BASE+OHCI_PERED_OFFSET) +#define LPC17_USBHOST_CTRLHEADED (LPC17_USB_BASE+OHCI_CTRLHEADED_OFFSET) +#define LPC17_USBHOST_CTRLED (LPC17_USB_BASE+OHCI_CTRLED_OFFSET) +#define LPC17_USBHOST_BULKHEADED (LPC17_USB_BASE+OHCI_BULKHEADED_OFFSET) +#define LPC17_USBHOST_BULKED (LPC17_USB_BASE+OHCI_BULKED_OFFSET) +#define LPC17_USBHOST_DONEHEAD (LPC17_USB_BASE+OHCI_DONEHEAD_OFFSET) + +/* Frame counters (section 7.3) */ + +#define LPC17_USBHOST_FMINT (LPC17_USB_BASE+OHCI_FMINT_OFFSET) +#define LPC17_USBHOST_FMREM (LPC17_USB_BASE+OHCI_FMREM_OFFSET) +#define LPC17_USBHOST_FMNO (LPC17_USB_BASE+OHCI_FMNO_OFFSET) +#define LPC17_USBHOST_PERSTART (LPC17_USB_BASE+OHCI_PERSTART_OFFSET) + +/* Root hub ports (section 7.4) */ + +#define LPC17_USBHOST_LSTHRES (LPC17_USB_BASE+OHCI_LSTHRES_OFFSET) +#define LPC17_USBHOST_RHDESCA (LPC17_USB_BASE+OHCI_RHDESCA_OFFSET) +#define LPC17_USBHOST_RHDESCB (LPC17_USB_BASE+OHCI_RHDESCB_OFFSET) +#define LPC17_USBHOST_RHSTATUS (LPC17_USB_BASE+OHCI_RHSTATUS_OFFSET) +#define LPC17_USBHOST_RHPORTST1 (LPC17_USB_BASE+OHCI_RHPORTST1_OFFSET) +#define LPC17_USBHOST_RHPORTST2 (LPC17_USB_BASE+OHCI_RHPORTST2_OFFSET) #define LPC17_USBHOST_MODID (LPC17_USB_BASE+LPC17_USBHOST_MODID_OFFSET) /* USB OTG Controller ***************************************************************/ @@ -212,8 +201,8 @@ /* SIE Command registers */ -#define LPC17_USBDEV_CMDCODE (LPC17_USB_BASE+LPC17_USBDEV_CMDCODE_OFFSET) -#define LPC17_USBDEV_CMDDATA (LPC17_USB_BASE+LPC17_USBDEV_CMDDATA_OFFSET) +#define LPC17_USBDEV_CMDCODE (LPC17_USB_BASE+LPC17_USBDEV_CMDCODE_OFFSET) +#define LPC17_USBDEV_CMDDATA (LPC17_USB_BASE+LPC17_USBDEV_CMDDATA_OFFSET) /* USB transfer registers */ @@ -281,9 +270,17 @@ /* Register bit definitions *********************************************************/ /* USB Host Controller (OHCI) *******************************************************/ -/* UM10360: "Refer to the OHCI specification document on the Compaq website for - * register definitions" - */ +/* See include/nuttx/ohci.h */ + +/* Module ID/Revision ID */ + +#define USBHOST_MODID_VER_SHIFT (0) /* Bits 0-7: Unique version number */ +#define USBHOST_MODID_VER_MASK (0xff << USBHOST_MODID_VER_SHIFT) +#define USBHOST_MODID_REV_SHIFT (8) /* Bits 9-15: Unique revision number */ +#define USBHOST_MODID_REV_MASK (0xff << USBHOST_MODID_REV_SHIFT) +#define USBHOST_MODID_3505_SHIFT (16) /* Bits 16-31: 0x3505 */ +#define USBHOST_MODID_3505_MASK (0xffff << USBHOST_MODID_3505_SHIFT) +# define USBHOST_MODID_3505 (0x3505 << USBHOST_MODID_3505_SHIFT) /* USB OTG Controller ***************************************************************/ /* OTG registers: