Add logic for system timer
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@204 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
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commit
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@ -74,8 +74,15 @@
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#define LPC214X_ADC1_IRQ 21 /* ADC 1 */
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#define LPC214X_USB_IRQ 22 /* USB */
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#define LPC214X_IRQ_SYSTIMER LPC214X_TIMER0_IRQ
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#define NR_IRQS 23
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/* There are 16 vectored interrupts. If vectored interrupts are enabled, the
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* following will be used by the system.
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*/
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#define LPC214X_SYSTEMER_VEC 0 /* System timer */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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@ -92,44 +92,44 @@
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#define LPC214X_WD_FEED_OFFSET 0x08 /* Watchdog Feed Register */
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#define LPC214X_WD_TV_OFFSET 0x0C /* Watchdog Time Value Register */
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/* Timer 0 register offsets */
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/* Timer 0/1 register offsets */
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#define LPC214X_TMR_IR_OFFSET 0x00 /* Interrupt Register */
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#define LPC214X_TMR_TCR_OFFSET 0x04 /* Timer Control Register */
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#define LPC214X_TMR_TC_OFFSET 0x08 /* Timer Counter */
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#define LPC214X_TMR_PR_OFFSET 0x0c /* Prescale Register */
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#define LPC214X_TMR_PC_OFFSET 0x10 /* Prescale Counter Register */
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#define LPC214X_TMR_MCR_OFFSET 0x14 /* Match Control Register */
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#define LPC214X_TMR_MR0_OFFSET 0x18 /* Match Register 0 */
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#define LPC214X_TMR_MR1_OFFSET 0x1c /* Match Register 1 */
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#define LPC214X_TMR_MR2_OFFSET 0x20 /* Match Register 2 */
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#define LPC214X_TMR_MR3_OFFSET 0x24 /* Match Register 3 */
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#define LPC214X_TMR_CCR_OFFSET 0x28 /* Capture Control Register */
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#define LPC214X_TMR_CR0_OFFSET 0x2c /* Capture Register 0 */
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#define LPC214X_TMR_CR1_OFFSET 0x30 /* Capture Register 1 */
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#define LPC214X_TMR_CR2_OFFSET 0x34 /* Capture Register 2 */
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#define LPC214X_TMR_CR3_OFFSET 0x38 /* Capture Register 3 */
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#define LPC214X_TMR_EMR_OFFSET 0x3c /* External Match Register */
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#define LPC214X_TMR_IR_OFFSET 0x00 /* RW:Interrupt Register */
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#define LPC214X_TMR_TCR_OFFSET 0x04 /* RW: Timer Control Register */
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#define LPC214X_TMR_TC_OFFSET 0x08 /* RW: Timer Counter */
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#define LPC214X_TMR_PR_OFFSET 0x0c /* RW: Prescale Register */
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#define LPC214X_TMR_PC_OFFSET 0x10 /* RW: Prescale Counter Register */
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#define LPC214X_TMR_MCR_OFFSET 0x14 /* RW: Match Control Register */
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#define LPC214X_TMR_MR0_OFFSET 0x18 /* RW: Match Register 0 */
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#define LPC214X_TMR_MR1_OFFSET 0x1c /* RW: Match Register 1 */
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#define LPC214X_TMR_MR2_OFFSET 0x20 /* RW: Match Register 2 */
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#define LPC214X_TMR_MR3_OFFSET 0x24 /* RW: Match Register 3 */
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#define LPC214X_TMR_CCR_OFFSET 0x28 /* RW: Capture Control Register */
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#define LPC214X_TMR_CR0_OFFSET 0x2c /* R: Capture Register 0 */
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#define LPC214X_TMR_CR1_OFFSET 0x30 /* R: Capture Register 1 */
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#define LPC214X_TMR_CR2_OFFSET 0x34 /* R: Capture Register 2 */
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#define LPC214X_TMR_CR3_OFFSET 0x38 /* RW: Capture Register 3 */
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#define LPC214X_TMR_EMR_OFFSET 0x3c /* RW: External Match Register */
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#define LPC214X_TMR_CTCR_OFFSET 0x70 /* Count Control Register */
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#define LPC214X_TMR_CTCR_OFFSET 0x70 /* RW: Count Control Register */
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/* UART0/1 Register Offsets */
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#define LPC214X_UART_RBR_OFFSET 0x00 /* R: Receive Buffer Register (DLAB=0) */
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#define LPC214X_UART_THR_OFFSET 0x00 /* W: Transmit Holding Register (DLAB=0) */
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#define LPC214X_UART_DLL_OFFSET 0x00 /* W: Divisor Latch Register (LSB) */
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#define LPC214X_UART_DLL_OFFSET 0x00 /* W: Divisor Latch Register (LSB, DLAB=1) */
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#define LPC214X_UART_IER_OFFSET 0x04 /* W: Interrupt Enable Register (DLAB=0) */
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#define LPC214X_UART_DLM_OFFSET 0x04 /* R/W: Divisor Latch Register (MSB, DLAB=1) */
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#define LPC214X_UART_IIR_OFFSET 0x08 /* R: Interrupt ID Register (DLAB=) */
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#define LPC214X_UART_DLM_OFFSET 0x04 /* RW: Divisor Latch Register (MSB, DLAB=1) */
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#define LPC214X_UART_IIR_OFFSET 0x08 /* R: Interrupt ID Register */
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#define LPC214X_UART_FCR_OFFSET 0x08 /* W: FIFO Control Register */
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#define LPC214X_UART_LCR_OFFSET 0x0c /* R/W: Line Control Register */
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#define LPC214X_UART_MCR_OFFSET 0x10 /* R/W: Modem Control REgister (2146/6/8 UART1 Only) */
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#define LPC214X_UART_LCR_OFFSET 0x0c /* RW: Line Control Register */
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#define LPC214X_UART_MCR_OFFSET 0x10 /* RW: Modem Control REgister (2146/6/8 UART1 Only) */
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#define LPC214X_UART_LSR_OFFSET 0x14 /* R: Scratch Pad Register */
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#define LPC214X_UART_MSR_OFFSET 0x18 /* R/W: MODEM Status Register (2146/6/8 UART1 Only) */
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#define LPC214X_UART_SCR_OFFSET 0x1c /* R/W: Line Status Register */
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#define LPC214X_UART_ACR_OFFSET 0x20 /* R/W: Autobaud Control Register */
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#define LPC214X_UART_FDR_OFFSET 0x28 /* R/W: Fractional Divider Register */
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#define LPC214X_UART_TER_OFFSET 0x30 /* R/W: Transmit Enable Register */
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#define LPC214X_UART_MSR_OFFSET 0x18 /* RW: MODEM Status Register (2146/6/8 UART1 Only) */
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#define LPC214X_UART_SCR_OFFSET 0x1c /* RW: Line Status Register */
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#define LPC214X_UART_ACR_OFFSET 0x20 /* RW: Autobaud Control Register */
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#define LPC214X_UART_FDR_OFFSET 0x28 /* RW: Fractional Divider Register */
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#define LPC214X_UART_TER_OFFSET 0x30 /* RW: Transmit Enable Register */
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/* PWM register offsets */
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152
arch/arm/src/lpc214x/lpc214x_timer.h
Normal file
152
arch/arm/src/lpc214x/lpc214x_timer.h
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@ -0,0 +1,152 @@
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/************************************************************************************
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* lpc214x/lpc214x_timer.h
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*
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* Copyright (C) 2007 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name Gregory Nutt nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __LPC214X_TIMER_H
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#define __LPC214X_TIMER_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Timer registers are 8-, 16-bit and 32-bits wide */
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/* Timer Interrupt Register Bit Definitions (8-bit) */
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#define LPC214X_TMR_IR_MR0I (1 << 0) /* Interrupt flag for match channel 0 */
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#define LPC214X_TMR_IR_MR1I (1 << 1) /* Interrupt flag for match channel 1 */
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#define LPC214X_TMR_IR_MR2I (1 << 2) /* Interrupt flag for match channel 2 */
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#define LPC214X_TMR_IR_MR3I (1 << 3) /* Interrupt flag for match channel 3 */
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#define LPC214X_TMR_IR_CR0I (1 << 4) /* Interrupt flag for capture channel 0 event */
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#define LPC214X_TMR_IR_CR1I (1 << 5) /* Interrupt flag for capture channel 1 event */
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#define LPC214X_TMR_IR_CR2I (1 << 6) /* Interrupt flag for capture channel 2 event */
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#define LPC214X_TMR_IR_CR3I (1 << 7) /* Interrupt flag for capture channel 3 event */
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#define LPC214X_TMR_IR_ALLI (0xff) /* All timer interrupts */
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/* Timer Control Register Bit Definitions (8-bits) */
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#define LPC214X_TMR_CR_ENABLE (1 << 0) /* Counter Enable */
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#define LPC214X_TMR_CR_RESET (1 << 1) /* Countger Reset */
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/* Timer Counter (32-bits, no bit fields) */
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/* Timer Prescale Register Bit Definitions (32-bits, no bit fields) */
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/* Timer Prescale Counter Register Bit Definitions */
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/* Timer Match Control Register Bit Definitions (16-bit) */
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#define LPC214X_TMR_MCR_MR0I (1 << 0) /* Enable Interrupt when MR0 matches TC */
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#define LPC214X_TMR_MCR_MR0R (1 << 1) /* Enable Reset of TC upon MR0 match */
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#define LPC214X_TMR_MCR_MR0S (1 << 2) /* Enable Stop of TC upon MR0 match */
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#define LPC214X_TMR_MCR_MR1I (1 << 3) /* Enable Interrupt when MR1 matches TC */
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#define LPC214X_TMR_MCR_MR1R (1 << 4) /* Enable Reset of TC upon MR1 match */
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#define LPC214X_TMR_MCR_MR1S (1 << 5) /* Enable Stop of TC upon MR1 match */
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#define LPC214X_TMR_MCR_MR2I (1 << 6) /* Enable Interrupt when MR2 matches TC */
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#define LPC214X_TMR_MCR_MR2R (1 << 7) /* Enable Reset of TC upon MR2 match */
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#define LPC214X_TMR_MCR_MR2S (1 << 8) /* Enable Stop of TC upon MR2 match */
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#define LPC214X_TMR_MCR_MR3I (1 << 9) /* Enable Interrupt when MR3 matches TC */
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#define LPC214X_TMR_MCR_MR3R (1 << 10) /* Enable Reset of TC upon MR3 match */
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#define LPC214X_TMR_MCR_MR3S (1 << 11) /* Enable Stop of TC upon MR3 match */
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/* Timer Match Register 0/1/2/3 (32-bits, no bit fields) */
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/* Timer Capture Control Register Bit Definitions */
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#define LPC214X_TMR_CCR_CAP0RE (1 << 0) /* Enable Rising edge on CAPn.0 will load TC to CR0 */
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#define LPC214X_TMR_CCR_CAP0FE (1 << 1) /* Enable Falling edge on CAPn.0 will load TC to CR0 */
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#define LPC214X_TMR_CCR_CAP0I (1 << 2) /* Enable Interrupt on load of CR0 */
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#define LPC214X_TMR_CCR_CAP1RE (1 << 3) /* Enable Rising edge on CAPn.1 will load TC to CR1 */
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#define LPC214X_TMR_CCR_CAP1FE (1 << 4) /* Enable Falling edge on CAPn.1 will load TC to CR1 */
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#define LPC214X_TMR_CCR_CAP1I (1 << 5) /* Enable Interrupt on load of CR1 */
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#define LPC214X_TMR_CCR_CAP2RE (1 << 6) /* Enable Rising edge on CAPn.2 will load TC to CR2 */
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#define LPC214X_TMR_CCR_CAP2FE (1 << 7) /* Enable Falling edge on CAPn.2 will load TC to CR2 */
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#define LPC214X_TMR_CCR_CAP2I (1 << 8) /* Enable Interrupt on load of CR2 */
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#define LPC214X_TMR_CCR_CAP3RE (1 << 9) /* Enable Rising edge on CAPn.3 will load TC to CR3 */
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#define LPC214X_TMR_CCR_CAP3FE (1 << 10) /* Enable Falling edge on CAPn.3 will load TC to CR3 */
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#define LPC214X_TMR_CCR_CAP3I (1 << 11) /* Enable Interrupt on load of CR3 */
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/* Timer Capture Register 0/1/2/3 (32-bits, no bit fields) */
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/* Timer External Match Register Bit Definitions */
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#define LPC214X_TMR_EMR_EM0 (1 << 0) /* External Match 0 */
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#define LPC214X_TMR_EMR_EM1 (1 << 1) /* External Match 1 */
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#define LPC214X_TMR_EMR_EM2 (1 << 2) /* External Match 2 */
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#define LPC214X_TMR_EMR_EM3 (1 << 3) /* External Match 3 */
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#define LPC214X_TMR_EMR_EMC0(b) ((b) << 4) /* External match control 0 (see below) */
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#define LPC214X_TMR_EMR_EMC1(b) ((b) << 6) /* External match control 1 (see below) */
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#define LPC214X_TMR_EMR_EMC2(b) ((b) << 8) /* External match control 2 (see below) */
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#define LPC214X_TMR_EMR_EMC3(b) ((b) << 10) /* External match control 3 (see below) */
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/* EMR External Match Control (EMCn) Field Falues */
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#define LPC214X_TMR_EMR_MASK (3) /* Mask for all bits */
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#define LPC214X_TMR_EMR_NOOP (0) /* Do nothing */
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#define LPC214X_TMR_EMR_CLEAR (1) /* Clear corresponding EMn bit/output to 0 */
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#define LPC214X_TMR_EMR_SET (2) /* Set corresponding EMn bit/output to 1 */
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#define LPC214X_TMR_EMR_TOGGLE (3) /* Toggle corresponding EMn bit/output */
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/* Timer Count Control Register Bit Definitions (8-bit) */
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#define LPC214X_TMR_
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#define LPC214X_TMR_CTCR_MODE_MASK (3 << 0) /* Counter/Timer Mode */
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#define LPC214X_TMR_CTCR_PCLK (0 << 0) /* Rising edge of PCLK */
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#define LPC214X_TMR_CTCR_RISING (1 << 0) /* Rising edge of CAP input */
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#define LPC214X_TMR_CTDR_FALLING (2 << 0) /* Failing edge of CAP input */
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#define LPC214X_TMR_CTCR_BOTH (3 << 0) /* Both edges of CAP input */
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#define LPC214X_TMR_CTCR_INPUT_MASK (3 << 2) /* Counter Input Select */
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#define LPC214X_TMR_CTCR_CR0 (0 << 2) /* CAPn.0 */
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#define LPC214X_TMR_CTCR_CR1 (1 << 2) /* CAPn.1 */
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#define LPC214X_TMR_CTCR_CR2 (2 << 2) /* CAPn.2 */
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#define LPC214X_TMR_CTCR_CR3 (3 << 2) /* CAPn.3 */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#endif /* __LPC214X_TIMER_H */
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@ -41,14 +41,29 @@
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#include <sys/types.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "clock_internal.h"
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#include "up_internal.h"
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#include "up_arch.h"
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#include "lpc214x_timer.h"
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#include "lpc214x_vic.h"
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/************************************************************
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* Definitions
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************************************************************/
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#define PCLKFREQ (LPC214X_FOSC/4) /* PCLK must be FOSC/4 */
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#define tmr_getreg8(o) getreg8(LPC214X_TMR0_BASE+(o))
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#define tmr_getreg16(o) getreg16(LPC214X_TMR0_BASE+(o))
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#define tmr_getreg32(o) getreg32(LPC214X_TMR0_BASE+(o))
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#define tmr_putreg8(o,v) putreg8((v), LPC214X_TMR0_BASE+(o))
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#define tmr_putreg16(o,v) putreg16((v), LPC214X_TMR0_BASE+(o))
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#define tmr_putreg32(o,v) putreg32((v), LPC214X_TMR0_BASE+(o))
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/************************************************************
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* Private Types
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************************************************************/
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@ -70,11 +85,25 @@
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*
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************************************************************/
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#ifdef CONFIG_VECTORED_INTERRUPTS
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int up_timerisr(uint32 *regs)
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#else
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int up_timerisr(int irq, uint32 *regs)
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#endif
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{
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/* Process timer interrupt */
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sched_process_timer();
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/* Clear the MR0 match interrupt */
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tmr_putreg8(LPC214X_TMR_IR_MR0I, LPC214X_TMR_IR_OFFSET);
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/* Reset the VIC as well */
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#ifdef CONFIG_VECTORED_INTERRUPTS
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vic_putreg(0, LPC214X_VIC_VECTADDR_OFFSET);
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#endif
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return 0;
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}
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@ -89,6 +118,45 @@ int up_timerisr(int irq, uint32 *regs)
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void up_timerinit(void)
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{
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#warning "Not implemented"
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}
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uint16 mcr;
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/* Clear all match and capture event interrupts */
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tmr_putreg8(LPC214X_TMR_IR_ALLI, LPC214X_TMR_IR_OFFSET);
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/* Clear the timer counter */
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tmr_putreg32(0, LPC214X_TMR_TC_OFFSET);
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/* No pre-scaler */
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tmr_putreg32(0, LPC214X_TMR_PR_OFFSET);
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/* Set timer match registger to get a TICK_PER_SEC rate
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* See arch/board.h and sched/os_internal.h
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*/
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tmr_putreg32(LPC214X_PCLKFREQ/TICK_PER_SEC, LPC214X_TMR_MR0_OFFSET);
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/* Reset timer counter regiser and interrupt on match */
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mcr = tmr_getreg16(LPC214X_TMR_MCR_OFFSET);
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mcr &= ~LPC214X_TMR_MCR_MR1I;
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mcr |= (LPC214X_TMR_MCR_MR0I | LPC214X_TMR_MCR_MR0R);
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tmr_putreg16(mcr, LPC214X_TMR_MCR_OFFSET);
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/* Enable counting */
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tmr_putreg8(LPC214X_TMR_CR_ENABLE, LPC214X_TMR_TCR_OFFSET);
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/* Attach the timer interrupt vector */
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#ifdef CONFIG_VECTORED_INTERRUPTS
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up_attach_vector(LPC214X_IRQ_SYSTIMER, LPC214X_SYSTEMER_VEC, (vic_vector_t)up_timerisr);
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#else
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(void)irq_attach(LPC214X_IRQ_SYSTIMER, (xcpt_t)up_timerisr);
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#endif
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/* And enable the timer interrupt */
|
||||
|
||||
up_enable_irq(LPC214X_IRQ_SYSTIMER);
|
||||
}
|
||||
|
||||
@ -1,70 +1,70 @@
|
||||
/************************************************************************************
|
||||
* lpc214x/vic.h
|
||||
*
|
||||
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name Gregory Nutt nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __LPC214X_VIC_H
|
||||
#define __LPC214X_VIC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* All VIC registers are 32-bits wide */
|
||||
|
||||
#define vic_getreg(o) getreg32(LPC214X_VIC_BASE+(o))
|
||||
#define vic_putreg(v,o) putreg32((v),LPC214X_VIC_BASE+(o))
|
||||
|
||||
// Vector Control Register bit definitions
|
||||
|
||||
#define LPC214X_VECTCNTL_IRQMASK (0x0000001f)
|
||||
#define LPC214X_VECTCNTL_IRQSHIFT (0)
|
||||
#define LPC214X_VECTCNTL_ENABLE (1 << 5)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __LPC214X_VIC_H */
|
||||
/************************************************************************************
|
||||
* lpc214x/lpc214x_vic.h
|
||||
*
|
||||
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name Gregory Nutt nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __LPC214X_VIC_H
|
||||
#define __LPC214X_VIC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* All VIC registers are 32-bits wide */
|
||||
|
||||
#define vic_getreg(o) getreg32(LPC214X_VIC_BASE+(o))
|
||||
#define vic_putreg(v,o) putreg32((v),LPC214X_VIC_BASE+(o))
|
||||
|
||||
/* Vector Control Register bit definitions */
|
||||
|
||||
#define LPC214X_VECTCNTL_IRQMASK (0x0000001f)
|
||||
#define LPC214X_VECTCNTL_IRQSHIFT (0)
|
||||
#define LPC214X_VECTCNTL_ENABLE (1 << 5)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __LPC214X_VIC_H */
|
||||
|
||||
@ -55,6 +55,8 @@
|
||||
#define LPC214X_MSEL (PLL_M-1)
|
||||
#define LPC214X_PLL_P 2
|
||||
|
||||
#define LPC214X_PCLKFREQ (LPC214X_FOSC/4) /* PCLK must be FOSC/4 */
|
||||
|
||||
#define LPC214X_PSEL0 5
|
||||
#define LPC214X_PSEL1 6
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user