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Merged nuttx/arch into master

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This commit is contained in:
Wail Khemir 2015-11-20 18:11:17 -05:00
commit efb8d31af6
13 changed files with 351 additions and 186 deletions
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4
arch/arm/src/efm32/efm32_rtc_burtc.c
View File

@ -367,7 +367,7 @@ static uint64_t efm32_get_burtc_tick(void)
************************************************************************************/
/************************************************************************************
* Name: up_rtcinitialize
* Name: up_rtc_initialize
*
* Description:
* Initialize the hardware RTC per the selected configuration. This function is
@ -381,7 +381,7 @@ static uint64_t efm32_get_burtc_tick(void)
*
************************************************************************************/
int up_rtcinitialize(void)
int up_rtc_initialize(void)
{
efm32_rtc_burtc_init();

4
arch/arm/src/lpc17xx/lpc176x_rtc.c
View File

@ -263,7 +263,7 @@ static int rtc_interrupt(int irq, void *context)
************************************************************************************/
/************************************************************************************
* Name: up_rtcinitialize
* Name: up_rtc_initialize
*
* Description:
* Initialize the hardware RTC per the selected configuration. This function is
@ -277,7 +277,7 @@ static int rtc_interrupt(int irq, void *context)
*
************************************************************************************/
int up_rtcinitialize(void)
int up_rtc_initialize(void)
{
int ret;

4
arch/arm/src/sam34/sam_rtc.c
View File

@ -351,7 +351,7 @@ static uint32_t rtc_sync(void)
************************************************************************************/
/************************************************************************************
* Name: up_rtcinitialize
* Name: up_rtc_initialize
*
* Description:
* Initialize the hardware RTC per the selected configuration. This function is
@ -365,7 +365,7 @@ static uint32_t rtc_sync(void)
*
************************************************************************************/
int up_rtcinitialize(void)
int up_rtc_initialize(void)
{
uint32_t ver;

4
arch/arm/src/sama5/sam_rtc.c
View File

@ -308,7 +308,7 @@ static int rtc_interrupt(int irq, void *context)
************************************************************************************/
/************************************************************************************
* Name: up_rtcinitialize
* Name: up_rtc_initialize
*
* Description:
* Initialize the hardware RTC per the selected configuration. This function is
@ -322,7 +322,7 @@ static int rtc_interrupt(int irq, void *context)
*
************************************************************************************/
int up_rtcinitialize(void)
int up_rtc_initialize(void)
{
uint32_t ver;

2
arch/arm/src/stm32/Make.defs
View File

@ -109,7 +109,7 @@ CHIP_ASRCS =
CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c
CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c stm32_irq.c
CHIP_CSRCS += stm32_dma.c stm32_lowputc.c stm32_serial.c stm32_spi.c
CHIP_CSRCS += stm32_sdio.c stm32_tim.c stm32_waste.c stm32_ccm.c
CHIP_CSRCS += stm32_sdio.c stm32_tim.c stm32_waste.c stm32_ccm.c stm32_uid.c
ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += stm32_tim_lowerhalf.c

4
arch/arm/src/stm32/stm32_rtcc.c
View File

@ -594,7 +594,7 @@ static int rtc_interrupt(int irq, void *context)
************************************************************************************/
/************************************************************************************
* Name: up_rtcinitialize
* Name: up_rtc_initialize
*
* Description:
* Initialize the hardware RTC per the selected configuration. This function is
@ -608,7 +608,7 @@ static int rtc_interrupt(int irq, void *context)
*
************************************************************************************/
int up_rtcinitialize(void)
int up_rtc_initialize(void)
{
uint32_t regval;
uint32_t tr_bkp;

4
arch/arm/src/stm32/stm32_rtcounter.c
View File

@ -350,7 +350,7 @@ static int stm32_rtc_interrupt(int irq, void *context)
************************************************************************************/
/************************************************************************************
* Name: up_rtcinitialize
* Name: up_rtc_initialize
*
* Description:
* Initialize the hardware RTC per the selected configuration. This function is
@ -364,7 +364,7 @@ static int stm32_rtc_interrupt(int irq, void *context)
*
************************************************************************************/
int up_rtcinitialize(void)
int up_rtc_initialize(void)
{
/* Enable write access to the backup domain (RTC registers, RTC backup data
* registers and backup SRAM).

1
arch/arm/src/stm32/stm32_tim.h
View File

@ -201,6 +201,7 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev);
* to indicate the nature of any failure.
*
****************************************************************************/
#ifdef CONFIG_TIMER
int stm32_timer_initialize(FAR const char *devpath, int timer);
#endif

361
arch/arm/src/stm32/stm32_tim_lowerhalf.c
View File

@ -52,9 +52,10 @@
#include "stm32_tim.h"
#if defined(CONFIG_TIMER) && \
( defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM3) || \
defined(CONFIG_STM32_TIM4) || defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) )
(defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \
defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \
defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8))
/****************************************************************************
* Pre-processor Definitions
@ -67,6 +68,7 @@
* driver state structure. This structure must be cast-compatible with the
* timer_lowerhalf_s structure.
*/
struct stm32_lowerhalf_s
{
const struct timer_ops_s *ops; /* Lower half operations */
@ -81,11 +83,12 @@ struct stm32_lowerhalf_s
****************************************************************************/
/* Helper functions *********************************************************/
static struct stm32_lowerhalf_s* stm32_get_lowerhalf(int timer);
static xcpt_t stm32_get_interrupt(int timer);
static struct stm32_lowerhalf_s *stm32_get_lowerhalf(int timer);
static xcpt_t stm32_get_interrupt(int timer);
/* Interrupt handling *******************************************************/
#ifdef CONFIG_STM32_TIM1
static int stm32_tim1_interrupt(int irq, FAR void *context);
#endif
@ -129,20 +132,22 @@ static int stm32_tim13_interrupt(int irq, FAR void *context);
static int stm32_tim14_interrupt(int irq, FAR void *context);
#endif
static int stm32_timer_handler(struct stm32_lowerhalf_s* attr);
static int stm32_timer_handler(struct stm32_lowerhalf_s *attr);
/* "Lower half" driver methods **********************************************/
static int stm32_start(struct timer_lowerhalf_s *lower);
static int stm32_stop(struct timer_lowerhalf_s *lower);
static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout);
static tccb_t stm32_sethandler(struct timer_lowerhalf_s *lower, tccb_t handler);
static int stm32_start(struct timer_lowerhalf_s *lower);
static int stm32_stop(struct timer_lowerhalf_s *lower);
static int stm32_settimeout(struct timer_lowerhalf_s *lower,
uint32_t timeout);
static tccb_t stm32_sethandler(struct timer_lowerhalf_s *lower,
tccb_t handler);
/****************************************************************************
* Private Data
****************************************************************************/
/* "Lower half" driver methods */
static const struct timer_ops_s g_timer_ops =
{
.start = stm32_start,
@ -213,87 +218,88 @@ static struct stm32_lowerhalf_s g_tim14_lowerHalf;
* A pointer to the lower half structure on success, NULL on failure
*
****************************************************************************/
static struct stm32_lowerhalf_s* stm32_get_lowerhalf(int timer)
{
struct stm32_lowerhalf_s* lower;
switch(timer)
{
static struct stm32_lowerhalf_s *stm32_get_lowerhalf(int timer)
{
struct stm32_lowerhalf_s *lower;
switch (timer)
{
#ifdef CONFIG_STM32_TIM1
case 1:
lower = &g_tim1_lowerHalf;
break;
case 1:
lower = &g_tim1_lowerHalf;
break;
#endif
#ifdef CONFIG_STM32_TIM2
case 2:
lower = &g_tim2_lowerHalf;
break;
case 2:
lower = &g_tim2_lowerHalf;
break;
#endif
#ifdef CONFIG_STM32_TIM3
case 3:
lower = &g_tim3_lowerHalf;
break;
case 3:
lower = &g_tim3_lowerHalf;
break;
#endif
#ifdef CONFIG_STM32_TIM4
case 4:
lower = &g_tim4_lowerHalf;
break;
case 4:
lower = &g_tim4_lowerHalf;
break;
#endif
#ifdef CONFIG_STM32_TIM5
case 5:
lower = &g_tim5_lowerHalf;
break;
case 5:
lower = &g_tim5_lowerHalf;
break;
#endif
#ifdef CONFIG_STM32_TIM6
case 6:
lower = &g_tim6_lowerHalf;
break;
case 6:
lower = &g_tim6_lowerHalf;
break;
#endif
#ifdef CONFIG_STM32_TIM7
case 7:
lower = &g_tim7_lowerHalf;
break;
case 7:
lower = &g_tim7_lowerHalf;
break;
#endif
#ifdef CONFIG_STM32_TIM8
case 8:
lower = &g_tim8_lowerHalf;
break;
case 8:
lower = &g_tim8_lowerHalf;
break;
#endif
#ifdef CONFIG_STM32_TIM9
case 9:
lower = &g_tim9_lowerHalf;
break;
case 9:
lower = &g_tim9_lowerHalf;
break;
#endif
#ifdef CONFIG_STM32_TIM10
case 10:
lower = &g_tim10_lowerHalf;
break;
case 10:
lower = &g_tim10_lowerHalf;
break;
#endif
#ifdef CONFIG_STM32_TIM11
case 11:
lower = &g_tim11_lowerHalf;
break;
case 11:
lower = &g_tim11_lowerHalf;
break;
#endif
#ifdef CONFIG_STM32_TIM12
case 12:
lower = &g_tim12_lowerHalf;
break;
case 12:
lower = &g_tim12_lowerHalf;
break;
#endif
#ifdef CONFIG_STM32_TIM13
case 13:
lower = &g_tim13_lowerHalf;
break;
case 13:
lower = &g_tim13_lowerHalf;
break;
#endif
#ifdef CONFIG_STM32_TIM14
case 14:
lower = &g_tim14_lowerHalf;
break;
case 14:
lower = &g_tim14_lowerHalf;
break;
#endif
default:
lower = 0;
}
default:
lower = 0;
}
return lower;
return lower;
}
/****************************************************************************
@ -309,87 +315,88 @@ static struct stm32_lowerhalf_s* stm32_get_lowerhalf(int timer)
* A pointer to the interrupt handler on success, NULL on failure
*
****************************************************************************/
static xcpt_t stm32_get_interrupt(int timer)
{
xcpt_t intr;
xcpt_t intr;
switch(timer)
{
switch (timer)
{
#ifdef CONFIG_STM32_TIM1
case 1:
intr = stm32_tim1_interrupt;
break;
case 1:
intr = stm32_tim1_interrupt;
break;
#endif
#ifdef CONFIG_STM32_TIM2
case 2:
intr = stm32_tim2_interrupt;
break;
case 2:
intr = stm32_tim2_interrupt;
break;
#endif
#ifdef CONFIG_STM32_TIM3
case 3:
intr = stm32_tim3_interrupt;
break;
case 3:
intr = stm32_tim3_interrupt;
break;
#endif
#ifdef CONFIG_STM32_TIM4
case 4:
intr = stm32_tim4_interrupt;
break;
case 4:
intr = stm32_tim4_interrupt;
break;
#endif
#ifdef CONFIG_STM32_TIM5
case 5:
intr = stm32_tim5_interrupt;
break;
case 5:
intr = stm32_tim5_interrupt;
break;
#endif
#ifdef CONFIG_STM32_TIM6
case 6:
intr = stm32_tim6_interrupt;
break;
case 6:
intr = stm32_tim6_interrupt;
break;
#endif
#ifdef CONFIG_STM32_TIM7
case 7:
intr = stm32_tim7_interrupt;
break;
case 7:
intr = stm32_tim7_interrupt;
break;
#endif
#ifdef CONFIG_STM32_TIM8
case 8:
intr = stm32_tim8_interrupt;
break;
case 8:
intr = stm32_tim8_interrupt;
break;
#endif
#ifdef CONFIG_STM32_TIM9
case 9:
intr = stm32_tim9_interrupt;
break;
case 9:
intr = stm32_tim9_interrupt;
break;
#endif
#ifdef CONFIG_STM32_TIM10
case 10:
intr = stm32_tim10_interrupt;
break;
case 10:
intr = stm32_tim10_interrupt;
break;
#endif
#ifdef CONFIG_STM32_TIM11
case 11:
intr = stm32_tim11_interrupt;
break;
case 11:
intr = stm32_tim11_interrupt;
break;
#endif
#ifdef CONFIG_STM32_TIM12
case 12:
intr = stm32_tim12_interrupt;
break;
case 12:
intr = stm32_tim12_interrupt;
break;
#endif
#ifdef CONFIG_STM32_TIM13
case 13:
intr = stm32_tim13_interrupt;
break;
case 13:
intr = stm32_tim13_interrupt;
break;
#endif
#ifdef CONFIG_STM32_TIM14
case 14:
intr = stm32_tim14_interrupt;
break;
case 14:
intr = stm32_tim14_interrupt;
break;
#endif
default:
intr = 0;
}
default:
intr = 0;
}
return intr;
return intr;
}
/****************************************************************************
@ -399,6 +406,7 @@ static xcpt_t stm32_get_interrupt(int timer)
* Individual interrupt handlers for each timer
*
****************************************************************************/
#ifdef CONFIG_STM32_TIM1
static int stm32_tim1_interrupt(int irq, FAR void *context)
{
@ -505,29 +513,30 @@ static int stm32_tim14_interrupt(int irq, FAR void *context)
*
* Input Parameters:
*
*
* Returned Values:
*
*
****************************************************************************/
static int stm32_timer_handler(struct stm32_lowerhalf_s* lower)
static int stm32_timer_handler(struct stm32_lowerhalf_s *lower)
{
STM32_TIM_ACKINT(lower->tim, 0);
STM32_TIM_ACKINT(lower->tim, 0);
uint32_t next_interval_us = 0;
int ret = (*lower->handlerUsr)(&next_interval_us);
uint32_t next_interval_us = 0;
int ret = (*lower->handlerUsr)(&next_interval_us);
if(ret == OK)
{
if(next_interval_us > 0)
STM32_TIM_SETPERIOD(lower->tim, next_interval_us);
}
else
{
stm32_stop(lower);
}
if (ret == OK)
{
if (next_interval_us > 0)
{
STM32_TIM_SETPERIOD(lower->tim, next_interval_us);
}
}
else
{
stm32_stop(lower);
}
return 0;
return 0;
}
/****************************************************************************
@ -550,21 +559,22 @@ static int stm32_start(struct timer_lowerhalf_s *lower)
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
if (!priv->started)
{
STM32_TIM_SETCLOCK(priv->tim, 1000000); // 1000000 Hz = 1 microsecond
STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP);
{
STM32_TIM_SETCLOCK(priv->tim, 1000000); /* 1000000 Hz = 1 microsecond */
STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP);
if(priv->handlerUsr)
{
STM32_TIM_SETISR(priv->tim, priv->handlerTim, 0);
STM32_TIM_ENABLEINT(priv->tim, 0);
}
if (priv->handlerUsr)
{
STM32_TIM_SETISR(priv->tim, priv->handlerTim, 0);
STM32_TIM_ENABLEINT(priv->tim, 0);
}
priv->started = true;
return OK;
}
priv->started = true;
return OK;
}
/* Return EBUSY to indicate that the timer was already running */
return -EBUSY;
}
@ -588,15 +598,16 @@ static int stm32_stop(struct timer_lowerhalf_s *lower)
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
if (priv->started)
{
STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED);
STM32_TIM_DISABLEINT(priv->tim, 0);
STM32_TIM_SETISR(priv->tim, 0, 0);
priv->started = false;
return OK;
}
{
STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED);
STM32_TIM_DISABLEINT(priv->tim, 0);
STM32_TIM_SETISR(priv->tim, 0, 0);
priv->started = false;
return OK;
}
/* Return ENODEV to indicate that the timer was not running */
return -ENODEV;
}
@ -621,9 +632,9 @@ static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout)
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
if (priv->started)
{
return -EPERM;
}
{
return -EPERM;
}
STM32_TIM_SETPERIOD(priv->tim, timeout);
return OK;
@ -647,35 +658,37 @@ static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout)
* no previous function pointer.
*
****************************************************************************/
static tccb_t stm32_sethandler(struct timer_lowerhalf_s *lower, tccb_t newhandler)
static tccb_t stm32_sethandler(struct timer_lowerhalf_s *lower,
tccb_t newhandler)
{
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
irqstate_t flags = irqsave();
/* Get the old handler return value */
tccb_t oldhandler = priv->handlerUsr;
/* Save the new handler */
priv->handlerUsr = newhandler;
if(newhandler)
{
STM32_TIM_SETISR(priv->tim, priv->handlerTim, 0);
STM32_TIM_ENABLEINT(priv->tim, 0);
}
if (newhandler)
{
STM32_TIM_SETISR(priv->tim, priv->handlerTim, 0);
STM32_TIM_ENABLEINT(priv->tim, 0);
}
else
{
STM32_TIM_DISABLEINT(priv->tim, 0);
STM32_TIM_SETISR(priv->tim, 0, 0);
}
{
STM32_TIM_DISABLEINT(priv->tim, 0);
STM32_TIM_SETISR(priv->tim, 0, 0);
}
irqrestore(flags);
return oldhandler;
}
/****************************************************************************
* Public Functions
****************************************************************************/
@ -704,28 +717,32 @@ int stm32_timer_initialize(FAR const char *devpath, int timer)
memset(lower, 0, sizeof(struct stm32_lowerhalf_s));
/* Initialize the non-zero elements of lower half state structure */
lower->ops = &g_timer_ops;
lower->handlerTim = stm32_get_interrupt(timer);
lower->tim = stm32_tim_init(timer);
if(!lower->tim)
{
return -EINVAL;
}
if (!lower->tim)
{
return -EINVAL;
}
/* Register the timer driver as /dev/timerX. The returned value from
* timer_register is a handle that could be used with timer_unregister().
* REVISIT: The returned handle is discard here.
*/
void *drvr = timer_register(devpath, (struct timer_lowerhalf_s *)lower);
if (!drvr)
{
/* The actual cause of the failure may have been a failure to allocate
* perhaps a failure to register the timer driver (such as if the
* 'depath' were not unique). We know here but we return EEXIST to
* indicate the failure (implying the non-unique devpath).
*/
return -EEXIST;
}
{
/* The actual cause of the failure may have been a failure to allocate
* perhaps a failure to register the timer driver (such as if the
* 'depath' were not unique). We know here but we return EEXIST to
* indicate the failure (implying the non-unique devpath).
*/
return -EEXIST;
}
return OK;
}

63
arch/arm/src/stm32/stm32_uid.c Normal file
View File

@ -0,0 +1,63 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_uid.c
*
* Copyright (C) 2015 Marawan Ragab. All rights reserved.
* Author: Marawan Ragab <marawan31@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <chip/stm32_memorymap.h>
#include "stm32_uid.h"
#ifdef STM32_SYSMEM_UID /* Not defined for the STM32L */
/************************************************************************************
* Public Functions
************************************************************************************/
void stm32_get_uniqueid(uint8_t uniqueid[12])
{
int i;
for (i = 0; i < 12; i++)
{
uniqueid[i] = *((uint8_t*)(STM32_SYSMEM_UID)+i);
}
}
#endif /* STM32_SYSMEM_UID */

51
arch/arm/src/stm32/stm32_uid.h Normal file
View File

@ -0,0 +1,51 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_uid.h
*
* Copyright (C) 2015 Marawan Ragab. All rights reserved.
* Author: Marawan Ragab <marawan31@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_UID_H
#define __ARCH_ARM_SRC_STM32_UID_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <stdint.h>
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
void stm32_get_uniqueid(uint8_t uniqueid[12]);
#endif /* __ARCH_ARM_SRC_STM32_UID_H */

15
arch/sim/src/up_initialize.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/sim/src/up_initialize.c
*
* Copyright (C) 2007-2009, 2011-2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2009, 2011-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -79,6 +79,7 @@ static void up_init_smartfs(void)
FAR struct mtd_dev_s *mtd;
FAR struct spi_dev_s *spi;
#ifdef CONFIG_MTD_M25P
/* Initialize a simulated SPI FLASH block device m25p MTD driver */
spi = up_spiflashinitialize();
@ -87,6 +88,18 @@ static void up_init_smartfs(void)
/* Now initialize a SMART Flash block device and bind it to the MTD device */
smart_initialize(0, mtd, NULL);
#endif
#ifdef CONFIG_MTD_W25
/* Initialize a simulated SPI FLASH block device m25p MTD driver */
spi = up_spiflashinitialize();
mtd = w25_initialize(spi);
/* Now initialize a SMART Flash block device and bind it to the MTD device */
smart_initialize(0, mtd, NULL);
#endif
}
#endif

20
arch/sim/src/up_spiflash.c
View File

@ -84,6 +84,11 @@
#ifdef CONFIG_SIM_SPIFLASH_1M
# define CONFIG_SPIFLASH_SIZE (128 * 1024)
# define CONFIG_SPIFLASH_CAPACITY 0x11
#ifndef CONFIG_SIM_SPIFLASH_SECTORSIZE
# define CONFIG_SIM_SPIFLASH_SECTORSIZE 2048
#endif
#endif
#ifdef CONFIG_SIM_SPIFLASH_8M
@ -157,6 +162,7 @@
#define SPIFLASH_STATE_READ2 14
#define SPIFLASH_STATE_READ3 15
#define SPIFLASH_STATE_READ4 16
#define SPIFLASH_STATE_FREAD_WAIT 17
/* Instructions */
/* Command Value N Description Addr Dummy Data */
@ -666,6 +672,7 @@ static void spiflash_writeword(FAR struct sim_spiflashdev_s *priv, uint16_t data
break;
case SPIFLASH_READ:
case SPIFLASH_FAST_READ:
priv->state = SPIFLASH_STATE_READ1;
break;
@ -780,6 +787,18 @@ static void spiflash_writeword(FAR struct sim_spiflashdev_s *priv, uint16_t data
case SPIFLASH_STATE_READ3:
priv->address |= data;
if (priv->last_cmd == SPIFLASH_FAST_READ)
{
priv->state = SPIFLASH_STATE_FREAD_WAIT;
}
else
{
priv->state = SPIFLASH_STATE_READ4;
}
break;
case SPIFLASH_STATE_FREAD_WAIT:
priv->read_data = 0xff;
priv->state = SPIFLASH_STATE_READ4;
break;
@ -850,6 +869,7 @@ FAR struct spi_dev_s *up_spiflashinitialize()
priv->state = SPIFLASH_STATE_IDLE;
priv->read_data = 0xFF;
priv->last_cmd = 0xFF;
memset(&priv->data[0], 0xFF, sizeof(priv->data));
irqrestore(flags);
return (FAR struct spi_dev_s *)priv;