sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

arch/armv8-m: Update per the latest architecture reference manual

Browse Source 
https://developer.arm.com/documentation/ddi0553/latest

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2021-08-06 12:13:44 +08:00 committed by Alin Jerpelea
parent 35379403f8
commit f0001574ed
7 changed files with 393 additions and 459 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

273
arch/arm/src/armv8-m/arm_mpu.c
View File

@ -44,30 +44,6 @@
* Private Data
****************************************************************************/
/* These sets represent the set of disabled memory sub-regions. A bit set
* corresponds to a disabled sub-region; the LS bit corresponds to the first
* region.
*
* The g_ms_regionmask array is indexed by the number of subregions at the
* end of the region: 0 means no sub-regions are available(0xff) and 8 means
* all subregions are available (0x00).
*/
static const uint8_t g_ms_regionmask[9] =
{
0xff, 0xfe, 0xfc, 0xf8, 0xf0, 0xe0, 0xc0, 0x80, 0x00
};
/* The g_ls_regionmask array is indexed by the number of subregions at the
* beginning of the region: 0 means no sub-regions need be disabled (0x00)
* and 8 means all subregions must be disabled (0xff).
*/
static const uint8_t g_ls_regionmask[9] =
{
0x00, 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff
};
/* The next available region number */
static uint8_t g_region;
@ -76,111 +52,6 @@ static uint8_t g_region;
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: mpu_subregion_ms
*
* Description:
* Given (1) the size of the memory to be mapped and (2) the log2 size
* of the mapping to use, determine the minimal sub-region set at the
* to be disabled at the higher end of the region.
*
* Assumption:
* l2size has the same properties as the return value from
* mpu_log2regionceil()
*
****************************************************************************/
static inline uint32_t mpu_subregion_ms(size_t size, uint8_t l2size)
{
unsigned int nsrs;
uint32_t asize;
uint32_t mask;
/* Examples with l2size = 12:
*
* Shifted Adjusted Number Sub-Region
* Size Mask Size Shift Sub-Regions Bitset
* 0x1000 0x01ff 0x1000 9 8 0x00
* 0x0c00 0x01ff 0x0c00 9 6 0xc0
* 0x0c40 0x01ff 0x0e00 9 7 0x80
*/
if (l2size < 32)
{
mask = ((1 << l2size) - 1) >> 3; /* Shifted mask */
}
/* The 4Gb region size is a special case */
else
{
/* NOTE: There is no way to represent a 4Gb region size in the 32-bit
* input.
*/
mask = 0x1fffffff; /* Shifted mask */
}
asize = (size + mask) & ~mask; /* Adjusted size */
nsrs = asize >> (l2size - 3); /* Number of subregions */
return g_ms_regionmask[nsrs];
}
/****************************************************************************
* Name: mpu_subregion_ls
*
* Description:
* Given (1) the offset to the beginning of data in the region and (2) the
* log2 size of the mapping to use, determine the minimal sub-region set
* to span that memory region sub-region set at the to be disabled at the
* lower end of the region
*
* Assumption:
* l2size has the same properties as the return value from
* mpu_log2regionceil()
*
****************************************************************************/
static inline uint32_t mpu_subregion_ls(size_t offset, uint8_t l2size)
{
unsigned int nsrs;
uint32_t aoffset;
uint32_t mask;
/* Examples with l2size = 12:
*
* Shifted Adjusted Number Sub-Region
* Offset Mask Offset Shift Sub-Regions Bitset
* 0x0000 0x01ff 0x0000 9 8 0x00
* 0x0400 0x01ff 0x0400 9 6 0x03
* 0x02c0 0x01ff 0x0200 9 7 0x01
*/
if (l2size < 32)
{
mask = ((1 << l2size)-1) >> 3; /* Shifted mask */
}
/* The 4Gb region size is a special case */
else
{
/* NOTE: There is no way to represent a 4Gb region size in the 32-bit
* input.
*/
mask = 0x1fffffff; /* Shifted mask */
}
aoffset = offset & ~mask; /* Adjusted offset */
nsrs = aoffset >> (l2size - 3); /* Number of subregions */
return g_ls_regionmask[nsrs];
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: mpu_allocregion
*
@ -201,106 +72,9 @@ unsigned int mpu_allocregion(void)
}
/****************************************************************************
* Name: mpu_log2regionceil
*
* Description:
* Determine the smallest value of l2size (log base 2 size) such that the
* following is true:
*
* size <= (1 << l2size)
*
* Public Functions
****************************************************************************/
uint8_t mpu_log2regionceil(size_t size)
{
uint8_t l2size;
/* The minimum permitted region size is 32 bytes (log2(32) = 5. */
for (l2size = 5; l2size < 32 && size > (1 << l2size); l2size++);
return l2size;
}
/****************************************************************************
* Name: mpu_log2regionfloor
*
* Description:
* Determine the largest value of l2size (log base 2 size) such that the
* following is true:
*
* size >= (1 << l2size)
*
****************************************************************************/
uint8_t mpu_log2regionfloor(size_t size)
{
uint8_t l2size = mpu_log2regionceil(size);
if (l2size > 4 && size < (1 << l2size))
{
l2size--;
}
return l2size;
}
/****************************************************************************
* Name: mpu_subregion
*
* Description:
* Given the size of the (1) memory to be mapped and (2) the log2 size
* of the mapping to use, determine the minimal sub-region set to span
* that memory region.
*
* Assumption:
* l2size has the same properties as the return value from
* mpu_log2regionceil()
*
****************************************************************************/
uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size)
{
uint32_t mask;
size_t offset;
uint32_t ret;
/* Eight subregions are supported. The representation is as an 8-bit
* value with the LS bit corresponding to subregion 0. A bit is set
* to disable the sub-region.
*
* l2size: Log2 of the actual region size is <= (1 << l2size);
*/
DEBUGASSERT(l2size > 4 && size <= (1 << l2size));
/* For region sizes of 32, 64, and 128 bytes, the effect of setting
* one or more bits of the SRD field to 1 is UNPREDICTABLE.
*/
if (l2size < 8)
{
return 0;
}
/* Calculate the offset of the base address into the aligned region. */
mask = (1 << l2size) - 1;
offset = base & mask;
/* Calculate the mask need to handle disabled subregions at the end of the
* region
*/
ret = mpu_subregion_ms(size + offset, l2size);
/* Then OR in the mask need to handle disabled subregions at the beginning
* of the region.
*/
ret |= mpu_subregion_ls(offset, l2size);
return ret;
}
/****************************************************************************
* Name: mpu_control
*
@ -313,6 +87,15 @@ void mpu_control(bool enable, bool hfnmiena, bool privdefena)
{
uint32_t regval = 0;
putreg32((MPU_MAIR_STRONGLY_ORDER << 0) |
(MPU_MAIR_DEVICE << 8) |
(MPU_MAIR_NONCACHEABLE << 16) |
(MPU_MAIR_WRITE_THROUGH << 24),
MPU_MAIR0);
putreg32((MPU_MAIR_WRITE_BACK << 0),
MPU_MAIR1);
if (enable)
{
regval |= MPU_CTRL_ENABLE; /* Enable the MPU */
@ -340,13 +123,10 @@ void mpu_control(bool enable, bool hfnmiena, bool privdefena)
****************************************************************************/
void mpu_configure_region(uintptr_t base, size_t size,
uint32_t flags)
uint32_t flags1, uint32_t flags2)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
uint8_t l2size;
uint8_t subregions;
uintptr_t alignedbase;
uintptr_t limit;
/* Ensure the base address alignment
*
@ -356,34 +136,15 @@ void mpu_configure_region(uintptr_t base, size_t size,
* aligns with the size of the selected region."
*/
alignedbase = base & MPU_RBAR_ADDR_MASK;
l2size = mpu_log2regionceil(size + base - alignedbase);
alignedbase &= ~((1 << l2size) - 1);
l2size = mpu_log2regionceil(size + base - alignedbase);
DEBUGASSERT(alignedbase + (1 << l2size) >= base + size);
DEBUGASSERT(l2size == 5 ||
alignedbase + (1 << (l2size - 1)) < base + size);
DEBUGASSERT((alignedbase & MPU_RBAR_ADDR_MASK) == alignedbase);
DEBUGASSERT((alignedbase & ((1 << l2size) - 1)) == 0);
limit = (base + size) & MPU_RLAR_LIMIT_MASK;
base &= MPU_RBAR_BASE_MASK;
/* Select the region */
putreg32(region, MPU_RNR);
/* Select the region base address */
/* Set the region base, limit and attribute */
putreg32(alignedbase | region | MPU_RBAR_VALID, MPU_RBAR);
/* Select the region size and the sub-region map */
subregions = mpu_subregion(base, size, l2size);
/* The configure the region */
regval = MPU_RASR_ENABLE | /* Enable region */
MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */
((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */
flags;
putreg32(regval, MPU_RASR);
putreg32(base | flags1, MPU_RBAR);
putreg32(limit | flags2 | MPU_RLAR_ENABLE, MPU_RLAR);
}

43
arch/arm/src/armv8-m/dwt.h
View File

@ -85,17 +85,50 @@
#define DWT_FOLDCNT (DWT_BASE + 0x0018) /* Folded-instruction Count Register */
#define DWT_PCSR (DWT_BASE + 0x001c) /* Program Counter Sample Register */
#define DWT_COMP0 (DWT_BASE + 0x0020) /* Comparator Register 0 */
#define DWT_MASK0 (DWT_BASE + 0x0024) /* Mask Register 0 */
#define DWT_FUNCTION0 (DWT_BASE + 0x0028) /* Function Register 0 */
#define DWT_MASK0 (DWT_BASE + 0x002c) /* Mask Register 0 */
#define DWT_COMP1 (DWT_BASE + 0x0030) /* Comparator Register 1 */
#define DWT_MASK1 (DWT_BASE + 0x0034) /* Mask Register 1 */
#define DWT_FUNCTION1 (DWT_BASE + 0x0038) /* Function Register 1 */
#define DWT_MASK1 (DWT_BASE + 0x003c) /* Mask Register 1 */
#define DWT_COMP2 (DWT_BASE + 0x0040) /* Comparator Register 2 */
#define DWT_MASK2 (DWT_BASE + 0x0044) /* Mask Register 2 */
#define DWT_FUNCTION2 (DWT_BASE + 0x0048) /* Function Register 2 */
#define DWT_MASK2 (DWT_BASE + 0x004c) /* Mask Register 2 */
#define DWT_COMP3 (DWT_BASE + 0x0050) /* Comparator Register 3 */
#define DWT_MASK3 (DWT_BASE + 0x0054) /* Mask Register 3 */
#define DWT_FUNCTION3 (DWT_BASE + 0x0058) /* Function Register 3 */
#define DWT_MASK3 (DWT_BASE + 0x005c) /* Mask Register 3 */
#define DWT_COMP4 (DWT_BASE + 0x0060) /* Comparator Register 4 */
#define DWT_FUNCTION4 (DWT_BASE + 0x0068) /* Function Register 4 */
#define DWT_MASK4 (DWT_BASE + 0x006c) /* Mask Register 4 */
#define DWT_COMP5 (DWT_BASE + 0x0070) /* Comparator Register 5 */
#define DWT_FUNCTION5 (DWT_BASE + 0x0078) /* Function Register 5 */
#define DWT_MASK5 (DWT_BASE + 0x007c) /* Mask Register 5 */
#define DWT_COMP6 (DWT_BASE + 0x0080) /* Comparator Register 6 */
#define DWT_FUNCTION6 (DWT_BASE + 0x0088) /* Function Register 6 */
#define DWT_MASK6 (DWT_BASE + 0x008c) /* Mask Register 6 */
#define DWT_COMP7 (DWT_BASE + 0x0090) /* Comparator Register 7 */
#define DWT_FUNCTION7 (DWT_BASE + 0x0098) /* Function Register 7 */
#define DWT_MASK7 (DWT_BASE + 0x009c) /* Mask Register 7 */
#define DWT_COMP8 (DWT_BASE + 0x00a0) /* Comparator Register 8 */
#define DWT_FUNCTION8 (DWT_BASE + 0x00a8) /* Function Register 8 */
#define DWT_MASK8 (DWT_BASE + 0x00ac) /* Mask Register 8 */
#define DWT_COMP9 (DWT_BASE + 0x00b0) /* Comparator Register 9 */
#define DWT_FUNCTION9 (DWT_BASE + 0x00b8) /* Function Register 9 */
#define DWT_MASK9 (DWT_BASE + 0x00bc) /* Mask Register 9 */
#define DWT_COMP10 (DWT_BASE + 0x00c0) /* Comparator Register 10 */
#define DWT_FUNCTION10 (DWT_BASE + 0x00c8) /* Function Register 10 */
#define DWT_MASK10 (DWT_BASE + 0x00cc) /* Mask Register 10 */
#define DWT_COMP11 (DWT_BASE + 0x00d0) /* Comparator Register 11 */
#define DWT_FUNCTION11 (DWT_BASE + 0x00d8) /* Function Register 11 */
#define DWT_MASK11 (DWT_BASE + 0x00dc) /* Mask Register 11 */
#define DWT_COMP12 (DWT_BASE + 0x00e0) /* Comparator Register 12 */
#define DWT_FUNCTION12 (DWT_BASE + 0x00e8) /* Function Register 12 */
#define DWT_MASK12 (DWT_BASE + 0x00ec) /* Mask Register 12 */
#define DWT_COMP13 (DWT_BASE + 0x00f0) /* Comparator Register 13 */
#define DWT_FUNCTION13 (DWT_BASE + 0x00f8) /* Function Register 13 */
#define DWT_MASK13 (DWT_BASE + 0x00fc) /* Mask Register 13 */
#define DWT_COMP14 (DWT_BASE + 0x0100) /* Comparator Register 14 */
#define DWT_FUNCTION14 (DWT_BASE + 0x0108) /* Function Register 14 */
#define DWT_MASK14 (DWT_BASE + 0x010c) /* Mask Register 14 */
/* DWT Register Bit Field Definitions ***************************************/
@ -111,6 +144,8 @@
#define DWT_CTRL_NOCYCCNT_MASK (0x1ul << DWT_CTRL_NOCYCCNT_SHIFT)
#define DWT_CTRL_NOPRFCNT_SHIFT 24
#define DWT_CTRL_NOPRFCNT_MASK (0x1ul << DWT_CTRL_NOPRFCNT_SHIFT)
#define DWT_CTRL_CYCDISS_SHIFT 23
#define DWT_CTRL_CYCDISS_MASK (0x1ul << DWT_CTRL_CYCDISS_SHIFT)
#define DWT_CTRL_CYCEVTENA_SHIFT 22
#define DWT_CTRL_CYCEVTENA_MASK (0x1ul << DWT_CTRL_CYCEVTENA_SHIFT)
#define DWT_CTRL_FOLDEVTENA_SHIFT 21

30
arch/arm/src/armv8-m/exc_return.h
View File

@ -90,11 +90,11 @@
/* EXC_RETURN_BASE: Bits that are always set in an EXC_RETURN value. */
#if !defined(CONFIG_ARCH_TRUSTZONE_NONSECURE)
#ifdef CONFIG_ARCH_TRUSTZONE_NONSECURE
#define EXC_RETURN_BASE (0xffffff80)
#else
#define EXC_RETURN_BASE (0xffffff80 | EXC_RETURN_EXC_SECURE | \
EXC_RETURN_SECURE_STACK)
#else
#define EXC_RETURN_BASE (0xffffff80)
#endif
/* EXC_RETURN_HANDLER: Return to handler mode. Exception return gets state
@ -129,6 +129,30 @@
EXC_RETURN_DEF_STACKING)
#endif
#if defined(CONFIG_ARCH_FPU)
#define EXC_INTEGRITY_SIGNATURE (0xfefa125a)
#else
#define EXC_INTEGRITY_SIGNATURE (0xfefa125b)
#endif
/* FUNC_RETURN_EXC_SECURE: Exception Secure. The security domain the
* function was taken to. If this bit is clear non-secure, else secure.
*/
#define FUNC_RETURN_EXC_SECURE (1 << 0)
/* FUNC_RETURN_BASE: Bits that are always set in a FUNC_RETURN value. */
#define FUNC_RETURN_BASE (0xfefffffe)
/* FUNC_RETURN_SECURE: Return to the secure state. */
#define FUNC_RETURN_SECURE (FUNC_RETURN_BASE | FUNC_RETURN_EXC_SECURE)
/* FUNC_RETURN_NONSECURE: Return to the non-secure state. */
#define FUNC_RETURN_NONSECURE (FUNC_RETURN_BASE)
/****************************************************************************
* Inline Functions
****************************************************************************/

13
arch/arm/src/armv8-m/fpb.h
View File

@ -29,7 +29,7 @@
/* FPB Register Base Address ************************************************/
#define FPB_BASE 0xe0002000
#define FPB_BASE 0xe0002000
/* FPB Register Offsets *****************************************************/
@ -70,7 +70,7 @@
*/
#define FPB_CTRL_NUM_CODE2_SHIFT 12
#define FPB_CTRL_NUM_CODE2_MASK 0x00003000
#define FPB_CTRL_NUM_CODE2_MASK 0x00007000
/* NUM_LIT
*
@ -127,6 +127,15 @@
#define FPB_REMAP_REMAP_SHIFT 5
#define FPB_REMAP_REMAP_MASK 0x1fffffe0
/* REMAP
*
* Remap supported field.
*/
#define FPB_REMAP_RMPSPT_SHIFT 29
#define FPB_REMAP_RMPSPT_MASK 0x20000000
# define FPB_REMAP_RMPSPT 0x20000000
/* FPB_COMP0 - FPB_COMP7 */
/* REPLACE

287
arch/arm/src/armv8-m/mpu.h
View File

@ -41,20 +41,48 @@
* Pre-processor Definitions
****************************************************************************/
/* MPU Register Bases */
#define MPU_BASE 0xe000ed90
#define MPU_BASE_NS 0xe002ed90
/* MPU Register Offsets */
#define MPU_TYPE_OFFSET 0x0000 /* MPU Type Register */
#define MPU_CTRL_OFFSET 0x0004 /* MPU Control Register */
#define MPU_RNR_OFFSET 0x0008 /* MPU Region Number Register */
#define MPU_RBAR_OFFSET 0x000c /* MPU Region Base Address Register */
#define MPU_RLAR_OFFSET 0x0010 /* MPU Region Limit Address Register */
#define MPU_RBAR_A1_OFFSET 0x0014 /* MPU alias registers */
#define MPU_RLAR_A1_OFFSET 0x0018
#define MPU_RBAR_A2_OFFSET 0x001c
#define MPU_RLAR_A2_OFFSET 0x0020
#define MPU_RBAR_A3_OFFSET 0x0024
#define MPU_RLAR_A3_OFFSET 0x0028
#define MPU_MAIR_OFFSET(n) (0x0040 + 4 * ((n) >> 2))
#define MPU_MAIR0_OFFSET 0x0040 /* MPU Memory Attribute Indirection Register 0 */
#define MPU_MAIR1_OFFSET 0x0044 /* MPU Memory Attribute Indirection Register 1 */
/* MPU Register Addresses */
#define MPU_TYPE 0xe000ed90 /* MPU Type Register */
#define MPU_CTRL 0xe000ed94 /* MPU Control Register */
#define MPU_RNR 0xe000ed98 /* MPU Region Number Register */
#define MPU_RBAR 0xe000ed9c /* MPU Region Base Address Register */
#define MPU_RASR 0xe000eda0 /* MPU Region Attribute and Size Register */
#define MPU_TYPE (MPU_BASE + MPU_TYPE_OFFSET)
#define MPU_CTRL (MPU_BASE + MPU_CTRL_OFFSET)
#define MPU_RNR (MPU_BASE + MPU_RNR_OFFSET)
#define MPU_RBAR (MPU_BASE + MPU_RBAR_OFFSET)
#define MPU_RLAR (MPU_BASE + MPU_RLAR_OFFSET)
#define MPU_RBAR_A1 0xe000eda4 /* MPU alias registers */
#define MPU_RASR_A1 0xe000eda8
#define MPU_RBAR_A2 0xe000edac
#define MPU_RASR_A2 0xe000edb0
#define MPU_RBAR_A3 0xe000edb4
#define MPU_RASR_A3 0xe000edb8
#define MPU_RBAR_A1 (MPU_BASE + MPU_RBAR_A1_OFFSET)
#define MPU_RLAR_A1 (MPU_BASE + MPU_RLAR_A1_OFFSET)
#define MPU_RBAR_A2 (MPU_BASE + MPU_RBAR_A2_OFFSET)
#define MPU_RLAR_A2 (MPU_BASE + MPU_RLAR_A2_OFFSET)
#define MPU_RBAR_A3 (MPU_BASE + MPU_RBAR_A3_OFFSET)
#define MPU_RLAR_A3 (MPU_BASE + MPU_RLAR_A3_OFFSET)
#define MPU_MAIR(n) (MPU_BASE + MPU_MAIR_OFFSET(n))
#define MPU_MAIR0 (MPU_BASE + MPU_MAIR0_OFFSET)
#define MPU_MAIR1 (MPU_BASE + MPU_MAIR1_OFFSET)
/* MPU Type Register Bit Definitions */
@ -86,51 +114,62 @@
/* MPU Region Base Address Register Bit Definitions */
#define MPU_RBAR_REGION_SHIFT (0) /* Bits 0-3: MPU region */
#define MPU_RBAR_REGION_MASK (15 << MPU_RBAR_REGION_SHIFT)
#define MPU_RBAR_VALID (1 << 4) /* Bit 4: MPU Region Number valid */
#define MPU_RBAR_ADDR_MASK 0xffffffe0 /* Bits N-31: Region base addrese */
#define MPU_RBAR_XN (1 << 0) /* Bit 0: Execute never */
#define MPU_RBAR_AP_SHIFT (1) /* Bits 1-2: Access permission */
#define MPU_RBAR_AP_MASK (3 << MPU_RBAR_AP_SHIFT)
# define MPU_RBAR_AP_RWNO (0 << MPU_RBAR_AP_SHIFT) /* P:RW U:None */
# define MPU_RBAR_AP_RWRW (1 << MPU_RBAR_AP_SHIFT) /* P:RW U:RW */
# define MPU_RBAR_AP_RONO (2 << MPU_RBAR_AP_SHIFT) /* P:RO U:None */
# define MPU_RBAR_AP_RORO (3 << MPU_RBAR_AP_SHIFT) /* P:RO U:RO */
#define MPU_RBAR_SH_SHIFT (3) /* Bits 3-4: Shareability */
#define MPU_RBAR_SH_MASK (3 << MPU_RBAR_SH_SHIFT)
# define MPU_RBAR_SH_NO (0 << MPU_RBAR_SH_SHIFT) /* Non-shareable */
# define MPU_RBAR_SH_OUTER (2 << MPU_RBAR_SH_SHIFT) /* Outer shareable */
# define MPU_RBAR_SH_INNER (3 << MPU_RBAR_SH_SHIFT) /* Inner shareable */
#define MPU_RBAR_BASE_MASK 0xffffffe0 /* Bits 5-31: Region base addrese */
/* MPU Region Attributes and Size Register Bit Definitions */
/* MPU Region Region Limit Address Register Bit Definitions */
#define MPU_RASR_ENABLE (1 << 0) /* Bit 0: Region enable */
#define MPU_RASR_SIZE_SHIFT (1) /* Bits 1-5: Size of the MPU protection region */
#define MPU_RASR_SIZE_MASK (31 << MPU_RASR_SIZE_SHIFT)
# define MPU_RASR_SIZE_LOG2(n) ((n-1) << MPU_RASR_SIZE_SHIFT)
#define MPU_RASR_SRD_SHIFT (8) /* Bits 8-15: Subregion disable */
#define MPU_RASR_SRD_MASK (0xff << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_0 (0x01 << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_1 (0x02 << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_2 (0x04 << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_3 (0x08 << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_4 (0x10 << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_5 (0x20 << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_6 (0x40 << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_7 (0x80 << MPU_RASR_SRD_SHIFT)
#define MPU_RASR_ATTR_SHIFT (16) /* Bits 16-31: MPU Region Attribute field */
#define MPU_RASR_ATTR_MASK (0xffff << MPU_RASR_ATTR_SHIFT)
# define MPU_RASR_B (1 << 16) /* Bit 16: Bufferable */
# define MPU_RASR_C (1 << 17) /* Bit 17: Cacheable */
# define MPU_RASR_S (1 << 18) /* Bit 18: Shareable */
# define MPU_RASR_TEX_SHIFT (19) /* Bits 19-21: TEX Address Permission */
# define MPU_RASR_TEX_MASK (7 << MPU_RASR_TEX_SHIFT)
# define MPU_RASR_TEX_SO (0 << MPU_RASR_TEX_SHIFT) /* Strongly Ordered */
# define MPU_RASR_TEX_NOR (1 << MPU_RASR_TEX_SHIFT) /* Normal */
# define MPU_RASR_TEX_DEV (2 << MPU_RASR_TEX_SHIFT) /* Device */
# define MPU_RASR_TEX_BB(bb) ((4|(bb)) << MPU_RASR_TEX_SHIFT)
# define MPU_RASR_CP_NC (0) /* Non-cacheable */
# define MPU_RASR_CP_WBRA (1) /* Write back, write and Read- Allocate */
# define MPU_RASR_CP_WT (2) /* Write through, no Write-Allocate */
# define MPU_RASR_CP_WB (4) /* Write back, no Write-Allocate */
# define MPU_RASR_AP_SHIFT (24) /* Bits 24-26: Access permission */
# define MPU_RASR_AP_MASK (7 << MPU_RASR_AP_SHIFT)
# define MPU_RASR_AP_NONO (0 << MPU_RASR_AP_SHIFT) /* P:None U:None */
# define MPU_RASR_AP_RWNO (1 << MPU_RASR_AP_SHIFT) /* P:RW U:None */
# define MPU_RASR_AP_RWRO (2 << MPU_RASR_AP_SHIFT) /* P:RW U:RO */
# define MPU_RASR_AP_RWRW (3 << MPU_RASR_AP_SHIFT) /* P:RW U:RW */
# define MPU_RASR_AP_RONO (5 << MPU_RASR_AP_SHIFT) /* P:RO U:None */
# define MPU_RASR_AP_RORO (6 << MPU_RASR_AP_SHIFT) /* P:RO U:RO */
# define MPU_RASR_XN (1 << 28) /* Bit 28: Instruction access disable */
#define MPU_RLAR_ENABLE (1 << 0) /* Bit 0: Region enable */
#define MPU_RLAR_INDX_SHIFT (1) /* Bits 1-3: Attribute index */
#define MPU_RLAR_INDX_MASK (7 << MPU_RLAR_INDX_SHIFT)
#define MPU_RLAR_STRONGLY_ORDER (0 << MPU_RLAR_INDX_SHIFT)
#define MPU_RLAR_DEVICE (1 << MPU_RLAR_INDX_SHIFT)
#define MPU_RLAR_NONCACHEABLE (2 << MPU_RLAR_INDX_SHIFT)
#define MPU_RLAR_WRITE_THROUGH (3 << MPU_RLAR_INDX_SHIFT)
#define MPU_RLAR_WRITE_BACK (4 << MPU_RLAR_INDX_SHIFT)
#define MPU_RLAR_PXN (1 << 4) /* Bit 4: Privileged execute never */
#define MPU_RLAR_LIMIT_MASK 0xffffffe0 /* Bits 5-31: Region limit address */
/* MPU Memory Attribute Indirection Register Bit Definitions */
#define MPU_MAIR_INNER_WA (1 << 0) /* Bit 0: Inner write allocation */
#define MPU_MAIR_INNER_RA (1 << 1) /* Bit 1: Inner read allocation */
#define MPU_MAIR_INNER_WB (1 << 2) /* Bit 2: Inner write back */
#define MPU_MAIR_INNER_NT (1 << 3) /* Bit 3: Inner non-transient */
#define MPU_MAIR_INNER_NC (4 << 0) /* Bit 0-3: Inner non-cacheable */
#define MPU_MAIR_INNER_NGNRNE (0 << 2) /* Bit 2-3: Inner nGnRnE */
#define MPU_MAIR_INNER_NGNRE (1 << 2) /* Bit 2-3: Inner nGnRE */
#define MPU_MAIR_INNER_NGRE (2 << 2) /* Bit 2-3: Inner nGRE */
#define MPU_MAIR_INNER_GRE (3 << 2) /* Bit 2-3: Inner GRE */
#define MPU_MAIR_OUTER_WA (1 << 4) /* Bit 4: Outer write allocation */
#define MPU_MAIR_OUTER_RA (1 << 5) /* Bit 5: Outer read allocation */
#define MPU_MAIR_OUTER_WB (1 << 6) /* Bit 6: Outer write back */
#define MPU_MAIR_OUTER_NT (1 << 7) /* Bit 7: Outer non-transient */
#define MPU_MAIR_OUTER_DEVICE (0 << 4) /* Bit 4-7: Outer device */
#define MPU_MAIR_OUTER_NC (4 << 4) /* Bit 4-7: Outer non-cacheable */
#define MPU_MAIR_STRONGLY_ORDER (MPU_MAIR_OUTER_DEVICE | MPU_MAIR_INNER_NGNRNE)
#define MPU_MAIR_DEVICE (MPU_MAIR_OUTER_DEVICE | MPU_MAIR_INNER_NGNRE)
#define MPU_MAIR_NONCACHEABLE (MPU_MAIR_OUTER_NC | MPU_MAIR_INNER_NC)
#define MPU_MAIR_WRITE_THROUGH (MPU_MAIR_OUTER_NT | MPU_MAIR_OUTER_RA | \
MPU_MAIR_OUTER_WA | MPU_MAIR_INNER_NT | \
MPU_MAIR_INNER_RA | MPU_MAIR_INNER_WA)
#define MPU_MAIR_WRITE_BACK (MPU_MAIR_OUTER_NT | MPU_MAIR_OUTER_WB | \
MPU_MAIR_OUTER_RA | MPU_MAIR_OUTER_WA | \
MPU_MAIR_INNER_NT | MPU_MAIR_INNER_WB | \
MPU_MAIR_INNER_RA | MPU_MAIR_INNER_WA)
#ifdef CONFIG_ARM_MPU
@ -148,58 +187,6 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Name: mpu_allocregion
*
* Description:
* Allocate the next region
*
****************************************************************************/
unsigned int mpu_allocregion(void);
/****************************************************************************
* Name: mpu_log2regionceil
*
* Description:
* Determine the smallest value of l2size (log base 2 size) such that the
* following is true:
*
* size <= (1 << l2size)
*
****************************************************************************/
uint8_t mpu_log2regionceil(size_t size);
/****************************************************************************
* Name: mpu_log2regionfloor
*
* Description:
* Determine the largest value of l2size (log base 2 size) such that the
* following is true:
*
* size >= (1 << l2size)
*
****************************************************************************/
uint8_t mpu_log2regionfloor(size_t size);
/****************************************************************************
* Name: mpu_subregion
*
* Description:
* Given (1) the offset to the beginning of valid data, (2) the size of the
* memory to be mapped and (2) the log2 size of the mapping to use,
* determine the minimal sub-region set to span that memory region.
*
* Assumption:
* l2size has the same properties as the return value from
* mpu_log2regionceil()
*
****************************************************************************/
uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size);
/****************************************************************************
* Name: mpu_control
*
@ -219,7 +206,7 @@ void mpu_control(bool enable, bool hfnmiena, bool privdefena);
****************************************************************************/
void mpu_configure_region(uintptr_t base, size_t size,
uint32_t flags);
uint32_t flags1, uint32_t flags2);
/****************************************************************************
* Inline Functions
@ -260,12 +247,9 @@ void mpu_configure_region(uintptr_t base, size_t size,
{ \
/* The configure the region */ \
mpu_configure_region(base, size, \
MPU_RASR_TEX_SO | /* Ordered */ \
/* Not Cacheable */ \
/* Not Bufferable */ \
MPU_RASR_S | /* Shareable */ \
MPU_RASR_AP_RWNO /* P:RW U:None */ \
/* Instruction access */); \
MPU_RBAR_AP_RWNO, \
MPU_RLAR_STRONGLY_ORDER | \
MPU_RLAR_PXN); \
} while (0)
/****************************************************************************
@ -281,12 +265,8 @@ void mpu_configure_region(uintptr_t base, size_t size,
{ \
/* The configure the region */ \
mpu_configure_region(base, size, \
MPU_RASR_TEX_SO | /* Ordered */ \
MPU_RASR_C | /* Cacheable */ \
/* Not Bufferable */ \
/* Not Shareable */ \
MPU_RASR_AP_RORO /* P:RO U:RO */ \
/* Instruction access */); \
MPU_RBAR_AP_RORO, \
MPU_RLAR_WRITE_BACK); \
} while (0)
/****************************************************************************
@ -302,12 +282,8 @@ void mpu_configure_region(uintptr_t base, size_t size,
{ \
/* The configure the region */ \
mpu_configure_region(base, size, \
MPU_RASR_TEX_SO | /* Ordered */ \
MPU_RASR_C | /* Cacheable */ \
/* Not Bufferable */ \
/* Not Shareable */ \
MPU_RASR_AP_RONO /* P:RO U:None */ \
/* Instruction access */); \
MPU_RBAR_AP_RONO, \
MPU_RLAR_WRITE_BACK); \
} while (0)
/****************************************************************************
@ -323,12 +299,10 @@ void mpu_configure_region(uintptr_t base, size_t size,
{ \
/* The configure the region */ \
mpu_configure_region(base, size, \
MPU_RASR_TEX_SO | /* Ordered */ \
MPU_RASR_C | /* Cacheable */ \
/* Not Bufferable */ \
MPU_RASR_S | /* Shareable */ \
MPU_RASR_AP_RWRW /* P:RW U:RW */ \
/* Instruction access */); \
MPU_RBAR_XN | \
MPU_RBAR_AP_RWRW, \
MPU_RLAR_NONCACHEABLE | \
MPU_RLAR_PXN); \
} while (0)
/****************************************************************************
@ -343,13 +317,10 @@ void mpu_configure_region(uintptr_t base, size_t size,
do \
{ \
/* The configure the region */ \
mpu_configure_region(base, size,\
MPU_RASR_TEX_SO | /* Ordered */ \
MPU_RASR_C | /* Cacheable */ \
/* Not Bufferable */ \
MPU_RASR_S | /* Shareable */ \
MPU_RASR_AP_RWNO /* P:RW U:None */ \
/* Instruction access */); \
mpu_configure_region(base, size, \
MPU_RBAR_AP_RWNO, \
MPU_RLAR_NONCACHEABLE | \
MPU_RLAR_PXN); \
} while (0)
/****************************************************************************
@ -365,12 +336,11 @@ void mpu_configure_region(uintptr_t base, size_t size,
{ \
/* The configure the region */ \
mpu_configure_region(base, size, \
MPU_RASR_TEX_SO | /* Ordered */ \
MPU_RASR_C | /* Cacheable */ \
MPU_RASR_B | /* Bufferable */ \
MPU_RASR_S | /* Shareable */ \
MPU_RASR_AP_RWRW /* P:RW U:RW */ \
/* Instruction access */); \
MPU_RBAR_XN | \
MPU_RBAR_AP_RWRW | \
MPU_RBAR_SH_OUTER, \
MPU_RLAR_WRITE_BACK | \
MPU_RLAR_PXN); \
} while (0)
/****************************************************************************
@ -386,12 +356,10 @@ void mpu_configure_region(uintptr_t base, size_t size,
{ \
/* The configure the region */ \
mpu_configure_region(base, size, \
MPU_RASR_TEX_SO | /* Ordered */ \
MPU_RASR_C | /* Cacheable */ \
MPU_RASR_B | /* Bufferable */ \
MPU_RASR_S | /* Shareable */ \
MPU_RASR_AP_RWNO /* P:RW U:None */ \
/* Instruction access */); \
MPU_RBAR_AP_RWNO | \
MPU_RBAR_SH_OUTER, \
MPU_RLAR_WRITE_BACK | \
MPU_RLAR_PXN); \
} while (0)
/****************************************************************************
@ -407,12 +375,9 @@ void mpu_configure_region(uintptr_t base, size_t size,
{ \
/* Then configure the region */ \
mpu_configure_region(base, size, \
MPU_RASR_TEX_DEV | /* Device */ \
/* Not Cacheable */ \
MPU_RASR_B | /* Bufferable */ \
MPU_RASR_S | /* Shareable */ \
MPU_RASR_AP_RWNO | /* P:RW U:None */ \
MPU_RASR_XN /* No Instruction access */); \
MPU_RBAR_AP_RWNO, \
MPU_RLAR_DEVICE | \
MPU_RLAR_PXN); \
} while (0)
/****************************************************************************
@ -428,12 +393,10 @@ void mpu_configure_region(uintptr_t base, size_t size,
{ \
/* Then configure the region */ \
mpu_configure_region(base, size, \
MPU_RASR_TEX_DEV | /* Device */ \
/* Not Cacheable */ \
MPU_RASR_B | /* Bufferable */ \
MPU_RASR_S | /* Shareable */ \
MPU_RASR_AP_RWRW | /* P:RW U:RW */ \
MPU_RASR_XN /* No Instruction access */); \
MPU_RBAR_XN | \
MPU_RBAR_AP_RWRW, \
MPU_RLAR_DEVICE | \
MPU_RLAR_PXN); \
} while (0)
#undef EXTERN

154
arch/arm/src/armv8-m/nvic.h
View File

@ -43,7 +43,8 @@
#define NVIC_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define NVIC_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define NVIC_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
/* Vectors 7-10: Reserved */
#define NVIC_IRQ_SECUREFAULT (7) /* Vector 7: Secure fault */
/* Vectors 8-10: Reserved */
#define NVIC_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define NVIC_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
@ -59,10 +60,14 @@
/* NVIC base address ********************************************************/
#define ARMV8M_NVIC_BASE 0xe000e000
#define ARMV8M_NVIC_BASE_NS 0xe002e000
/* NVIC register offsets ****************************************************/
#define NVIC_ICTR_OFFSET 0x0004 /* Interrupt controller type register */
#define NVIC_ACTLR_OFFSET 0x0008 /* Auxiliary Control Register */
#define NVIC_CPPWR_OFFSET 0x000c /* Coprocessor Power Control Register */
#define NVIC_SYSTICK_CTRL_OFFSET 0x0010 /* SysTick control and status register */
#define NVIC_SYSTICK_RELOAD_OFFSET 0x0014 /* SysTick reload value register */
#define NVIC_SYSTICK_CURRENT_OFFSET 0x0018 /* SysTick current value register */
@ -192,6 +197,7 @@
/* System Control Block (SCB) */
#define NVIC_REVIDR_OFFSET 0x0cfc /* Revision ID Register */
#define NVIC_CPUID_BASE_OFFSET 0x0d00 /* CPUID base register */
#define NVIC_INTCTRL_OFFSET 0x0d04 /* Interrupt control state register */
#define NVIC_VECTAB_OFFSET 0x0d08 /* Vector table offset register */
@ -222,38 +228,61 @@
#define NVIC_ISAR2_OFFSET 0x0d68 /* ISA feature register 2 */
#define NVIC_ISAR3_OFFSET 0x0d6c /* ISA feature register 3 */
#define NVIC_ISAR4_OFFSET 0x0d70 /* ISA feature register 4 */
#define NVIC_CLIDR_OFFSET 0x0d78 /* Cache Level ID register (Cortex-M7) */
#define NVIC_CTR_OFFSET 0x0d7c /* Cache Type register (Cortex-M7) */
#define NVIC_CCSIDR_OFFSET 0x0d80 /* Cache Size ID Register (Cortex-M7) */
#define NVIC_CSSELR_OFFSET 0x0d84 /* Cache Size Selection Register (Cortex-M7) */
#define NVIC_ISAR5_OFFSET 0x0d74 /* ISA feature register 5 */
#define NVIC_CLIDR_OFFSET 0x0d78 /* Cache Level ID register */
#define NVIC_CTR_OFFSET 0x0d7c /* Cache Type register */
#define NVIC_CCSIDR_OFFSET 0x0d80 /* Cache Size ID Register */
#define NVIC_CSSELR_OFFSET 0x0d84 /* Cache Size Selection Register */
#define NVIC_CPACR_OFFSET 0x0d88 /* Coprocessor Access Control Register */
#define NVIC_NSACR_OFFSET 0x0d8c /* Non-secure Access Control Register */
/* Debug Control Block */
#define NVIC_DHCSR_OFFSET 0x0df0 /* Debug Halting Control and Status Register */
#define NVIC_DCRSR_OFFSET 0x0df4 /* Debug Core Register Selector Register */
#define NVIC_DCRDR_OFFSET 0x0df8 /* Debug Core Register Data Register */
#define NVIC_DEMCR_OFFSET 0x0dfc /* Debug Exception and Monitor Control Register */
#define NVIC_DSCEMCR_OFFSET 0x0e00 /* Debug Set Clear Exception and Monitor Control Register */
#define NVIC_DAUTHCTRL_OFFSET 0x0e04 /* Debug Authentication Control Register */
#define NVIC_DSCSR_OFFSET 0x0e08 /* Debug Security Control and Status Register */
/* Software Interrupt Generation */
#define NVIC_STIR_OFFSET 0x0f00 /* Software trigger interrupt register */
/* Reliability, Availability and Serviceability Extension */
#define NVIC_RFSR_OFFSET 0x0f04 /* RAS Fault Status Register */
/* Floating-Point Extension */
#define NVIC_FPCCR_OFFSET 0x0f34 /* Floating-point Context Control Register */
#define NVIC_FPCAR_OFFSET 0x0f38 /* Floating-point Context Address Register */
#define NVIC_FPDSCR_OFFSET 0x0f3c /* Floating-point Default Status Control Register */
#define NVIC_MVFR0_OFFSET 0x0f40 /* Media and VFP Feature Register 0 */
#define NVIC_MVFR1_OFFSET 0x0f44 /* Media and VFP Feature Register 1 */
#define NVIC_MVFR2_OFFSET 0x0f48 /* Media and VFP Feature Register 2 */
#define NVIC_ICIALLU_OFFSET 0x0f50 /* I-Cache Invalidate All to PoU (Cortex-M7) */
#define NVIC_ICIMVAU_OFFSET 0x0f58 /* I-Cache Invalidate by MVA to PoU (Cortex-M7) */
#define NVIC_DCIMVAC_OFFSET 0x0f5c /* D-Cache Invalidate by MVA to PoC (Cortex-M7) */
#define NVIC_DCISW_OFFSET 0x0f60 /* D-Cache Invalidate by Set-way (Cortex-M7) */
#define NVIC_DCCMVAU_OFFSET 0x0f64 /* D-Cache Clean by MVA to PoU (Cortex-M7) */
#define NVIC_DCCMVAC_OFFSET 0x0f68 /* D-Cache Clean by MVA to PoC (Cortex-M7) */
#define NVIC_DCCSW_OFFSET 0x0f6c /* D-Cache Clean by Set-way (Cortex-M7) */
#define NVIC_DCCIMVAC_OFFSET 0x0f70 /* D-Cache Clean and Invalidate by MVA to PoC (Cortex-M7) */
#define NVIC_DCCISW_OFFSET 0x0f74 /* D-Cache Clean and Invalidate by Set-way (Cortex-M7) */
#define NVIC_BPIALL_OFFSET 0x0f78 /* Branch predictor invalidate all (Cortex-M7) */
/* Cache Maintenance Operations */
#define NVIC_ICIALLU_OFFSET 0x0f50 /* I-Cache Invalidate All to PoU */
#define NVIC_ICIMVAU_OFFSET 0x0f58 /* I-Cache Invalidate by MVA to PoU */
#define NVIC_DCIMVAC_OFFSET 0x0f5c /* D-Cache Invalidate by MVA to PoC */
#define NVIC_DCISW_OFFSET 0x0f60 /* D-Cache Invalidate by Set-way */
#define NVIC_DCCMVAU_OFFSET 0x0f64 /* D-Cache Clean by MVA to PoU */
#define NVIC_DCCMVAC_OFFSET 0x0f68 /* D-Cache Clean by MVA to PoC */
#define NVIC_DCCSW_OFFSET 0x0f6c /* D-Cache Clean by Set-way */
#define NVIC_DCCIMVAC_OFFSET 0x0f70 /* D-Cache Clean and Invalidate by MVA to PoC */
#define NVIC_DCCISW_OFFSET 0x0f74 /* D-Cache Clean and Invalidate by Set-way */
#define NVIC_BPIALL_OFFSET 0x0f78 /* Branch predictor invalidate all */
#define NVIC_ITCMCR_OFFSET 0x0f90 /* Instruction Tightly-Coupled Memory Control Register */
#define NVIC_DTCMCR_OFFSET 0x0f94 /* Data Tightly-Coupled Memory Control Registers */
#define NVIC_AHBPCR_OFFSET 0x0f98 /* AHBP Control Register */
#define NVIC_CACR_OFFSET 0x0f9c /* L1 Cache Control Register */
#define NVIC_AHBSCR_OFFSET 0x0fa0 /* AHB Slave Control Register */
#define NVIC_ABFSR_OFFSET 0x0fa8 /* Auxiliary Bus Fault Status */
#define NVIC_PID4_OFFSET 0x0fd0 /* Peripheral identification register (PID4) */
#define NVIC_PID5_OFFSET 0x0fd4 /* Peripheral identification register (PID5) */
#define NVIC_PID6_OFFSET 0x0fd8 /* Peripheral identification register (PID6) */
@ -270,6 +299,9 @@
/* NVIC register addresses **************************************************/
#define NVIC_ICTR (ARMV8M_NVIC_BASE + NVIC_ICTR_OFFSET)
#define NVIC_ACTLR (ARMV8M_NVIC_BASE + NVIC_ACTLR_OFFSET)
#define NVIC_CPPWR (ARMV8M_NVIC_BASE + NVIC_CPPWR_OFFSET)
#define NVIC_SYSTICK_CTRL (ARMV8M_NVIC_BASE + NVIC_SYSTICK_CTRL_OFFSET)
#define NVIC_SYSTICK_RELOAD (ARMV8M_NVIC_BASE + NVIC_SYSTICK_RELOAD_OFFSET)
#define NVIC_SYSTICK_CURRENT (ARMV8M_NVIC_BASE + NVIC_SYSTICK_CURRENT_OFFSET)
@ -396,6 +428,7 @@
#define NVIC_IRQ228_231_PRIORITY (ARMV8M_NVIC_BASE + NVIC_IRQ228_231_PRIORITY_OFFSET)
#define NVIC_IRQ232_235_PRIORITY (ARMV8M_NVIC_BASE + NVIC_IRQ232_235_PRIORITY_OFFSET)
#define NVIC_REVIDR (ARMV8M_NVIC_BASE + NVIC_REVIDR_OFFSET)
#define NVIC_CPUID_BASE (ARMV8M_NVIC_BASE + NVIC_CPUID_BASE_OFFSET)
#define NVIC_INTCTRL (ARMV8M_NVIC_BASE + NVIC_INTCTRL_OFFSET)
#define NVIC_VECTAB (ARMV8M_NVIC_BASE + NVIC_VECTAB_OFFSET)
@ -426,22 +459,33 @@
#define NVIC_ISAR2 (ARMV8M_NVIC_BASE + NVIC_ISAR2_OFFSET)
#define NVIC_ISAR3 (ARMV8M_NVIC_BASE + NVIC_ISAR3_OFFSET)
#define NVIC_ISAR4 (ARMV8M_NVIC_BASE + NVIC_ISAR4_OFFSET)
#define NVIC_ISAR5 (ARMV8M_NVIC_BASE + NVIC_ISAR5_OFFSET)
#define NVIC_CLIDR (ARMV8M_NVIC_BASE + NVIC_CLIDR_OFFSET)
#define NVIC_CTR (ARMV8M_NVIC_BASE + NVIC_CTR_OFFSET)
#define NVIC_CCSIDR (ARMV8M_NVIC_BASE + NVIC_CCSIDR_OFFSET)
#define NVIC_CSSELR (ARMV8M_NVIC_BASE + NVIC_CSSELR_OFFSET)
#define NVIC_CPACR (ARMV8M_NVIC_BASE + NVIC_CPACR_OFFSET)
#define NVIC_NSACR (ARMV8M_NVIC_BASE + NVIC_NSACR_OFFSET)
#define NVIC_DHCSR (ARMV8M_NVIC_BASE + NVIC_DHCSR_OFFSET)
#define NVIC_DCRSR (ARMV8M_NVIC_BASE + NVIC_DCRSR_OFFSET)
#define NVIC_DCRDR (ARMV8M_NVIC_BASE + NVIC_DCRDR_OFFSET)
#define NVIC_DEMCR (ARMV8M_NVIC_BASE + NVIC_DEMCR_OFFSET)
#define NVIC_DSCEMCR (ARMV8M_NVIC_BASE + NVIC_DSCEMCR_OFFSET)
#define NVIC_DAUTHCTRL (ARMV8M_NVIC_BASE + NVIC_DAUTHCTRL_OFFSET)
#define NVIC_DSCSR (ARMV8M_NVIC_BASE + NVIC_DSCSR_OFFSET)
#define NVIC_STIR (ARMV8M_NVIC_BASE + NVIC_STIR_OFFSET)
#define NVIC_RFSR (ARMV8M_NVIC_BASE + NVIC_RFSR_OFFSET)
#define NVIC_FPCCR (ARMV8M_NVIC_BASE + NVIC_FPCCR_OFFSET)
#define NVIC_FPCAR (ARMV8M_NVIC_BASE + NVIC_FPCAR_OFFSET)
#define NVIC_FPDSCR (ARMV8M_NVIC_BASE + NVIC_FPDSCR_OFFSET)
#define NVIC_MVFR0 (ARMV8M_NVIC_BASE + NVIC_MVFR0_OFFSET)
#define NVIC_MVFR1 (ARMV8M_NVIC_BASE + NVIC_MVFR1_OFFSET)
#define NVIC_MVFR2 (ARMV8M_NVIC_BASE + NVIC_MVFR2_OFFSET)
#define NVIC_ICIALLU (ARMV8M_NVIC_BASE + NVIC_ICIALLU_OFFSET)
#define NVIC_ICIMVAU (ARMV8M_NVIC_BASE + NVIC_ICIMVAU_OFFSET)
#define NVIC_DCIMVAC (ARMV8M_NVIC_BASE + NVIC_DCIMVAC_OFFSET)
@ -452,12 +496,14 @@
#define NVIC_DCCIMVAC (ARMV8M_NVIC_BASE + NVIC_DCCIMVAC_OFFSET)
#define NVIC_DCCISW (ARMV8M_NVIC_BASE + NVIC_DCCISW_OFFSET)
#define NVIC_BPIALL (ARMV8M_NVIC_BASE + NVIC_BPIALL_OFFSET)
#define NVIC_ITCMCR (ARMV8M_NVIC_BASE + NVIC_ITCMCR_OFFSET)
#define NVIC_DTCMCR (ARMV8M_NVIC_BASE + NVIC_DTCMCR_OFFSET)
#define NVIC_AHBPCR (ARMV8M_NVIC_BASE + NVIC_AHBPCR_OFFSET)
#define NVIC_CACR (ARMV8M_NVIC_BASE + NVIC_CACR_OFFSET)
#define NVIC_AHBSCR (ARMV8M_NVIC_BASE + NVIC_AHBSCR_OFFSET)
#define NVIC_ABFSR (ARMV8M_NVIC_BASE + NVIC_ABFSR_OFFSET)
#define NVIC_PID4 (ARMV8M_NVIC_BASE + NVIC_PID4_OFFSET)
#define NVIC_PID5 (ARMV8M_NVIC_BASE + NVIC_PID5_OFFSET)
#define NVIC_PID6 (ARMV8M_NVIC_BASE + NVIC_PID6_OFFSET)
@ -478,6 +524,11 @@
#define NVIC_ICTR_INTLINESNUM_SHIFT 0 /* Bits 0-3: Number of interrupt inputs / 32 - 1 */
#define NVIC_ICTR_INTLINESNUM_MASK (15 << NVIC_ICTR_INTLINESNUM_SHIFT)
/* Coprocessor Power Control Register (CPPWR) */
#define NVIC_CPPWR_SU(n) (1 << 2 * (n)) /* Low power mode */
#define NVIC_CPPWR_SUS(n) (2 << 2 * (n)) /* Only accessible from the Secure state */
/* SysTick control and status register (SYSTICK_CTRL) */
#define NVIC_SYSTICK_CTRL_ENABLE (1 << 0) /* Bit 0: Enable */
@ -505,10 +556,12 @@
/* Interrupt control state register (INTCTRL) */
#define NVIC_INTCTRL_NMIPENDSET (1 << 31) /* Bit 31: Set pending NMI bit */
#define NVIC_INTCTRL_NMIPENDCLR (1 << 30) /* Bit 30: Clear pending NMI bit */
#define NVIC_INTCTRL_PENDSVSET (1 << 28) /* Bit 28: Set pending PendSV bit */
#define NVIC_INTCTRL_PENDSVCLR (1 << 27) /* Bit 27: Clear pending PendSV bit */
#define NVIC_INTCTRL_PENDSTSET (1 << 26) /* Bit 26: Set pending SysTick bit */
#define NVIC_INTCTRL_PENDSTCLR (1 << 25) /* Bit 25: Clear pending SysTick bit */
#define NVIC_INTCTRL_STTNS (1 << 24) /* Bit 24: SysTick Targets Non-secure */
#define NVIC_INTCTRL_ISPREEMPOT (1 << 23) /* Bit 23: Pending active next cycle */
#define NVIC_INTCTRL_ISRPENDING (1 << 22) /* Bit 22: Interrupt pending flag */
#define NVIC_INTCTRL_VECTPENDING_SHIFT 12 /* Bits 21-12: Pending ISR number field */
@ -522,7 +575,7 @@
/* Bit 0: Reserved */
#define NVIC_SYSCON_SLEEPONEXIT (1 << 1) /* Bit 1: Sleep-on-exit (returning from Handler to Thread mode) */
#define NVIC_SYSCON_SLEEPDEEP (1 << 2) /* Bit 2: Use deep sleep in low power mode */
/* Bit 3: Reserved */
#define NVIC_SYSCON_SLEEPDEEPS (1 << 3) /* Bit 3: Sleep deep secure */
#define NVIC_SYSCON_SEVONPEND (1 << 4) /* Bit 4: Send Event on Pending bit */
/* Bits 5-31: Reserved */
@ -534,10 +587,12 @@
#define NVIC_CFGCON_DIV0TRP (1 << 4) /* Bit 4: Enables fault on divide-by-zero */
#define NVIC_CFGCON_BFHFNMIGN (1 << 8) /* Bit 8: Disables data bus faults */
#define NVIC_CFGCON_STKALIGN (1 << 9) /* Bit 9: Indicates stack alignment on exception */
/* Cortex-M7: */
#define NVIC_CFGCON_STKOFHFNMIGN (1 << 10) /* Bit 10: Stack overflow in HardFault and NMI ignore */
#define NVIC_CFGCON_DC (1 << 16) /* Bit 16: Data cache enable */
#define NVIC_CFGCON_IC (1 << 17) /* Bit 17: Instruction cache enable */
#define NVIC_CFGCON_BP (1 << 18) /* Bit 18: Branch prediction enable */
#define NVIC_CFGCON_LOB (1 << 19) /* Bit 19: Loop and branch info cache enable */
#define NVIC_CFGCON_TRD (1 << 20) /* Bit 20: Thread reentrancy disabled */
/* System handler 4-7 priority register */
@ -577,9 +632,15 @@
#define NVIC_AIRCR_VECTRESET (1 << 0) /* Bit 0: VECTRESET */
#define NVIC_AIRCR_VECTCLRACTIVE (1 << 1) /* Bit 1: Reserved for debug use */
#define NVIC_AIRCR_SYSRESETREQ (1 << 2) /* Bit 2: System reset */
/* Bits 2-7: Reserved */
#define NVIC_AIRCR_PRIGROUP_SHIFT (8) /* Bits 8-14: PRIGROUP */
#define NVIC_AIRCR_SYSRESETREQS (1 << 3) /* Bit 3: System reset request secure only */
#define NVIC_AIRCR_DIT (1 << 4) /* Bit 4: Data Independent Timing */
#define NVIC_AIRCR_IESB (1 << 5) /* Bit 5: Implicit ESB Enable */
/* Bits 6-7: Reserved */
#define NVIC_AIRCR_PRIGROUP_SHIFT (8) /* Bits 8-10: PRIGROUP */
#define NVIC_AIRCR_PRIGROUP_MASK (7 << NVIC_AIRCR_PRIGROUP_SHIFT)
/* Bits 11-12: Reserved */
#define NVIC_AIRCR_BFHFNMINS (1 << 13) /* Bit 13: BusFault, HardFault, and NMI Non-secure enable */
#define NVIC_AIRCR_PRIS (1 << 14) /* Bit 14: Prioritize Secure exceptions */
#define NVIC_AIRCR_ENDIANNESS (1 << 15) /* Bit 15: 1=Big endian */
#define NVIC_AIRCR_VECTKEY_SHIFT (16) /* Bits 16-31: VECTKEY */
#define NVIC_AIRCR_VECTKEY_MASK (0xffff << NVIC_AIRCR_VECTKEY_SHIFT)
@ -592,7 +653,10 @@
#define NVIC_SYSHCON_MEMFAULTACT (1 << 0) /* Bit 0: MemManage is active */
#define NVIC_SYSHCON_BUSFAULTACT (1 << 1) /* Bit 1: BusFault is active */
#define NVIC_SYSHCON_HARDFAULTACT (1 << 2) /* Bit 2: HardFault is active */
#define NVIC_SYSHCON_USGFAULTACT (1 << 3) /* Bit 3: UsageFault is active */
#define NVIC_SYSHCON_SECUREFAULTACT (1 << 4) /* Bit 4: SecureFault is active */
#define NVIC_SYSHCON_NMIACT (1 << 5) /* Bit 5: NMI is active */
#define NVIC_SYSHCON_SVCALLACT (1 << 7) /* Bit 7: SVCall is active */
#define NVIC_SYSHCON_MONITORACT (1 << 8) /* Bit 8: Monitor is active */
#define NVIC_SYSHCON_PENDSVACT (1 << 10) /* Bit 10: PendSV is active */
@ -604,13 +668,19 @@
#define NVIC_SYSHCON_MEMFAULTENA (1 << 16) /* Bit 16: MemFault enabled */
#define NVIC_SYSHCON_BUSFAULTENA (1 << 17) /* Bit 17: BusFault enabled */
#define NVIC_SYSHCON_USGFAULTENA (1 << 18) /* Bit 18: UsageFault enabled */
#define NVIC_SYSHCON_SECUREFAULTENA (1 << 19) /* Bit 10: SecureFault enabled */
#define NVIC_SYSHCON_SECUREFAULTPENDED (1 << 20) /* Bit 10: SecureFault is pended */
#define NVIC_SYSHCON_HARDFAULTPENDED (1 << 20) /* Bit 10: HardFault is pended */
/* Cache Level ID register (Cortex-M7) */
/* Cache Level ID register */
#define NVIC_CLIDR_L1CT_SHIFT (0) /* Bits 0-2: Level 1 cache type */
#define NVIC_CLIDR_L1CT_MASK (7 << NVIC_CLIDR_L1CT_SHIFT)
# define NVIC_CLIDR_L1CT_ICACHE (1 << NVIC_CLIDR_LOC_SHIFT)
# define NVIC_CLIDR_L1CT_DCACHE (2 << NVIC_CLIDR_LOC_SHIFT)
# define NVIC_CLIDR_L1CT_ICACHE (1 << NVIC_CLIDR_L1CT_SHIFT)
# define NVIC_CLIDR_L1CT_DCACHE (2 << NVIC_CLIDR_L1CT_SHIFT)
# define NVIC_CLIDR_L1CT_UNIFIED (4 << NVIC_CLIDR_L1CT_SHIFT)
#define NVIC_CLIDR_LOUIS_SHIFT (21) /* Bits 21-23: Level of Unification Inner Shareable */
#define NVIC_CLIDR_LOUIS_MASK (7 << NVIC_CLIDR_LOC_SHIFT)
#define NVIC_CLIDR_LOC_SHIFT (24) /* Bits 24-26: Level of Coherency */
#define NVIC_CLIDR_LOC_MASK (7 << NVIC_CLIDR_LOC_SHIFT)
# define NVIC_CLIDR_LOC_IMPLEMENTED (1 << NVIC_CLIDR_LOC_SHIFT)
@ -619,8 +689,14 @@
#define NVIC_CLIDR_LOUU_MASK (7 << NVIC_CLIDR_LOUU_SHIFT)
# define NVIC_CLIDR_LOUU_IMPLEMENTED (1 << NVIC_CLIDR_LOUU_SHIFT)
# define NVIC_CLIDR_LOUU_UNIMPLEMENTED (0 << NVIC_CLIDR_LOUU_SHIFT)
#define NVIC_CLIDR_ICB_SHIFT (30) /* Bits 31-30: Inner cache boundary */
#define NVIC_CLIDR_ICB_MASK (3 << NVIC_CLIDR_ICB_SHIFT)
# define NVIC_CLIDR_ICB_UNKOWN (0 << NVIC_CLIDR_ICB_SHIFT)
# define NVIC_CLIDR_ICB_L1 (1 << NVIC_CLIDR_ICB_SHIFT)
# define NVIC_CLIDR_ICB_L2 (2 << NVIC_CLIDR_ICB_SHIFT)
# define NVIC_CLIDR_ICB_L3 (3 << NVIC_CLIDR_ICB_SHIFT)
/* Cache Type register (Cortex-M7) */
/* Cache Type register */
#define NVIC_CTR_IMINLINE_SHIFT (0) /* Bits 0-3: ImInLine */
#define NVIC_CTR_IMINLINE_MASK (15 << NVIC_CTR_IMINLINE_SHIFT)
@ -628,12 +704,12 @@
#define NVIC_CTR_DMINLINE_MASK (15 << NVIC_CTR_DMINLINE_SHIFT)
#define NVIC_CTR_ERG_SHIFT (20) /* Bits 20-23: ERG */
#define NVIC_CTR_ERG_MASK (15 << NVIC_CTR_ERG_SHIFT)
#define NVIC_CTR_CWG_SHIFT (24) /* Bits 24-27: ERG */
#define NVIC_CTR_CWG_SHIFT (24) /* Bits 24-27: CWG */
#define NVIC_CTR_CWG_MASK (15 << NVIC_CTR_CWG_SHIFT)
#define NVIC_CTR_FORMAT_SHIFT (29) /* Bits 29-31: Format */
#define NVIC_CTR_FORMAT_MASK (7 << NVIC_CTR_FORMAT_SHIFT)
/* Cache Size ID Register (Cortex-M7) */
/* Cache Size ID Register */
#define NVIC_CCSIDR_LINESIZE_SHIFT (0) /* Bits 0-2: Number of words in each cache line */
#define NVIC_CCSIDR_LINESIZE_MASK (7 << NVIC_CCSIDR_LINESIZE_SHIFT)
@ -646,7 +722,7 @@
#define NVIC_CCSIDR_WB_SHIFT (1 << 30) /* Bits 30: Write-Back support */
#define NVIC_CCSIDR_WT_SHIFT (1 << 31) /* Bits 31: Write-Through support */
/* Cache Size Selection Register (Cortex-M7) */
/* Cache Size Selection Register */
#define NVIC_CSSELR_IND (1 << 0) /* Bit 0: Selects either instruction or data cache */
# define NVIC_CSSELR_IND_ICACHE (0 << 0) /* 0=Instruction Cache */
@ -664,6 +740,13 @@
# define NVIC_CPACR_CP_PRIV(n) (1 << NVIC_CPACR_CP_SHIFT(n))
# define NVIC_CPACR_CP_FULL(n) (3 << NVIC_CPACR_CP_SHIFT(n))
/* Non-secure Access Control Register (NSACR) */
#define NVIC_NSACR_CP_SHIFT(n) (n)
#define NVIC_NSACR_CP_MASK(n) (1 << NVIC_CPACR_CP_SHIFT(n))
# define NVIC_NSACR_CP_SECURE(n) (0 << NVIC_CPACR_CP_SHIFT(n))
# define NVIC_NSACR_CP_FULL(n) (1 << NVIC_CPACR_CP_SHIFT(n))
/* Debug Exception and Monitor Control Register (DEMCR) */
#define NVIC_DEMCR_VCCORERESET (1 << 0) /* Bit 0: Reset Vector Catch */
@ -674,12 +757,23 @@
#define NVIC_DEMCR_VCBUSERR (1 << 8) /* Bit 8: Debug Trap on normal Bus error */
#define NVIC_DEMCR_VCINTERR (1 << 9) /* Bit 9: Debug Trap on interrupt/exception service errors */
#define NVIC_DEMCR_VCHARDERR (1 << 10) /* Bit 10: Debug trap on Hard Fault */
#define NVIC_DEMCR_VCSFERR (1 << 11) /* Bit 11: Debug trap on Secure Fault */
#define NVIC_DEMCR_MONEN (1 << 16) /* Bit 16: Enable the debug monitor */
#define NVIC_DEMCR_MONPEND (1 << 17) /* Bit 17: Pend the monitor to activate when priority permits */
#define NVIC_DEMCR_MONSTEP (1 << 18) /* Bit 18: Steps the core */
#define NVIC_DEMCR_MONREQ (1 << 19) /* Bit 19: Monitor wake-up mode */
#define NVIC_DEMCR_SDME (1 << 20) /* Bit 20: Enable the security debug monitor */
#define NVIC_DEMCR_UMON_EN (1 << 21) /* Bit 21: Unprivileged monitor enable */
#define NVIC_DEMCR_MONPRKEY (1 << 23) /* Bit 23: Monitor pend req key */
#define NVIC_DEMCR_TRCENA (1 << 24) /* Bit 24: Enable trace and debug blocks */
/* Debug Set Clear Exception and Monitor Control Register (DSCEMCR) */
#define NVIC_DSCEMCR_SET_MON_PEND (1 << 1) /* Bit 1: Set monitor pend */
#define NVIC_DSCEMCR_SET_MON_REQ (1 << 3) /* Bit 3: Set monitor request */
#define NVIC_DSCEMCR_CLR_MON_PEND (1 << 17) /* Bit 17: Clear monitor pend */
#define NVIC_DSCEMCR_CLR_MON_REQ (1 << 19) /* Bit 19: Clear monitor request */
/* Floating-Point Context Control Register (FPCCR) */
#define NVIC_FPCCR_LSPACT (1 << 0) /* Bit 0: Lazy state preservation active */
@ -702,9 +796,9 @@
/* Instruction Tightly-Coupled Memory Control Register (ITCMCR) */
/* Data Tightly-Coupled Memory Control Registers (DTCMCR */
/* Data Tightly-Coupled Memory Control Registers (DTCMCR) */
#define NVIC_TCMCR_EN (1 << 0) /* Bit 9: TCM enable */
#define NVIC_TCMCR_EN (1 << 0) /* Bit 0: TCM enable */
#define NVIC_TCMCR_RMW (1 << 1) /* Bit 1: Read-Modify-Write (RMW) enable */
#define NVIC_TCMCR_RETEN (1 << 2) /* Bit 2: Retry phase enable */
#define NVIC_TCMCR_SZ_SHIFT (3) /* Bits 3-6: Size of the TCM */
@ -724,7 +818,7 @@
# define NVIC_TCMCR_SZ_8MB (14 << NVIC_TCMCR_SZ_SHIFT)
# define NVIC_TCMCR_SZ_16MB (15 << NVIC_TCMCR_SZ_SHIFT)
/* AHBP Control Register (AHBPCR, Cortex-M7) */
/* AHBP Control Register (AHBPCR) */
#define NVIC_AHBPCR_EN (1 << 0) /* Bit 0: AHBP enable */
#define NVIC_AHBPCR_SZ_SHIFT (1) /* Bits 1-3: AHBP size */
@ -735,7 +829,7 @@
# define NVIC_AHBPCR_SZ_256MB (3 << NVIC_AHBPCR_SZ_SHIFT)
# define NVIC_AHBPCR_SZ_512MB (4 << NVIC_AHBPCR_SZ_SHIFT)
/* L1 Cache Control Register (CACR, Cortex-M7) */
/* L1 Cache Control Register (CACR) */
#define NVIC_CACR_SIWT (1 << 0) /* Bit 0: Shared cacheable-is-WT for data cache */
#define NVIC_CACR_ECCDIS (1 << 1) /* Bit 1: Enables ECC in the instruction and data cache */

52
arch/arm/src/armv8-m/psr.h
View File

@ -31,6 +31,9 @@
/* Application Program Status Register (APSR) */
#define ARMV8M_APSR_GE_SHIFT 16 /* Bits 16-19: Greater than or equal flags */
#define ARMV8M_APSR_GE_MASK (0xf << ARMV8M_APSR_GE_SHIFT)
#define ARMV8M_APSR_Q (1 << 27) /* Bit 27: Sticky saturation flag */
#define ARMV8M_APSR_V (1 << 28) /* Bit 28: Overflow flag */
#define ARMV8M_APSR_C (1 << 29) /* Bit 29: Carry/borrow flag */
@ -45,17 +48,28 @@
/* Execution PSR Register (EPSR) */
#define ARMV8M_EPSR_ICIIT1_SHIFT 10 /* Bits 15-10: Interrupt-Continuable-Instruction/If-Then bits */
#define ARMV8M_EPSR_ICIIT1_MASK (3 << ARMV8M_EPSR_ICIIT1_SHIFT)
#define ARMV8M_EPSR_ICIIT1_MASK (0x3f << ARMV8M_EPSR_ICIIT1_SHIFT)
#define ARMV8M_EPSR_B (1 << 21) /* Bit 21: Branch target identification active */
#define ARMV8M_EPSR_T (1 << 24) /* Bit 24: T-bit */
#define ARMV8M_EPSR_ICIIT2_SHIFT 25 /* Bits 26-25: Interrupt-Continuable-Instruction/If-Then bits */
#define ARMV8M_EPSR_ICIIT2_MASK (3 << ARMV8M_EPSR_ICIIT2_SHIFT)
/* Return PSR Register (RETPSR) */
#define ARMV8M_RETPSR_SPREALIGN (1 << 9) /* Bit 9: Stack-pointer re-align */
#define ARMV8M_RETPSR_SFPA (1 << 20) /* Bit 20: Secure Floating-point active */
/* Save xPSR bits */
#define ARMV8M_XPSR_ISR_SHIFT ARMV8M_IPSR_ISR_SHIFT
#define ARMV8M_XPSR_ISR_MASK ARMV8M_IPSR_ISR_MASK
#define ARMV8M_XPSR_ICIIT1_SHIFT ARMV8M_EPSR_ICIIT1_SHIFT/
#define ARMV8M_XPSR_SPREALIGN ARMV8M_RETPSR_SPREALIGN
#define ARMV8M_XPSR_ICIIT1_SHIFT ARMV8M_EPSR_ICIIT1_SHIFT
#define ARMV8M_XPSR_ICIIT1_MASK ARMV8M_EPSR_ICIIT1_MASK
#define ARMV8M_XPSR_GE_SHIFT ARMV8M_APSR_GE_SHIFT
#define ARMV8M_XPSR_GE_MASK ARMV8M_APSR_GE_MASK
#define ARMV8M_XPSR_SFPA ARMV8M_RETPSR_SFPA
#define ARMV8M_XPSR_B ARMV8M_EPSR_B
#define ARMV8M_XPSR_T ARMV8M_EPSR_T
#define ARMV8M_XPSR_ICIIT2_SHIFT ARMV8M_EPSR_ICIIT2_SHIFT
#define ARMV8M_XPSR_ICIIT2_MASK ARMV8M_EPSR_ICIIT2_MASK
@ -65,6 +79,40 @@
#define ARMV8M_XPSR_Z ARMV8M_APSR_Z
#define ARMV8M_XPSR_N ARMV8M_APSR_N
/* Floating-point Status and Control Register (FPSCR) */
#define ARMV8M_FPSCR_IOC (1 << 0) /* Bit 0: Invalid Operation */
#define ARMV8M_FPSCR_DZC (1 << 1) /* Bit 1: Divide by Zero */
#define ARMV8M_FPSCR_OFC (1 << 2) /* Bit 2: Overflow */
#define ARMV8M_FPSCR_UFC (1 << 3) /* Bit 3: Underflow */
#define ARMV8M_FPSCR_IXC (1 << 4) /* Bit 4: Inexact */
#define ARMV8M_FPSCR_IDC (1 << 7) /* Bit 7: Input Denormal */
#define ARMV8M_FPSCR_LTPSIZE_SHIFT 16 /* Bits 16-18: Vector element size */
#define ARMV8M_FPSCR_LTPSIZE_8BIT (0x0 << ARMV8M_FPSCR_RM_SHIFT)
#define ARMV8M_FPSCR_LTPSIZE_16BIT (0x1 << ARMV8M_FPSCR_RM_SHIFT)
#define ARMV8M_FPSCR_LTPSIZE_32BIT (0x2 << ARMV8M_FPSCR_RM_SHIFT)
#define ARMV8M_FPSCR_LTPSIZE_DONE (0x3 << ARMV8M_FPSCR_RM_SHIFT)
#define ARMV8M_FPSCR_LTPSIZE_MASK (0x7 << ARMV8M_FPSCR_RM_SHIFT)
#define ARMV8M_FPSCR_FZ16 (1 << 19) /* Bit 19: Flush-to-zero mode(half-precision) */
#define ARMV8M_FPSCR_RM_SHIFT 22 /* Bits 22-23: Round mode */
#define ARMV8M_FPSCR_RM_NEAR (0x0 << ARMV8M_FPSCR_RM_SHIFT)
#define ARMV8M_FPSCR_RM_PLUS (0x1 << ARMV8M_FPSCR_RM_SHIFT)
#define ARMV8M_FPSCR_RM_MINUS (0x2 << ARMV8M_FPSCR_RM_SHIFT)
#define ARMV8M_FPSCR_RM_ZERO (0x3 << ARMV8M_FPSCR_RM_SHIFT)
#define ARMV8M_FPSCR_RM_MASK (0x3 << ARMV8M_FPSCR_RM_SHIFT)
#define ARMV8M_FPSCR_FZ (1 << 24) /* Bit 24: Flush-to-zero mode */
#define ARMV8M_FPSCR_DN (1 << 25) /* Bit 25: Default NaN mode */
#define ARMV8M_FPSCR_AHP (1 << 26) /* Bit 26: Alternative half-precision */
#define ARMV8M_FPSCR_Q (1 << 27) /* Bit 27: Sticky saturation flag */
#define ARMV8M_FPSCR_V (1 << 28) /* Bit 28: Overflow flag */
#define ARMV8M_FPSCR_C (1 << 29) /* Bit 29: Carry/borrow flag */
#define ARMV8M_FPSCR_Z (1 << 30) /* Bit 30: Zero flag */
#define ARMV8M_FPSCR_N (1 << 31) /* Bit 31: Negative, less than flag */
/****************************************************************************
* Inline Functions
****************************************************************************/