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Additional corrections to state restore logic

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@466 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2007-12-30 21:54:55 +00:00
parent 821975f7bd
commit f038ce79e9
3 changed files with 15 additions and 16 deletions
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4
TODO
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@ -231,9 +231,9 @@ o Build system
Priority: Low Priority: Low
Description: Dependencies do not work correctly under configs/<board>/src Description: Dependencies do not work correctly under configs/<board>/src
(same as arch/<arch>/src/board) with SDCC. (same as arch/<arch>/src/board). Seems to be worse using SDCC.
Status: Open Status: Open
Priority: Medium Priority: Medium (maybe higher for z80 target)
o Applications & Tests (examples/) o Applications & Tests (examples/)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

14
arch/z80/include/z80/irq.h
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@ -70,13 +70,13 @@
*/ */
#define XCPT_I (0) /* Offset 0: Saved I w/interrupt state in carry */ #define XCPT_I (0) /* Offset 0: Saved I w/interrupt state in carry */
#define XCPT_AF (1) /* Offset 1: Saved AF register */ #define XCPT_BC (1) /* Offset 1: Saved BC register */
#define XCPT_BC (2) /* Offset 2: Saved BC register */ #define XCPT_DE (2) /* Offset 2: Saved DE register */
#define XCPT_DE (3) /* Offset 3: Saved DE register */ #define XCPT_IX (3) /* Offset 3: Saved IX register */
#define XCPT_HL (4) /* Offset 4: Saved HL register */ #define XCPT_IY (4) /* Offset 4: Saved IY register */
#define XCPT_IX (5) /* Offset 5: Saved IX register */ #define XCPT_SP (5) /* Offset 5: Offset to SP at time of interrupt */
#define XCPT_IY (6) /* Offset 6: Saved IY register */ #define XCPT_HL (6) /* Offset 6: Saved HL register */
#define XCPT_SP (7) /* Offset 7: Offset to SP at time of interrupt */ #define XCPT_AF (7) /* Offset 7: Saved AF register */
#define XCPT_PC (8) /* Offset 8: Offset to PC at time of interrupt */ #define XCPT_PC (8) /* Offset 8: Offset to PC at time of interrupt */
#define XCPTCONTEXT_REGS (9) #define XCPTCONTEXT_REGS (9)

13
arch/z80/src/common/up_restoreusercontext.asm
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@ -49,7 +49,6 @@
; up_restoreusercontext ; up_restoreusercontext
;************************************************************************** ;**************************************************************************
; .area _CODE (ABS,OVR)
_up_restoreusercontext: _up_restoreusercontext:
; On entry, stack contains return address (not used), then address ; On entry, stack contains return address (not used), then address
; of the register save structure ; of the register save structure
@ -79,9 +78,7 @@ _up_restoreusercontext:
pop ix ; Offset 3: IX pop ix ; Offset 3: IX
pop iy ; Offset 4: IY pop iy ; Offset 4: IY
exx ; Use alternate BC/DE/HL exx ; Use alternate BC/DE/HL
ld hl, #-2 ; Offset of SP to account for ret addr on stack pop hl ; Offset 5: HL' = Stack pointer after return
pop de ; Offset 5: HL' = Stack pointer after return
add hl, de ; HL = Stack pointer value before return
exx ; Restore original BC/DE/HL exx ; Restore original BC/DE/HL
pop hl ; Offset 6: HL pop hl ; Offset 6: HL
pop af ; Offset 7: AF pop af ; Offset 7: AF
@ -89,7 +86,9 @@ _up_restoreusercontext:
; Restore the stack pointer ; Restore the stack pointer
exx ; Use alternate BC/DE/HL exx ; Use alternate BC/DE/HL
pop de ; DE' = return address
ld sp, hl ; Set SP = saved stack pointer value before return ld sp, hl ; Set SP = saved stack pointer value before return
push de ; Save return address for ret instruction
exx ; Restore original BC/DE/HL exx ; Restore original BC/DE/HL
; Restore interrupt state ; Restore interrupt state
@ -97,8 +96,8 @@ _up_restoreusercontext:
ex af, af' ; Recover interrupt state ex af, af' ; Recover interrupt state
jr nc, noinrestore ; No carry, IFF2=0, means disabled jr nc, noinrestore ; No carry, IFF2=0, means disabled
ex af, af' ; Restore AF (before enabling interrupts) ex af, af' ; Restore AF (before enabling interrupts)
ei ; yes ei ; yes.. Enable interrupts
ret ret ; and return
noinrestore: noinrestore:
ex af, af' ; Restore AF ex af, af' ; Restore AF
ret ret ; Return with interrupts disabled