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Bugfixes submitted by David Hewson

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2543 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-03-16 00:53:32 +00:00
parent f736b27773
commit f03cb0ff3a
10 changed files with 33 additions and 31 deletions
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4
arch/arm/include/lpc313x/irq.h
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/include/lpc313x/irq.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -59,7 +59,7 @@
#define LPC313X_IRQ_TMR1 5 /* IRQ6: Timer 1 Interrupt */
#define LPC313X_IRQ_TMR2 6 /* IRQ7: Timer 2 Interrupt */
#define LPC313X_IRQ_TMR3 7 /* IRQ8: Timer 3 Interrupt */
#define LPC313X_IRQ_TMR3 8 /* IRQ9: ADC 10-bit */
#define LPC313X_IRQ_ADC 8 /* IRQ9: ADC 10-bit */
#define LPC313X_IRQ_UART 9 /* IRQ10: UART */
#define LPC313X_IRQ_I2C0 10 /* IRQ11: I2C0 */
#define LPC313X_IRQ_I2C1 11 /* IRQ12: I2C1 */

12
arch/arm/src/lpc313x/lpc313x_cgu.h
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@ -1,7 +1,7 @@
/************************************************************************************************
* arch/arm/src/lpc313x/lpc313x_cgu.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* References:
@ -1223,17 +1223,19 @@
/* Fractional divider register 0 to 23 FDC0 to FDC23 (except FDC17) addresses 0x13004518 to 0x13004574 */
#define CGU_FDC_MSUB_SHIFT (11) /* Bits 11-18: Modulo subtraction value */
#define CGU_FDC_MSUB_MASK (255 << CGU_FDC_MSUB_SHIFT)
#define CGU_FDC_MSUB_MASK (0x000000ff << CGU_FDC_MSUB_SHIFT)
#define CGU_FDC_MSUB_EXTEND (0xffffff00)
#define CGU_FDC_MADD_SHIFT (3) /* Bits 3-10: Modulo addition value */
#define CGU_FDC_MADD_MASK (255 << CGU_FDC_MADD_SHIFT)
#define CGU_FDC_MADD_MASK (0x000000ff << CGU_FDC_MADD_SHIFT)
#define CGU_FDC_STRETCH (1 << 2) /* Bit 2: Enables the stretching option */
#define CGU_FDC_RESET (1 << 1) /* Bit 1: Reset fractional divider */
#define CGU_FDC_RUN (1 << 0) /* Bit 0: Enable fractional divider */
#define CGU_FDC17_MSUB_SHIFT (16) /* Bits 16-28: Modulo subtraction value */
#define CGU_FDC17_MSUB_MASK (0x1fff << CGU_FDC17_MSUB_SHIFT)
#define CGU_FDC17_MSUB_MASK (0x00001fff << CGU_FDC17_MSUB_SHIFT)
#define CGU_FDC17_MSUB_EXTEND (0xffffe000)
#define CGU_FDC17_MADD_SHIFT (3) /* Bits 3-15: Modulo addition value */
#define CGU_FDC17_MADD_MASK (0x1fff << CGU_FDC17_MADD_SHIFT)
#define CGU_FDC17_MADD_MASK (0x00001fff << CGU_FDC17_MADD_SHIFT)
#define CGU_FDC17_STRETCH (1 << 2) /* Bit 2: Enables the stretching option */
#define CGU_FDC17_RESET (1 << 1) /* Bit 1: Reset fractional divider */
#define CGU_FDC17_RUN (1 << 0) /* Bit 0: Enable fractional divider */

4
arch/arm/src/lpc313x/lpc313x_cgudrvr.h
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@ -1,7 +1,7 @@
/************************************************************************
* arch/arm/src/lpc313x/lpc313x_cgudrvr.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* References:
@ -561,7 +561,7 @@ static inline uint32_t lpc313x_getbasefreq(enum lpc313x_domainid_e dmnid)
/* Fetch the SSR register associated with this clock domain */
regval = getreg32(LPC313X_CGU_SSR_OFFSET((int)dmnid));
regval = getreg32(LPC313X_CGU_SSR((int)dmnid));
/* Extract the last frequency input selection */

8
arch/arm/src/lpc313x/lpc313x_clkfreq.c
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@ -1,7 +1,7 @@
/************************************************************************
* arch/arm/src/lpc313x/lpc313x_clkfreq.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* References:
@ -100,7 +100,7 @@ uint32_t lpc313x_clkfreq(enum lpc313x_clockid_e clkid,
* it is enabled (not necessary since lpc313x_fdcndx() also does this check
*/
regval = getreg32(LPC313X_CGU_FDC_OFFSET(fdcndx));
regval = getreg32(LPC313X_CGU_FDC(fdcndx));
if ((regval & CGU_ESR_ESREN) != 0)
{
int32_t msub;
@ -117,14 +117,14 @@ uint32_t lpc313x_clkfreq(enum lpc313x_clockid_e clkid,
{
/* Range is 0-0x1fff for both */
msub = (regval & CGU_FDC17_MSUB_MASK) >> CGU_FDC17_MSUB_SHIFT;
msub = ((regval & CGU_FDC17_MSUB_MASK) >> CGU_FDC17_MSUB_SHIFT) | CGU_FDC17_MSUB_EXTEND;
madd = (regval & CGU_FDC17_MADD_MASK) >> CGU_FDC17_MADD_SHIFT;
}
else
{
/* Range is 0-255 for both */
msub = (regval & CGU_FDC_MSUB_MASK) >> CGU_FDC_MSUB_SHIFT;
msub = ((regval & CGU_FDC_MSUB_MASK) >> CGU_FDC_MSUB_SHIFT) | CGU_FDC_MSUB_EXTEND;
madd = (regval & CGU_FDC_MADD_MASK) >> CGU_FDC_MADD_SHIFT;
}

4
arch/arm/src/lpc313x/lpc313x_fdcndx.c
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@ -1,7 +1,7 @@
/************************************************************************
* arch/arm/src/lpc313x/lpc313x_fdcndx.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* References:
@ -109,7 +109,7 @@ int lpc313x_fdcndx(enum lpc313x_clockid_e clkid, enum lpc313x_domainid_e dmnid)
{
/* Read the clock's ESR to get the fractional divider */
uint32_t regval = getreg32(LPC313X_CGU_ESR_OFFSET(esrndx));
uint32_t regval = getreg32(LPC313X_CGU_ESR(esrndx));
/* Check if any fractional divider is enabled for this clock. */

8
arch/arm/src/lpc313x/lpc313x_intc.h
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@ -1,7 +1,7 @@
/************************************************************************************************
* arch/arm/src/lpc313x/lpc313x_intc.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -177,11 +177,11 @@
#define INTC_REQUEST_ENABLE (1 << 16) /* Bit 16: Enable interrupt request */
#define INTC_REQUEST_TARGET_SHIFT (8) /* Bits 8-13: Interrupt target */
#define INTC_REQUEST_TARGET_MASK (63 << INTC_REQUEST_TARGET_SHIFT)
# define INTC_REQUEST_TARGET_IRQ (0 << INTC_REQUEST_TARGET_SHIFT) /* Proc interrupt request 0: IRQ */
# define INTC_REQUEST_TARGET_FIQ (1 << INTC_REQUEST_TARGET_SHIFT) /* Proc interrupt request 1: FIQ */
# define INTC_REQUEST_TARGET_IRQ (INTC_REQUEST_WETARGET | (0 << INTC_REQUEST_TARGET_SHIFT)) /* Proc interrupt request 0: IRQ */
# define INTC_REQUEST_TARGET_FIQ (INTC_REQUEST_WETARGET | (1 << INTC_REQUEST_TARGET_SHIFT)) /* Proc interrupt request 1: FIQ */
#define INTC_REQUEST_PRIOLEVEL_SHIFT (0) /* Bits 0-7: Priority level */
#define INTC_REQUEST_PRIOLEVEL_MASK (255 << INTC_REQUEST_PRIOLEVEL_SHIFT)
# define INTC_REQUEST_PRIOLEVEL(n) (((n) << INTC_REQUEST_TARGET_SHIFT) & INTC_REQUEST_PRIOLEVEL_MASK)
# define INTC_REQUEST_PRIOLEVEL(n) (((n) << INTC_REQUEST_PRIOLEVEL_SHIFT) & INTC_REQUEST_PRIOLEVEL_MASK)
/************************************************************************************************
* Public Types

12
arch/arm/src/lpc313x/lpc313x_irq.c
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@ -2,7 +2,7 @@
* arch/arm/src/lpc313x/lpc313x_irq.c
* arch/arm/src/chip/lpc313x_irq.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -105,13 +105,13 @@ void up_irqinitialize(void)
/* Disable all interrupts. Start from index 1 since 0 is unused.*/
for (irq = 1; irq <= NR_IRQS; irq++)
for (irq = 0; irq < NR_IRQS; irq++)
{
/* Initialize as high-active, disable the interrupt, set target to IRQ,
* Set priority level to 1 (= lowest) for all the interrupt lines
*/
uint32_t address = LPC313X_INTC_REQUEST(irq);
uint32_t address = LPC313X_INTC_REQUEST(irq+1);
putreg32(INTC_REQUEST_WEACTLOW|INTC_REQUEST_WEENABLE|INTC_REQUEST_TARGET_IRQ|
INTC_REQUEST_PRIOLEVEL(1)|INTC_REQUEST_WEPRIO, address);
@ -142,7 +142,7 @@ void up_disable_irq(int irq)
* interrupt source
*/
uint32_t address = LPC313X_INTC_REQUEST(irq);
uint32_t address = LPC313X_INTC_REQUEST(irq+1);
/* Clear the ENABLE bit with WE_ENABLE=1. Configuration settings will be
* preserved because WE_TARGET is zero.
@ -165,7 +165,7 @@ void up_enable_irq(int irq)
* interrupt source
*/
uint32_t address = LPC313X_INTC_REQUEST(irq);
uint32_t address = LPC313X_INTC_REQUEST(irq+1);
/* Set the ENABLE bit with WE_ENABLE=1. Configuration settings will be
* preserved because WE_TARGET is zero.
@ -188,7 +188,7 @@ void up_maskack_irq(int irq)
* interrupt source
*/
uint32_t address = LPC313X_INTC_REQUEST(irq);
uint32_t address = LPC313X_INTC_REQUEST(irq+1);
/* Clear the pending interrupt (INTC_REQUEST_CLRSWINT=1) AND disable interrupts
* (ENABLE=0 && WE_ENABLE=1). Configuration settings will be preserved because

4
arch/arm/src/lpc313x/lpc313x_pllconfig.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc313x/lpc313x_pllconfig.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* References:
@ -89,7 +89,7 @@ lpc313x_switchdomains(const struct lpc313x_pllconfig_s * const cfg)
{
/* Get the switch status registers (SSR) for this frequency input domain */
address = LPC313X_CGU_SSR_OFFSET(i);
address = LPC313X_CGU_SSR(i);
regval = getreg32(address);
/* Check if the current frequency selection is the PLL-to-be-configured */

4
arch/arm/src/lpc313x/lpc313x_setfdiv.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc313x/lpc313x_setfdiv.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -95,7 +95,7 @@ void lpc313x_setfdiv(enum lpc313x_domainid_e dmnid,
{
/* Yes.. Save the current reference frequency selection */
regaddr = LPC313X_CGU_SSR_OFFSET((int)dmnid);
regaddr = LPC313X_CGU_SSR((int)dmnid);
basefreq = (getreg32(regaddr) & CGU_SSR_FS_MASK) >> CGU_SSR_FS_SHIFT;
/* Switch domain to FFAST input */

4
arch/arm/src/lpc313x/lpc313x_setfreqin.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc313x/lpc313x_setfreqin.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* References:
@ -92,7 +92,7 @@ void lpc313x_selectfreqin(enum lpc313x_domainid_e dmnid, uint32_t finsel)
/* If FS1 is currently enabled set the reference clock to FS2 and enable FS2 */
if (getreg32(LPC313X_CGU_SSR(dmnid) & CGU_SSR_FS1STAT) != 0)
if ((getreg32(LPC313X_CGU_SSR(dmnid)) & CGU_SSR_FS1STAT) != 0)
{
/* Check if the selected frequency, FS1, is same as requested */