First cut at DMA code
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2142 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
1d90504a84
commit
f04860aa46
@ -39,10 +39,15 @@
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <semaphore.h>
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#include <debug.h>
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#include <errno.h>
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#include <arch/irq.h>
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#include "up_arch.h"
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#include "os_internal.h"
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#include "chip.h"
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#include "stm32_dma.h"
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#include "stm32_internal.h"
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@ -50,23 +55,262 @@
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define DMA1_NCHANNELS 7
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#if STM32_NDMA > 1
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# define DMA2_NCHANNELS 5
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# define DMA_NCHANNELS (DMA1_NCHANNELS+DMA2_NCHANNELS)
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#else
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# define DMA_NCHANNELS DMA1_NCHANNELS
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#endif
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/* Convert the DMA channel base address to the DMA register block address */
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#define DMA_BASE(ch) (ch & 0xfffffc00)
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* Pinch a byte if is possible if there are not very many DMA channels */
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#if DMA_NCHANNELS > 8
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typedef uint16 dma_bitset_t;
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#else
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typedef uint8 dma_bitset_t;
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#endif
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/* This structure descibes one DMA channel */
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struct stm32_dma_s
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{
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ubyte chan; /* DMA channel number */
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ubyte irq; /* DMA channel IRQ number */
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uint32 base; /* DMA register channel base address */
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dma_callback_t callback; /* Callback invoked when the DMA completes */
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* This bitset indicates which DMA channels have been allocated */
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static dma_bitset_t g_dmaallocated;
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static sem_t g_allocsem;
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/* This array describes the state of each DMA */
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static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
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{
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{
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.chan = 0,
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.irq = STM32_IRQ_DMA1CH1,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0),
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},
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{
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.chan = 1,
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.irq = STM32_IRQ_DMA1CH2,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1),
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},
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{
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.chan = 2,
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.irq = STM32_IRQ_DMA1CH3,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2),
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},
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{
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.chan = 3,
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.irq = STM32_IRQ_DMA1CH4,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3),
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},
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{
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.chan = 4,
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.irq = STM32_IRQ_DMA1CH5,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4),
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},
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{
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.chan = 5,
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.irq = STM32_IRQ_DMA1CH6,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5),
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},
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{
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.chan = 6,
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.irq = STM32_IRQ_DMA1CH7,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6),
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},
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#if STM32_NDMA > 1
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{
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.chan = 7,
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.irq = STM32_IRQ_DMA2CH1,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0),
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},
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{
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.chan = 8,
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.irq = STM32_IRQ_DMA2CH2,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1),
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},
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{
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.chan = 9,
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.irq = STM32_IRQ_DMA2CH3,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2),
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},
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{
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.chan = 10,
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.irq = STM32_IRQ_DMA2CH4,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3),
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},
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{
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.chan = 11,
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.irq = STM32_IRQ_DMA2CH5,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4),
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},
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#endif
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Global Functions
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* DMA register access functions
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****************************************************************************/
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/* Get non-channel register from DMA1 or DMA2 */
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static inline uint32 dmabase_getreg(struct stm32_dma_s *dmach, uint32 offset)
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{
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return getreg32(DMA_BASE(dmach->base) + offset);
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}
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/* Write to non-channel register in DMA1 or DMA2 */
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static inline void dmabase_putreg(struct stm32_dma_s *dmach, uint32 offset, uint32 value)
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{
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putreg32(value, DMA_BASE(dmach->base) + offset);
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}
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/* Get channel register from DMA1 or DMA2 */
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static inline uint32 dmachan_getreg(struct stm32_dma_s *dmach, uint32 offset)
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{
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return getreg32(dmach->base + offset);
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}
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/* Write to channel register in DMA1 or DMA2 */
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static inline void dmachan_putreg(struct stm32_dma_s *dmach, uint32 offset, uint32 value)
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{
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putreg32(value, dmach->base + offset);
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}
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/************************************************************************************
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* Name: stm32_dmatake() and stm32_dmagive()
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*
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* Description:
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* Take/give semaphore that protects the channel allocation bitset
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*
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************************************************************************************/
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static void stm32_dmatake(void)
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{
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/* Take the semaphore (perhaps waiting) */
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while (sem_wait(&g_allocsem) != 0)
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{
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/* The only case that an error should occur here is if the wait was awakened
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* by a signal.
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*/
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ASSERT(errno == EINTR);
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}
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}
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static inline void stm32_dmagive(void)
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{
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(void)sem_post(&g_allocsem);
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}
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/************************************************************************************
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* Name: stm32_dmainterrupt
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*
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* Description:
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* DMA interrupt handler
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*
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************************************************************************************/
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static int stm32_dmainterrupt(int irq, void *context)
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{
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struct stm32_dma_s *dmach;
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uint32 isr;
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int chan;
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/* Get the channel structure from the interrupt number */
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if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7)
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{
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chan = irq - STM32_IRQ_DMA1CH1;
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}
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else
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#if STM32_NDMA > 1
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if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5)
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{
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chan = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS;
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}
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else
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#endif
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{
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PANIC(OSERR_INTERNAL);
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}
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dmach = &g_dma[chan];
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/* Get the interrupt status (for this channel only) */
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isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & ~DMA_ISR_CHAN_MASK(chan);
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/* Clear pending interrupts (for this channel only) */
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dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr);
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/* Invoke the callback */
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if (dmach->callback)
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{
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dmach->callback(dmach, isr >> DMA_ISR_CHAN_SHIFT(chan));
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}
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_dmainitialize
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*
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* Description:
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* Initialize the DMA subsystem
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void weak_function stm32_dmainitialize(void)
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{
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int chan;
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/* Initialize the semaphore used to protect the allocation bitset */
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sem_init(&g_allocsem, 0, 1);
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/* Attach DMA interrupt vectors */
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for (chan = 0; chan < DMA_NCHANNELS; chan++)
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{
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irq_attach(g_dma[chan].irq, stm32_dmainterrupt);
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}
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}
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/****************************************************************************
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* Name: stm32_dmachannel
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*
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@ -80,5 +324,116 @@
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DMA_HANDLE stm32_dmachannel(void)
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{
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return NULL;
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struct stm32_dma_s *dmach = NULL;
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int chan;
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int bit;
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/* Make sure that we exclusive access to the DMA bitset */
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stm32_dmatake();
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/* Try each possible channel */
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for (chan = 0, bit = 1; chan < DMA_NCHANNELS; chan++, bit <<= 1)
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{
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/* Has this channel been allocated? */
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if ((g_dmaallocated & bit) == 0)
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{
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/* No.. grab it and return */
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g_dmaallocated |= bit;
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dmach = &g_dma[chan];
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break;
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}
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}
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stm32_dmagive();
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return (DMA_HANDLE)dmach;
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}
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/****************************************************************************
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* Name: stm32_dmasetup
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*
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* Description:
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* Configure DMA before using
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*
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****************************************************************************/
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void stm32_dmasetup(DMA_HANDLE handle, uint32 paddr, uint32 maddr, size_t ntransfers, uint32 ccr)
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{
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struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
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uint32 regval;
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/* Set the peripheral register address in the DMA_CPARx register. The data
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* will be moved from/to this address to/from the memory after the
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* peripheral event.
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*/
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dmachan_putreg(dmach, STM32_DMACHAN_CPAR_OFFSET, paddr);
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/* Set the memory address in the DMA_CMARx register. The data will be
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* written to or read from this memory after the peripheral event.
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*/
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dmachan_putreg(dmach, STM32_DMACHAN_CMAR_OFFSET, maddr);
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/* Configure the total number of data to be transferred in the DMA_CNDTRx
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* register. After each peripheral event, this value will be decremented.
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*/
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dmachan_putreg(dmach, STM32_DMACHAN_CNDTR_OFFSET, ntransfers);
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/* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx
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* register. Configure data transfer direction, circular mode, peripheral & memory
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* incremented mode, peripheral & memory data size, and interrupt after
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* half and/or full transfer in the DMA_CCRx register.
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*/
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regval = dmachan_gettreg(dmach, STM32_DMACHAN_CCR_OFFSET);
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regval &= ~(DMA_CCR_MEM2MEM|DMA_CCR_PL_MASK|DMA_CCR_MSIZE_MASK|DMA_CCR_PSIZE_MASK|
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DMA_CCR_MINC|DMA_CCR_PINC|DMA_CCR_CIRC|DMA_CCR_DIR);
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ccr &= (DMA_CCR_MEM2MEM|DMA_CCR_PL_MASK|DMA_CCR_MSIZE_MASK|DMA_CCR_PSIZE_MASK|
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DMA_CCR_MINC|DMA_CCR_PINC|DMA_CCR_CIRC|DMA_CCR_DIR);
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regval |= ccr;
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dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval);
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}
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/****************************************************************************
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* Name: stm32_dmastart
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*
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* Description:
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* Start the DMA transfer
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*
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****************************************************************************/
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void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, boolean half)
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{
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struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
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int irq;
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uint32 ccr;
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DEBUGASSERT(handle != NULL);
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/* Save the callback. This will be invoked whent the DMA commpletes */
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dmach->callback = callback;
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/* Activate the channel by setting the ENABLE bit in the DMA_CCRx register.
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* As soon as the channel is enabled, it can serve any DMA request from the
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* peripheral connected on the channel.
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*/
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ccr = dmachan_gettreg(dmach, STM32_DMACHAN_CCR_OFFSET);
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ccr |= DMA_CCR_EN;
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/* Once half of the bytes are transferred, the half-transfer flag (HTIF) is
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* set and an interrupt is generated if the Half-Transfer Interrupt Enable
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* bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag
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* (TCIF) is set and an interrupt is generated if the Transfer Complete
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* Interrupt Enable bit (TCIE) is set.
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*/
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ccr |= (half ? (DMA_CCR_HTIE|DMA_CCR_TEIE) : (DMA_CCR_TCIE|DMA_CCR_TEIE));
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dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr);
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}
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@ -60,10 +60,20 @@
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/* Register Offsets *****************************************************************/
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#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
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#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
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#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
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#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
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#define STM32_DMACHAN_OFFSET(n) (0x0014*(n))
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#define STM32_DMACHAN_CCR_OFFSET 0x0008
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#define STM32_DMACHAN_CNDTR_OFFSET 0x000c
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#define STM32_DMACHAN_CPAR_OFFSET 0x0010
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#define STM32_DMACHAN_CMAR_OFFSET 0x0014
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#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n))
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#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n))
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#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n))
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#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n))
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#define STM32_DMA_CCR_OFFSET(n) (0x0008+0x0014*(n))
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#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
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#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
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#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
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@ -72,7 +82,6 @@
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#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
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#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
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#define STM32_DMA_CNDTR_OFFSET(n) (0x000c+0x0014*(n))
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#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
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#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
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#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
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@ -81,7 +90,6 @@
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#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
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#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
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#define STM32_DMA_CPAR_OFFSET(n) (0x0010+0x0014*(n))
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#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
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#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
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#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
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@ -90,7 +98,6 @@
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#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
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#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
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#define STM32_DMA_CMAR_OFFSET(n) (0x0014+0x0014*(n))
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#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
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#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
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#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
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@ -101,102 +108,132 @@
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/* Register Addresses ***************************************************************/
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#define STM32_DMA_ISRC (STM32_DMA_BASE+STM32_DMA_ISRC_OFFSET)
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#define STM32_DMA_IFCR (STM32_DMA_BASE+STM32_DMA_IFCR_OFFSET)
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#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET)
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#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET)
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#define STM32_DMA_CCR(n) (STM32_DMA_BASE+STM32_DMA_CCR_OFFSET(n))
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#define STM32_DMA_CCR1 (STM32_DMA_BASE+STM32_DMA_CCR1_OFFSET)
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#define STM32_DMA_CCR2 (STM32_DMA_BASE+STM32_DMA_CCR2_OFFSET)
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#define STM32_DMA_CCR3 (STM32_DMA_BASE+STM32_DMA_CCR3_OFFSET)
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#define STM32_DMA_CCR4 (STM32_DMA_BASE+STM32_DMA_CCR4_OFFSET)
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#define STM32_DMA_CCR5 (STM32_DMA_BASE+STM32_DMA_CCR5_OFFSET)
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||||
#define STM32_DMA_CCR6 (STM32_DMA_BASE+STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA_CCR7 (STM32_DMA_BASE+STM32_DMA_CCR7_OFFSET)
|
||||
#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32_DMA_CNDTR(n) (STM32_DMA_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA_CNDTR1 (STM32_DMA_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA_CNDTR2 (STM32_DMA_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA_CNDTR3 (STM32_DMA_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA_CNDTR4 (STM32_DMA_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA_CNDTR5 (STM32_DMA_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA_CNDTR6 (STM32_DMA_BASE+STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA_CNDTR7 (STM32_DMA_BASE+STM32_DMA_CNDTR7_OFFSET)
|
||||
#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32_DMA_CPAR(n) (STM32_DMA_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA_CPAR1 (STM32_DMA_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA_CPAR2 (STM32_DMA_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA_CPAR3 (STM32_DMA_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA_CPAR4 (STM32_DMA_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA_CPAR5 (STM32_DMA_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA_CPAR6 (STM32_DMA_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA_CPAR7 (STM32_DMA_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32_DMA_CMAR(n) (STM32_DMA_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA_CMAR1 (STM32_DMA_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA_CMAR2 (STM32_DMA_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA_CMAR3 (STM32_DMA_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA_CMAR4 (STM32_DMA_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA_CMAR5 (STM32_DMA_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA_CMAR6 (STM32_DMA_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA_CMAR7 (STM32_DMA_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
#define DMA_CHAN_SHIFT(n) ((n) << 2)
|
||||
#define DMA_CHAN_MASK 0x0f
|
||||
#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */
|
||||
#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */
|
||||
#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */
|
||||
#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */
|
||||
|
||||
/* DMA interrupt status register */
|
||||
|
||||
#define DMA_ISRC_CHAN_SHIFT(n) (4*(n))
|
||||
#define DMA_ISRC_CHAN_MASK(n) (0x0f << DMA_ISRC_CHAN_SHIFT(n))
|
||||
#define DMA_ISRC_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */
|
||||
#define DMA_ISRC_CHAN1_MASK (0x0f << DMA_ISRC_CHAN1_SHIFT)
|
||||
#define DMA_ISRC_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */
|
||||
#define DMA_ISRC_CHAN2_MASK (0x0f << DMA_ISRC_CHAN2_SHIFT)
|
||||
#define DMA_ISRC_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */
|
||||
#define DMA_ISRC_CHAN3_MASK (0x0f << DMA_ISRC_CHAN3_SHIFT)
|
||||
#define DMA_ISRC_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */
|
||||
#define DMA_ISRC_CHAN4_MASK (0x0f << DMA_ISRC_CHAN4_SHIFT)
|
||||
#define DMA_ISRC_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */
|
||||
#define DMA_ISRC_CHAN5_MASK (0x0f << DMA_ISRC_CHAN5_SHIFT)
|
||||
#define DMA_ISRC_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */
|
||||
#define DMA_ISRC_CHAN6_MASK (0x0f << DMA_ISRC_CHAN6_SHIFT)
|
||||
#define DMA_ISRC_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
|
||||
#define DMA_ISRC_CHAN7_MASK (0x0f << DMA_ISRC_CHAN7_SHIFT)
|
||||
#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
|
||||
#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */
|
||||
#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT)
|
||||
#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */
|
||||
#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT)
|
||||
#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */
|
||||
#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT)
|
||||
#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */
|
||||
#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT)
|
||||
#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */
|
||||
#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT)
|
||||
#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */
|
||||
#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT)
|
||||
#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
|
||||
#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT)
|
||||
|
||||
#define DMA_ISRC_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */
|
||||
#define DMA_ISRC_GIF(n) (DMA_ISRC_GIF_BIT << DMA_ISRC_CHAN_SHIFT(n))
|
||||
#define DMA_ISRC_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */
|
||||
#define DMA_ISRC_TCIF(n) (DMA_ISRC_TCIF_BIT << DMA_ISRC_CHAN_SHIFT(n))
|
||||
#define DMA_ISRC_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */
|
||||
#define DMA_ISRC_HTIF(n) (DMA_ISRC_HTIF_BIT << DMA_ISRC_CHAN_SHIFT(n))
|
||||
#define DMA_ISRC_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */
|
||||
#define DMA_ISRC_TEIF(n) (DMA_ISRC_TEIF_BIT << DMA_ISRC_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
|
||||
/* DMA interrupt flag clear register */
|
||||
|
||||
#define DMA_IFCR_CHAN_SHIFT(n) (4*(n))
|
||||
#define DMA_IFCR_CHAN_MASK(n) (0x0f << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
|
||||
#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN1_MASK (0x0f << DMA_IFCR_CHAN1_SHIFT)
|
||||
#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT)
|
||||
#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN2_MASK (0x0f << DMA_IFCR_CHAN2_SHIFT)
|
||||
#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT)
|
||||
#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN3_MASK (0x0f << DMA_IFCR_CHAN3_SHIFT)
|
||||
#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT)
|
||||
#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN4_MASK (0x0f << DMA_IFCR_CHAN4_SHIFT)
|
||||
#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT)
|
||||
#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN5_MASK (0x0f << DMA_IFCR_CHAN5_SHIFT)
|
||||
#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT)
|
||||
#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN6_MASK (0x0f << DMA_IFCR_CHAN6_SHIFT)
|
||||
#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
|
||||
#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN7_MASK (0x0f << DMA_IFCR_CHAN7_SHIFT)
|
||||
#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
|
||||
|
||||
#define DMA_IFCR_CGIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt clear */
|
||||
#define DMA_IFCR_CGIF(n) (DMA_IFCR_CGIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CTCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete clear */
|
||||
#define DMA_IFCR_CTCIF(n) (DMA_IFCR_CTCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CHTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer clear */
|
||||
#define DMA_IFCR_CHTIF(n) (DMA_IFCR_CHTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CTEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error clear */
|
||||
#define DMA_IFCR_CTEIF(n) (DMA_IFCR_CTEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
|
||||
/* DMA channel configuration register */
|
||||
|
||||
|
||||
@ -380,6 +380,7 @@
|
||||
************************************************************************************/
|
||||
|
||||
typedef FAR void *DMA_HANDLE;
|
||||
typedef void (*dma_callback_t)(DMA_HANDLE handle, ubyte isr);
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
@ -476,6 +477,19 @@ EXTERN int stm32_dumpgpio(uint32 pinset, const char *msg);
|
||||
# define stm32_dumpgpio(p,m)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmainitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the DMA subsystem
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void weak_function stm32_dmainitialize(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmachannel
|
||||
*
|
||||
@ -489,6 +503,27 @@ EXTERN int stm32_dumpgpio(uint32 pinset, const char *msg);
|
||||
|
||||
EXTERN DMA_HANDLE stm32_dmachannel(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmasetup
|
||||
*
|
||||
* Description:
|
||||
* Configure DMA before using
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void stm32_dmasetup(DMA_HANDLE handle, uint32 paddr, uint32 maddr,
|
||||
size_t ntransfers, uint32 ccr);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmastart
|
||||
*
|
||||
* Description:
|
||||
* Start the DMA transfer
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, boolean half);
|
||||
|
||||
/************************************************************************************
|
||||
* Function: stm32_ethinitialize
|
||||
*
|
||||
|
||||
@ -869,7 +869,7 @@ void stm32_spitake(FAR struct spi_dev_s *dev)
|
||||
* by a signal.
|
||||
*/
|
||||
|
||||
ASSERT(*get_errno_ptr() == EINTR);
|
||||
ASSERT(errno == EINTR);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -72,6 +72,15 @@
|
||||
|
||||
void stm32_boardinitialize(void)
|
||||
{
|
||||
/* Initialize the DMA subsystem if the weak function stm32_dmainitialize has been
|
||||
* brought into the build
|
||||
*/
|
||||
|
||||
if (stm32_dmainitialize)
|
||||
{
|
||||
stm32_dmainitialize();
|
||||
}
|
||||
|
||||
/* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function
|
||||
* stm32_spiinitialize() has been brought into the link.
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user