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Add SAMA5 GPIO configuration support

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This commit is contained in:
Gregory Nutt 2013-07-22 20:59:47 -06:00
parent 339a55f1ea
commit f07d09aa48
10 changed files with 1675 additions and 196 deletions
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2
ChangeLog
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@ -5159,4 +5159,6 @@
* arch/arm/src/sama5/sam_lowputc.c and sam_serial.c: Add support
for SAMA5 UARTs. Does not even compile as of initial checkin.
(2013-7-22).
* arch/arm/src/sama5/sam_gpio.c: Add GPIO configuratino support
for the SAMA5. Still compilation issues. (2013-7-22).

6
arch/arm/src/sam34/sam4s_gpio.h
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@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H
#define __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H
#ifndef __ARCH_ARM_SRC_SAM34_SAM4S_GPIO_H
#define __ARCH_ARM_SRC_SAM34_SAM4S_GPIO_H
/************************************************************************************
* Included Files
@ -203,4 +203,4 @@ extern "C"
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H */
#endif /* __ARCH_ARM_SRC_SAM34_SAM4S_GPIO_H */

4
arch/arm/src/sama5/Make.defs
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@ -62,5 +62,5 @@ endif
CHIP_ASRCS =
CHIP_CSRCS = sam_boot.c sam_clockconfig.c sam_irq.c sam_lowputc.c
CHIP_CSRCS += sam_serial.c sam_timerisr.c
CHIP_CSRCS = sam_boot.c sam_clockconfig.c sam_gpio.c sam_irq.c
CHIP_CSRCS += sam_lowputc.c sam_serial.c sam_timerisr.c

588
arch/arm/src/sama5/chip/sam_pio.h Normal file
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@ -0,0 +1,588 @@
/****************************************************************************************
* arch/arm/src/sama5/chip/sam_pio.h
* Parallel Input/Output (PIO) Controller definitions for the SAMA5
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PIO_H
#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PIO_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* PIO register offsets *****************************************************************/
#define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */
#define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */
#define SAM_PIO_PSR_OFFSET 0x0008 /* PIO Status Register */
/* 0x000c: Reserved */
#define SAM_PIO_OER_OFFSET 0x0010 /* Output Enable Register */
#define SAM_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */
#define SAM_PIO_OSR_OFFSET 0x0018 /* Output Status Register */
/* 0x001c: Reserved */
#define SAM_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */
#define SAM_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */
#define SAM_PIO_IFSR_OFFSET 0x0028 /* Glitch Input Filter Status Register */
/* 0x002c: Reserved */
#define SAM_PIO_SODR_OFFSET 0x0030 /* Set Output Data Register */
#define SAM_PIO_CODR_OFFSET 0x0034 /* Clear Output Data Register */
#define SAM_PIO_ODSR_OFFSET 0x0038 /* Output Data Status Register */
#define SAM_PIO_PDSR_OFFSET 0x003c /* Pin Data Status Register */
#define SAM_PIO_IER_OFFSET 0x0040 /* Interrupt Enable Register */
#define SAM_PIO_IDR_OFFSET 0x0044 /* Interrupt Disable Register */
#define SAM_PIO_IMR_OFFSET 0x0048 /* Interrupt Mask Register */
#define SAM_PIO_ISR_OFFSET 0x004c /* Interrupt Status Register */
#define SAM_PIO_MDER_OFFSET 0x0050 /* Multi-driver Enable Register */
#define SAM_PIO_MDDR_OFFSET 0x0054 /* Multi-driver Disable Register */
#define SAM_PIO_MDSR_OFFSET 0x0058 /* Multi-driver Status Register */
/* 0x005c: Reserved */
#define SAM_PIO_PUDR_OFFSET 0x0060 /* Pull-up Disable Register */
#define SAM_PIO_PUER_OFFSET 0x0064 /* Pull-up Enable Register */
#define SAM_PIO_PUSR_OFFSET 0x0068 /* Pad Pull-up Status Register */
/* 0x006c: Reserved */
#define SAM_PIO_ABCDSR1_OFFSET 0x0070 /* Peripheral Select Register 1 */
#define SAM_PIO_ABCDSR2_OFFSET 0x0074 /* Peripheral Select Register 2 */
/* 0x0078-0x007c: Reserved */
#define SAM_PIO_IFSCDR_OFFSET 0x0080 /* Input Filter Slow Clock Disable Register */
#define SAM_PIO_IFSCER_OFFSET 0x0084 /* Input Filter Slow Clock Enable Register */
#define SAM_PIO_IFSCSR_OFFSET 0x0088 /* Input Filter Slow Clock Status Register */
#define SAM_PIO_SCDR_OFFSET 0x008c /* Slow Clock Divider Debouncing Register */
#define SAM_PIO_PPDDR_OFFSET 0x0090 /* Pad Pull Down Disable Register */
#define SAM_PIO_PPDER_OFFSET 0x0094 /* PIO Pad Pull Down Enable Register */
#define SAM_PIO_PPDSR_OFFSET 0x0098 /* PIO Pad Pull Down Status Register */
/* 0x009c: Reserved */
#define SAM_PIO_OWER_OFFSET 0x00a0 /* Output Write Enable */
#define SAM_PIO_OWDR_OFFSET 0x00a4 /* Output Write Disable */
#define SAM_PIO_OWSR_OFFSET 0x00a8 /* Output Write Status Register */
/* 0x00ac: Reserved */
#define SAM_PIO_AIMER_OFFSET 0x00b0 /* Additional Interrupt Modes Enable Register */
#define SAM_PIO_AIMDR_OFFSET 0x00b4 /* Additional Interrupt Modes Disables Register */
#define SAM_PIO_AIMMR_OFFSET 0x00b8 /* Additional Interrupt Modes Mask Register */
/* 0x00bc: Reserved */
#define SAM_PIO_ESR_OFFSET 0x00c0 /* Edge Select Register */
#define SAM_PIO_LSR_OFFSET 0x00c4 /* Level Select Register */
#define SAM_PIO_ELSR_OFFSET 0x00c8 /* Edge/Level Status Register */
/* 0x00cc: Reserved */
#define SAM_PIO_FELLSR_OFFSET 0x00d0 /* Falling Edge/Low Level Select Register */
#define SAM_PIO_REHLSR_OFFSET 0x00d4 /* Rising Edge/ High Level Select Register */
#define SAM_PIO_FRLHSR_OFFSET 0x00d8 /* Fall/Rise - Low/High Status Register */
/* 0x00dc: Reserved */
#define SAM_PIO_LOCKSR_OFFSET 0x00e0 /* Lock Status */
#define SAM_PIO_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
#define SAM_PIO_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
/* 0x00ec-0x00f8: Reserved */
#define SAM_PIO_SCHMITT_OFFSET 0x0100 /* Schmitt Trigger Register */
/* 0x0104-0x114: Reserved */
#define SAM_PIO_DRIVER1_OFFSET 0x0118 /* I/O Drive Register 1 */
#define SAM_PIO_DRIVER2_OFFSET 0x011c /* I/O Drive Register 2 */
/* 0x0120-0x14c: Reserved */
#define SAM_PIO_PCIER_OFFSET 0x0154 /* Parallel Capture Interrupt Enable Register */
#define SAM_PIO_PCIDR_OFFSET 0x0158 /* Parallel Capture Interrupt Disable Register */
#define SAM_PIO_PCIMR_OFFSET 0x015c /* Parallel Capture Interrupt Mask Register */
#define SAM_PIO_PCISR_OFFSET 0x0160 /* Parallel Capture Interrupt Status Register */
#define SAM_PIO_PCRHR_OFFSET 0x0164 /* Parallel Capture Reception Holding Register */
/* 0x0168-0x018c: Reserved for PDC registers */
/* PIO register adresses ****************************************************************/
#define PIOA (0)
#define PIOB (1)
#define PIOC (2)
#define NPIO (3)
#define SAM_PIO_PER(n) (SAM_PIO_VBASE(n)+SAM_PIO_PER_OFFSET)
#define SAM_PIO_PDR(n) (SAM_PIO_VBASE(n)+SAM_PIO_PDR_OFFSET)
#define SAM_PIO_PSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_PSR_OFFSET)
#define SAM_PIO_OER(n) (SAM_PIO_VBASE(n)+SAM_PIO_OER_OFFSET)
#define SAM_PIO_ODR(n) (SAM_PIO_VBASE(n)+SAM_PIO_ODR_OFFSET)
#define SAM_PIO_OSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_OSR_OFFSET)
#define SAM_PIO_IFER(n) (SAM_PIO_VBASE(n)+SAM_PIO_IFER_OFFSET)
#define SAM_PIO_IFDR(n) (SAM_PIO_VBASE(n)+SAM_PIO_IFDR_OFFSET)
#define SAM_PIO_IFSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_IFSR_OFFSET)
#define SAM_PIO_SODR(n) (SAM_PIO_VBASE(n)+SAM_PIO_SODR_OFFSET)
#define SAM_PIO_CODR(n) (SAM_PIO_VBASE(n)+SAM_PIO_CODR_OFFSET)
#define SAM_PIO_ODSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_ODSR_OFFSET)
#define SAM_PIO_PDSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_PDSR_OFFSET)
#define SAM_PIO_IER(n) (SAM_PIO_VBASE(n)+SAM_PIO_IER_OFFSET)
#define SAM_PIO_IDR(n) (SAM_PIO_VBASE(n)+SAM_PIO_IDR_OFFSET)
#define SAM_PIO_IMR(n) (SAM_PIO_VBASE(n)+SAM_PIO_IMR_OFFSET)
#define SAM_PIO_ISR(n) (SAM_PIO_VBASE(n)+SAM_PIO_ISR_OFFSET)
#define SAM_PIO_MDER(n) (SAM_PIO_VBASE(n)+SAM_PIO_MDER_OFFSET)
#define SAM_PIO_MDDR(n) (SAM_PIO_VBASE(n)+SAM_PIO_MDDR_OFFSET)
#define SAM_PIO_MDSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_MDSR_OFFSET)
#define SAM_PIO_PUDR(n) (SAM_PIO_VBASE(n)+SAM_PIO_PUDR_OFFSET)
#define SAM_PIO_PUER(n) (SAM_PIO_VBASE(n)+SAM_PIO_PUER_OFFSET)
#define SAM_PIO_PUSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_PUSR_OFFSET)
#define SAM_PIO_ABCDSR1(n) (SAM_PIO_VBASE(n)+SAM_PIO_ABCDSR1_OFFSET)
#define SAM_PIO_ABCDSR2(n) (SAM_PIO_VBASE(n)+SAM_PIO_ABCDSR2_OFFSET)
#define SAM_PIO_IFSCDR(n) (SAM_PIO_VBASE(n)+SAM_PIO_IFSCDR_OFFSET)
#define SAM_PIO_IFSCER(n) (SAM_PIO_VBASE(n)+SAM_PIO_IFSCER_OFFSET)
#define SAM_PIO_IFSCSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_IFSCSR_OFFSET)
#define SAM_PIO_SCDR(n) (SAM_PIO_VBASE(n)+SAM_PIO_SCDR_OFFSET)
#define SAM_PIO_PPDDR(n) (SAM_PIO_VBASE(n)+SAM_PIO_PPDDR_OFFSET)
#define SAM_PIO_PPDER(n) (SAM_PIO_VBASE(n)+SAM_PIO_PPDER_OFFSET)
#define SAM_PIO_PPDSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_PPDSR_OFFSET)
#define SAM_PIO_OWER(n) (SAM_PIO_VBASE(n)+SAM_PIO_OWER_OFFSET)
#define SAM_PIO_OWDR(n) (SAM_PIO_VBASE(n)+SAM_PIO_OWDR_OFFSET)
#define SAM_PIO_OWSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_OWSR_OFFSET)
#define SAM_PIO_AIMER(n) (SAM_PIO_VBASE(n)+SAM_PIO_AIMER_OFFSET)
#define SAM_PIO_AIMDR(n) (SAM_PIO_VBASE(n)+SAM_PIO_AIMDR_OFFSET)
#define SAM_PIO_AIMMR(n) (SAM_PIO_VBASE(n)+SAM_PIO_AIMMR_OFFSET)
#define SAM_PIO_ESR(n) (SAM_PIO_VBASE(n)+SAM_PIO_ESR_OFFSET)
#define SAM_PIO_LSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_LSR_OFFSET)
#define SAM_PIO_ELSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_ELSR_OFFSET)
#define SAM_PIO_FELLSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_FELLSR_OFFSET)
#define SAM_PIO_REHLSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_REHLSR_OFFSET)
#define SAM_PIO_FRLHSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_FRLHSR_OFFSET)
#define SAM_PIO_LOCKSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_LOCKSR_OFFSET)
#define SAM_PIO_WPMR(n) (SAM_PIO_VBASE(n)+SAM_PIO_WPMR_OFFSET)
#define SAM_PIO_WPSR(n) (SAM_PIO_VBASE(n)+SAM_PIO_WPSR_OFFSET)
#define SAM_PIO_SCHMITT(n) (SAM_PIO_VBASE(n)+SAM_PIO_SCHMITT_OFFSET)
#define SAM_PIO_DRIVER1(n) (SAM_PIO_VBASE(n)+SAM_PIO_DRIVER1_OFFSET)
#define SAM_PIO_DRIVER2(n) (SAM_PIO_VBASE(n)+SAM_PIO_DRIVER2_OFFSET)
#define SAM_PIOA_PER (SAM_PIOA_VBASE+SAM_PIO_PER_OFFSET)
#define SAM_PIOA_PDR (SAM_PIOA_VBASE+SAM_PIO_PDR_OFFSET)
#define SAM_PIOA_PSR (SAM_PIOA_VBASE+SAM_PIO_PSR_OFFSET)
#define SAM_PIOA_OER (SAM_PIOA_VBASE+SAM_PIO_OER_OFFSET)
#define SAM_PIOA_ODR (SAM_PIOA_VBASE+SAM_PIO_ODR_OFFSET)
#define SAM_PIOA_OSR (SAM_PIOA_VBASE+SAM_PIO_OSR_OFFSET)
#define SAM_PIOA_IFER (SAM_PIOA_VBASE+SAM_PIO_IFER_OFFSET)
#define SAM_PIOA_IFDR (SAM_PIOA_VBASE+SAM_PIO_IFDR_OFFSET)
#define SAM_PIOA_IFSR (SAM_PIOA_VBASE+SAM_PIO_IFSR_OFFSET)
#define SAM_PIOA_SODR (SAM_PIOA_VBASE+SAM_PIO_SODR_OFFSET)
#define SAM_PIOA_CODR (SAM_PIOA_VBASE+SAM_PIO_CODR_OFFSET)
#define SAM_PIOA_ODSR (SAM_PIOA_VBASE+SAM_PIO_ODSR_OFFSET)
#define SAM_PIOA_PDSR (SAM_PIOA_VBASE+SAM_PIO_PDSR_OFFSET)
#define SAM_PIOA_IER (SAM_PIOA_VBASE+SAM_PIO_IER_OFFSET)
#define SAM_PIOA_IDR (SAM_PIOA_VBASE+SAM_PIO_IDR_OFFSET)
#define SAM_PIOA_IMR (SAM_PIOA_VBASE+SAM_PIO_IMR_OFFSET)
#define SAM_PIOA_ISR (SAM_PIOA_VBASE+SAM_PIO_ISR_OFFSET)
#define SAM_PIOA_MDER (SAM_PIOA_VBASE+SAM_PIO_MDER_OFFSET)
#define SAM_PIOA_MDDR (SAM_PIOA_VBASE+SAM_PIO_MDDR_OFFSET)
#define SAM_PIOA_MDSR (SAM_PIOA_VBASE+SAM_PIO_MDSR_OFFSET)
#define SAM_PIOA_PUDR (SAM_PIOA_VBASE+SAM_PIO_PUDR_OFFSET)
#define SAM_PIOA_PUER (SAM_PIOA_VBASE+SAM_PIO_PUER_OFFSET)
#define SAM_PIOA_PUSR (SAM_PIOA_VBASE+SAM_PIO_PUSR_OFFSET)
#define SAM_PIOA_ABCDSR1 (SAM_PIOA_VBASE+SAM_PIO_ABCDSR1_OFFSET)
#define SAM_PIOA_ABCDSR2 (SAM_PIOA_VBASE+SAM_PIO_ABCDSR2_OFFSET)
#define SAM_PIOA_IFSCDR (SAM_PIOA_VBASE+SAM_PIO_IFSCDR_OFFSET)
#define SAM_PIOA_IFSCER (SAM_PIOA_VBASE+SAM_PIO_IFSCER_OFFSET)
#define SAM_PIOA_IFSCSR (SAM_PIOA_VBASE+SAM_PIO_IFSCSR_OFFSET)
#define SAM_PIOA_SCDR (SAM_PIOA_VBASE+SAM_PIO_SCDR_OFFSET)
#define SAM_PIOA_PPDDR (SAM_PIOA_VBASE+SAM_PIO_PPDDR_OFFSET)
#define SAM_PIOA_PPDER (SAM_PIOA_VBASE+SAM_PIO_PPDER_OFFSET)
#define SAM_PIOA_PPDSR (SAM_PIOA_VBASE+SAM_PIO_PPDSR_OFFSET)
#define SAM_PIOA_OWER (SAM_PIOA_VBASE+SAM_PIO_OWER_OFFSET)
#define SAM_PIOA_OWDR (SAM_PIOA_VBASE+SAM_PIO_OWDR_OFFSET)
#define SAM_PIOA_OWSR (SAM_PIOA_VBASE+SAM_PIO_OWSR_OFFSET)
#define SAM_PIOA_AIMER (SAM_PIOA_VBASE+SAM_PIO_AIMER_OFFSET)
#define SAM_PIOA_AIMDR (SAM_PIOA_VBASE+SAM_PIO_AIMDR_OFFSET)
#define SAM_PIOA_AIMMR (SAM_PIOA_VBASE+SAM_PIO_AIMMR_OFFSET)
#define SAM_PIOA_ESR (SAM_PIOA_VBASE+SAM_PIO_ESR_OFFSET)
#define SAM_PIOA_LSR (SAM_PIOA_VBASE+SAM_PIO_LSR_OFFSET)
#define SAM_PIOA_ELSR (SAM_PIOA_VBASE+SAM_PIO_ELSR_OFFSET)
#define SAM_PIOA_FELLSR (SAM_PIOA_VBASE+SAM_PIO_FELLSR_OFFSET)
#define SAM_PIOA_REHLSR (SAM_PIOA_VBASE+SAM_PIO_REHLSR_OFFSET)
#define SAM_PIOA_FRLHSR (SAM_PIOA_VBASE+SAM_PIO_FRLHSR_OFFSET)
#define SAM_PIOA_LOCKSR (SAM_PIOA_VBASE+SAM_PIO_LOCKSR_OFFSET)
#define SAM_PIOA_WPMR (SAM_PIOA_VBASE+SAM_PIO_WPMR_OFFSET)
#define SAM_PIOA_WPSR (SAM_PIOA_VBASE+SAM_PIO_WPSR_OFFSET)
#define SAM_PIOA_SCHMITT (SAM_PIOA_VBASE+SAM_PIO_SCHMITT_OFFSET)
#define SAM_PIOA_DRIVER1 (SAM_PIOA_VBASE+SAM_PIO_DRIVER1_OFFSET)
#define SAM_PIOA_DRIVER2 (SAM_PIOA_VBASE+SAM_PIO_DRIVER2_OFFSET)
#define SAM_PIOB_PER (SAM_PIOB_VBASE+SAM_PIO_PER_OFFSET)
#define SAM_PIOB_PDR (SAM_PIOB_VBASE+SAM_PIO_PDR_OFFSET)
#define SAM_PIOB_PSR (SAM_PIOB_VBASE+SAM_PIO_PSR_OFFSET)
#define SAM_PIOB_OER (SAM_PIOB_VBASE+SAM_PIO_OER_OFFSET)
#define SAM_PIOB_ODR (SAM_PIOB_VBASE+SAM_PIO_ODR_OFFSET)
#define SAM_PIOB_OSR (SAM_PIOB_VBASE+SAM_PIO_OSR_OFFSET)
#define SAM_PIOB_IFER (SAM_PIOB_VBASE+SAM_PIO_IFER_OFFSET)
#define SAM_PIOB_IFDR (SAM_PIOB_VBASE+SAM_PIO_IFDR_OFFSET)
#define SAM_PIOB_IFSR (SAM_PIOB_VBASE+SAM_PIO_IFSR_OFFSET)
#define SAM_PIOB_SODR (SAM_PIOB_VBASE+SAM_PIO_SODR_OFFSET)
#define SAM_PIOB_CODR (SAM_PIOB_VBASE+SAM_PIO_CODR_OFFSET)
#define SAM_PIOB_ODSR (SAM_PIOB_VBASE+SAM_PIO_ODSR_OFFSET)
#define SAM_PIOB_PDSR (SAM_PIOB_VBASE+SAM_PIO_PDSR_OFFSET)
#define SAM_PIOB_IER (SAM_PIOB_VBASE+SAM_PIO_IER_OFFSET)
#define SAM_PIOB_IDR (SAM_PIOB_VBASE+SAM_PIO_IDR_OFFSET)
#define SAM_PIOB_IMR (SAM_PIOB_VBASE+SAM_PIO_IMR_OFFSET)
#define SAM_PIOB_ISR (SAM_PIOB_VBASE+SAM_PIO_ISR_OFFSET)
#define SAM_PIOB_MDER (SAM_PIOB_VBASE+SAM_PIO_MDER_OFFSET)
#define SAM_PIOB_MDDR (SAM_PIOB_VBASE+SAM_PIO_MDDR_OFFSET)
#define SAM_PIOB_MDSR (SAM_PIOB_VBASE+SAM_PIO_MDSR_OFFSET)
#define SAM_PIOB_PUDR (SAM_PIOB_VBASE+SAM_PIO_PUDR_OFFSET)
#define SAM_PIOB_PUER (SAM_PIOB_VBASE+SAM_PIO_PUER_OFFSET)
#define SAM_PIOB_PUSR (SAM_PIOB_VBASE+SAM_PIO_PUSR_OFFSET)
#define SAM_PIOB_ABCDSR1 (SAM_PIOB_VBASE+SAM_PIO_ABCDSR1_OFFSET)
#define SAM_PIOB_ABCDSR2 (SAM_PIOB_VBASE+SAM_PIO_ABCDSR2_OFFSET)
#define SAM_PIOB_IFSCDR (SAM_PIOB_VBASE+SAM_PIO_IFSCDR_OFFSET)
#define SAM_PIOB_IFSCER (SAM_PIOB_VBASE+SAM_PIO_IFSCER_OFFSET)
#define SAM_PIOB_IFSCSR (SAM_PIOB_VBASE+SAM_PIO_IFSCSR_OFFSET)
#define SAM_PIOB_SCDR (SAM_PIOB_VBASE+SAM_PIO_SCDR_OFFSET)
#define SAM_PIOB_PPDDR (SAM_PIOB_VBASE+SAM_PIO_PPDDR_OFFSET)
#define SAM_PIOB_PPDER (SAM_PIOB_VBASE+SAM_PIO_PPDER_OFFSET)
#define SAM_PIOB_PPDSR (SAM_PIOB_VBASE+SAM_PIO_PPDSR_OFFSET)
#define SAM_PIOB_OWER (SAM_PIOB_VBASE+SAM_PIO_OWER_OFFSET)
#define SAM_PIOB_OWDR (SAM_PIOB_VBASE+SAM_PIO_OWDR_OFFSET)
#define SAM_PIOB_OWSR (SAM_PIOB_VBASE+SAM_PIO_OWSR_OFFSET)
#define SAM_PIOB_AIMER (SAM_PIOB_VBASE+SAM_PIO_AIMER_OFFSET)
#define SAM_PIOB_AIMDR (SAM_PIOB_VBASE+SAM_PIO_AIMDR_OFFSET)
#define SAM_PIOB_AIMMR (SAM_PIOB_VBASE+SAM_PIO_AIMMR_OFFSET)
#define SAM_PIOB_ESR (SAM_PIOB_VBASE+SAM_PIO_ESR_OFFSET)
#define SAM_PIOB_LSR (SAM_PIOB_VBASE+SAM_PIO_LSR_OFFSET)
#define SAM_PIOB_ELSR (SAM_PIOB_VBASE+SAM_PIO_ELSR_OFFSET)
#define SAM_PIOB_FELLSR (SAM_PIOB_VBASE+SAM_PIO_FELLSR_OFFSET)
#define SAM_PIOB_REHLSR (SAM_PIOB_VBASE+SAM_PIO_REHLSR_OFFSET)
#define SAM_PIOB_FRLHSR (SAM_PIOB_VBASE+SAM_PIO_FRLHSR_OFFSET)
#define SAM_PIOB_LOCKSR (SAM_PIOB_VBASE+SAM_PIO_LOCKSR_OFFSET)
#define SAM_PIOB_WPMR (SAM_PIOB_VBASE+SAM_PIO_WPMR_OFFSET)
#define SAM_PIOB_WPSR (SAM_PIOB_VBASE+SAM_PIO_WPSR_OFFSET)
#define SAM_PIOB_SCHMITT (SAM_PIOB_VBASE+SAM_PIO_SCHMITT_OFFSET)
#define SAM_PIOB_DRIVER1 (SAM_PIOB_VBASE+SAM_PIO_DRIVER1_OFFSET)
#define SAM_PIOB_DRIVER2 (SAM_PIOB_VBASE+SAM_PIO_DRIVER2_OFFSET)
#define SAM_PIOC_PER (SAM_PIOC_VBASE+SAM_PIO_PER_OFFSET)
#define SAM_PIOC_PDR (SAM_PIOC_VBASE+SAM_PIO_PDR_OFFSET)
#define SAM_PIOC_PSR (SAM_PIOC_VBASE+SAM_PIO_PSR_OFFSET)
#define SAM_PIOC_OER (SAM_PIOC_VBASE+SAM_PIO_OER_OFFSET)
#define SAM_PIOC_ODR (SAM_PIOC_VBASE+SAM_PIO_ODR_OFFSET)
#define SAM_PIOC_OSR (SAM_PIOC_VBASE+SAM_PIO_OSR_OFFSET)
#define SAM_PIOC_IFER (SAM_PIOC_VBASE+SAM_PIO_IFER_OFFSET)
#define SAM_PIOC_IFDR (SAM_PIOC_VBASE+SAM_PIO_IFDR_OFFSET)
#define SAM_PIOC_IFSR (SAM_PIOC_VBASE+SAM_PIO_IFSR_OFFSET)
#define SAM_PIOC_SODR (SAM_PIOC_VBASE+SAM_PIO_SODR_OFFSET)
#define SAM_PIOC_CODR (SAM_PIOC_VBASE+SAM_PIO_CODR_OFFSET)
#define SAM_PIOC_ODSR (SAM_PIOC_VBASE+SAM_PIO_ODSR_OFFSET)
#define SAM_PIOC_PDSR (SAM_PIOC_VBASE+SAM_PIO_PDSR_OFFSET)
#define SAM_PIOC_IER (SAM_PIOC_VBASE+SAM_PIO_IER_OFFSET)
#define SAM_PIOC_IDR (SAM_PIOC_VBASE+SAM_PIO_IDR_OFFSET)
#define SAM_PIOC_IMR (SAM_PIOC_VBASE+SAM_PIO_IMR_OFFSET)
#define SAM_PIOC_ISR (SAM_PIOC_VBASE+SAM_PIO_ISR_OFFSET)
#define SAM_PIOC_MDER (SAM_PIOC_VBASE+SAM_PIO_MDER_OFFSET)
#define SAM_PIOC_MDDR (SAM_PIOC_VBASE+SAM_PIO_MDDR_OFFSET)
#define SAM_PIOC_MDSR (SAM_PIOC_VBASE+SAM_PIO_MDSR_OFFSET)
#define SAM_PIOC_PUDR (SAM_PIOC_VBASE+SAM_PIO_PUDR_OFFSET)
#define SAM_PIOC_PUER (SAM_PIOC_VBASE+SAM_PIO_PUER_OFFSET)
#define SAM_PIOC_PUSR (SAM_PIOC_VBASE+SAM_PIO_PUSR_OFFSET)
#define SAM_PIOC_ABCDSR1 (SAM_PIOC_VBASE+SAM_PIO_ABCDSR1_OFFSET)
#define SAM_PIOC_ABCDSR2 (SAM_PIOC_VBASE+SAM_PIO_ABCDSR2_OFFSET)
#define SAM_PIOC_IFSCDR (SAM_PIOC_VBASE+SAM_PIO_IFSCDR_OFFSET)
#define SAM_PIOC_IFSCER (SAM_PIOC_VBASE+SAM_PIO_IFSCER_OFFSET)
#define SAM_PIOC_IFSCSR (SAM_PIOC_VBASE+SAM_PIO_IFSCSR_OFFSET)
#define SAM_PIOC_SCDR (SAM_PIOC_VBASE+SAM_PIO_SCDR_OFFSET)
#define SAM_PIOC_PPDDR (SAM_PIOC_VBASE+SAM_PIO_PPDDR_OFFSET)
#define SAM_PIOC_PPDER (SAM_PIOC_VBASE+SAM_PIO_PPDER_OFFSET)
#define SAM_PIOC_PPDSR (SAM_PIOC_VBASE+SAM_PIO_PPDSR_OFFSET)
#define SAM_PIOC_OWER (SAM_PIOC_VBASE+SAM_PIO_OWER_OFFSET)
#define SAM_PIOC_OWDR (SAM_PIOC_VBASE+SAM_PIO_OWDR_OFFSET)
#define SAM_PIOC_OWSR (SAM_PIOC_VBASE+SAM_PIO_OWSR_OFFSET)
#define SAM_PIOC_AIMER (SAM_PIOC_VBASE+SAM_PIO_AIMER_OFFSET)
#define SAM_PIOC_AIMDR (SAM_PIOC_VBASE+SAM_PIO_AIMDR_OFFSET)
#define SAM_PIOC_AIMMR (SAM_PIOC_VBASE+SAM_PIO_AIMMR_OFFSET)
#define SAM_PIOC_ESR (SAM_PIOC_VBASE+SAM_PIO_ESR_OFFSET)
#define SAM_PIOC_LSR (SAM_PIOC_VBASE+SAM_PIO_LSR_OFFSET)
#define SAM_PIOC_ELSR (SAM_PIOC_VBASE+SAM_PIO_ELSR_OFFSET)
#define SAM_PIOC_FELLSR (SAM_PIOC_VBASE+SAM_PIO_FELLSR_OFFSET)
#define SAM_PIOC_REHLSR (SAM_PIOC_VBASE+SAM_PIO_REHLSR_OFFSET)
#define SAM_PIOC_FRLHSR (SAM_PIOC_VBASE+SAM_PIO_FRLHSR_OFFSET)
#define SAM_PIOC_LOCKSR (SAM_PIOC_VBASE+SAM_PIO_LOCKSR_OFFSET)
#define SAM_PIOC_WPMR (SAM_PIOC_VBASE+SAM_PIO_WPMR_OFFSET)
#define SAM_PIOC_WPSR (SAM_PIOC_VBASE+SAM_PIO_WPSR_OFFSET)
#define SAM_PIOC_SCHMITT (SAM_PIOC_VBASE+SAM_PIO_SCHMITT_OFFSET)
#define SAM_PIOC_DRIVER1 (SAM_PIOC_VBASE+SAM_PIO_DRIVER1_OFFSET)
#define SAM_PIOC_DRIVER2 (SAM_PIOC_VBASE+SAM_PIO_DRIVER2_OFFSET)
#define SAM_PIOD_PER (SAM_PIOD_VBASE+SAM_PIO_PER_OFFSET)
#define SAM_PIOD_PDR (SAM_PIOD_VBASE+SAM_PIO_PDR_OFFSET)
#define SAM_PIOD_PSR (SAM_PIOD_VBASE+SAM_PIO_PSR_OFFSET)
#define SAM_PIOD_OER (SAM_PIOD_VBASE+SAM_PIO_OER_OFFSET)
#define SAM_PIOD_ODR (SAM_PIOD_VBASE+SAM_PIO_ODR_OFFSET)
#define SAM_PIOD_OSR (SAM_PIOD_VBASE+SAM_PIO_OSR_OFFSET)
#define SAM_PIOD_IFER (SAM_PIOD_VBASE+SAM_PIO_IFER_OFFSET)
#define SAM_PIOD_IFDR (SAM_PIOD_VBASE+SAM_PIO_IFDR_OFFSET)
#define SAM_PIOD_IFSR (SAM_PIOD_VBASE+SAM_PIO_IFSR_OFFSET)
#define SAM_PIOD_SODR (SAM_PIOD_VBASE+SAM_PIO_SODR_OFFSET)
#define SAM_PIOD_CODR (SAM_PIOD_VBASE+SAM_PIO_CODR_OFFSET)
#define SAM_PIOD_ODSR (SAM_PIOD_VBASE+SAM_PIO_ODSR_OFFSET)
#define SAM_PIOD_PDSR (SAM_PIOD_VBASE+SAM_PIO_PDSR_OFFSET)
#define SAM_PIOD_IER (SAM_PIOD_VBASE+SAM_PIO_IER_OFFSET)
#define SAM_PIOD_IDR (SAM_PIOD_VBASE+SAM_PIO_IDR_OFFSET)
#define SAM_PIOD_IMR (SAM_PIOD_VBASE+SAM_PIO_IMR_OFFSET)
#define SAM_PIOD_ISR (SAM_PIOD_VBASE+SAM_PIO_ISR_OFFSET)
#define SAM_PIOD_MDER (SAM_PIOD_VBASE+SAM_PIO_MDER_OFFSET)
#define SAM_PIOD_MDDR (SAM_PIOD_VBASE+SAM_PIO_MDDR_OFFSET)
#define SAM_PIOD_MDSR (SAM_PIOD_VBASE+SAM_PIO_MDSR_OFFSET)
#define SAM_PIOD_PUDR (SAM_PIOD_VBASE+SAM_PIO_PUDR_OFFSET)
#define SAM_PIOD_PUER (SAM_PIOD_VBASE+SAM_PIO_PUER_OFFSET)
#define SAM_PIOD_PUSR (SAM_PIOD_VBASE+SAM_PIO_PUSR_OFFSET)
#define SAM_PIOD_ABCDSR1 (SAM_PIOD_VBASE+SAM_PIO_ABCDSR1_OFFSET)
#define SAM_PIOD_ABCDSR2 (SAM_PIOD_VBASE+SAM_PIO_ABCDSR2_OFFSET)
#define SAM_PIOD_IFSCDR (SAM_PIOD_VBASE+SAM_PIO_IFSCDR_OFFSET)
#define SAM_PIOD_IFSCER (SAM_PIOD_VBASE+SAM_PIO_IFSCER_OFFSET)
#define SAM_PIOD_IFSCSR (SAM_PIOD_VBASE+SAM_PIO_IFSCSR_OFFSET)
#define SAM_PIOD_SCDR (SAM_PIOD_VBASE+SAM_PIO_SCDR_OFFSET)
#define SAM_PIOD_PPDDR (SAM_PIOD_VBASE+SAM_PIO_PPDDR_OFFSET)
#define SAM_PIOD_PPDER (SAM_PIOD_VBASE+SAM_PIO_PPDER_OFFSET)
#define SAM_PIOD_PPDSR (SAM_PIOD_VBASE+SAM_PIO_PPDSR_OFFSET)
#define SAM_PIOD_OWER (SAM_PIOD_VBASE+SAM_PIO_OWER_OFFSET)
#define SAM_PIOD_OWDR (SAM_PIOD_VBASE+SAM_PIO_OWDR_OFFSET)
#define SAM_PIOD_OWSR (SAM_PIOD_VBASE+SAM_PIO_OWSR_OFFSET)
#define SAM_PIOD_AIMER (SAM_PIOD_VBASE+SAM_PIO_AIMER_OFFSET)
#define SAM_PIOD_AIMDR (SAM_PIOD_VBASE+SAM_PIO_AIMDR_OFFSET)
#define SAM_PIOD_AIMMR (SAM_PIOD_VBASE+SAM_PIO_AIMMR_OFFSET)
#define SAM_PIOD_ESR (SAM_PIOD_VBASE+SAM_PIO_ESR_OFFSET)
#define SAM_PIOD_LSR (SAM_PIOD_VBASE+SAM_PIO_LSR_OFFSET)
#define SAM_PIOD_ELSR (SAM_PIOD_VBASE+SAM_PIO_ELSR_OFFSET)
#define SAM_PIOD_FELLSR (SAM_PIOD_VBASE+SAM_PIO_FELLSR_OFFSET)
#define SAM_PIOD_REHLSR (SAM_PIOD_VBASE+SAM_PIO_REHLSR_OFFSET)
#define SAM_PIOD_FRLHSR (SAM_PIOD_VBASE+SAM_PIO_FRLHSR_OFFSET)
#define SAM_PIOD_LOCKSR (SAM_PIOD_VBASE+SAM_PIO_LOCKSR_OFFSET)
#define SAM_PIOD_WPMR (SAM_PIOD_VBASE+SAM_PIO_WPMR_OFFSET)
#define SAM_PIOD_WPSR (SAM_PIOD_VBASE+SAM_PIO_WPSR_OFFSET)
#define SAM_PIOD_SCHMITT (SAM_PIOD_VBASE+SAM_PIO_SCHMITT_OFFSET)
#define SAM_PIOD_DRIVER1 (SAM_PIOD_VBASE+SAM_PIO_DRIVER1_OFFSET)
#define SAM_PIOD_DRIVER2 (SAM_PIOD_VBASE+SAM_PIO_DRIVER2_OFFSET)
#define SAM_PIOE_PER (SAM_PIOE_VBASE+SAM_PIO_PER_OFFSET)
#define SAM_PIOE_PDR (SAM_PIOE_VBASE+SAM_PIO_PDR_OFFSET)
#define SAM_PIOE_PSR (SAM_PIOE_VBASE+SAM_PIO_PSR_OFFSET)
#define SAM_PIOE_OER (SAM_PIOE_VBASE+SAM_PIO_OER_OFFSET)
#define SAM_PIOE_ODR (SAM_PIOE_VBASE+SAM_PIO_ODR_OFFSET)
#define SAM_PIOE_OSR (SAM_PIOE_VBASE+SAM_PIO_OSR_OFFSET)
#define SAM_PIOE_IFER (SAM_PIOE_VBASE+SAM_PIO_IFER_OFFSET)
#define SAM_PIOE_IFDR (SAM_PIOE_VBASE+SAM_PIO_IFDR_OFFSET)
#define SAM_PIOE_IFSR (SAM_PIOE_VBASE+SAM_PIO_IFSR_OFFSET)
#define SAM_PIOE_SODR (SAM_PIOE_VBASE+SAM_PIO_SODR_OFFSET)
#define SAM_PIOE_CODR (SAM_PIOE_VBASE+SAM_PIO_CODR_OFFSET)
#define SAM_PIOE_ODSR (SAM_PIOE_VBASE+SAM_PIO_ODSR_OFFSET)
#define SAM_PIOE_PDSR (SAM_PIOE_VBASE+SAM_PIO_PDSR_OFFSET)
#define SAM_PIOE_IER (SAM_PIOE_VBASE+SAM_PIO_IER_OFFSET)
#define SAM_PIOE_IDR (SAM_PIOE_VBASE+SAM_PIO_IDR_OFFSET)
#define SAM_PIOE_IMR (SAM_PIOE_VBASE+SAM_PIO_IMR_OFFSET)
#define SAM_PIOE_ISR (SAM_PIOE_VBASE+SAM_PIO_ISR_OFFSET)
#define SAM_PIOE_MDER (SAM_PIOE_VBASE+SAM_PIO_MDER_OFFSET)
#define SAM_PIOE_MDDR (SAM_PIOE_VBASE+SAM_PIO_MDDR_OFFSET)
#define SAM_PIOE_MDSR (SAM_PIOE_VBASE+SAM_PIO_MDSR_OFFSET)
#define SAM_PIOE_PUDR (SAM_PIOE_VBASE+SAM_PIO_PUDR_OFFSET)
#define SAM_PIOE_PUER (SAM_PIOE_VBASE+SAM_PIO_PUER_OFFSET)
#define SAM_PIOE_PUSR (SAM_PIOE_VBASE+SAM_PIO_PUSR_OFFSET)
#define SAM_PIOE_ABCDSR1 (SAM_PIOE_VBASE+SAM_PIO_ABCDSR1_OFFSET)
#define SAM_PIOE_ABCDSR2 (SAM_PIOE_VBASE+SAM_PIO_ABCDSR2_OFFSET)
#define SAM_PIOE_IFSCDR (SAM_PIOE_VBASE+SAM_PIO_IFSCDR_OFFSET)
#define SAM_PIOE_IFSCER (SAM_PIOE_VBASE+SAM_PIO_IFSCER_OFFSET)
#define SAM_PIOE_IFSCSR (SAM_PIOE_VBASE+SAM_PIO_IFSCSR_OFFSET)
#define SAM_PIOE_SCDR (SAM_PIOE_VBASE+SAM_PIO_SCDR_OFFSET)
#define SAM_PIOE_PPDDR (SAM_PIOE_VBASE+SAM_PIO_PPDDR_OFFSET)
#define SAM_PIOE_PPDER (SAM_PIOE_VBASE+SAM_PIO_PPDER_OFFSET)
#define SAM_PIOE_PPDSR (SAM_PIOE_VBASE+SAM_PIO_PPDSR_OFFSET)
#define SAM_PIOE_OWER (SAM_PIOE_VBASE+SAM_PIO_OWER_OFFSET)
#define SAM_PIOE_OWDR (SAM_PIOE_VBASE+SAM_PIO_OWDR_OFFSET)
#define SAM_PIOE_OWSR (SAM_PIOE_VBASE+SAM_PIO_OWSR_OFFSET)
#define SAM_PIOE_AIMER (SAM_PIOE_VBASE+SAM_PIO_AIMER_OFFSET)
#define SAM_PIOE_AIMDR (SAM_PIOE_VBASE+SAM_PIO_AIMDR_OFFSET)
#define SAM_PIOE_AIMMR (SAM_PIOE_VBASE+SAM_PIO_AIMMR_OFFSET)
#define SAM_PIOE_ESR (SAM_PIOE_VBASE+SAM_PIO_ESR_OFFSET)
#define SAM_PIOE_LSR (SAM_PIOE_VBASE+SAM_PIO_LSR_OFFSET)
#define SAM_PIOE_ELSR (SAM_PIOE_VBASE+SAM_PIO_ELSR_OFFSET)
#define SAM_PIOE_FELLSR (SAM_PIOE_VBASE+SAM_PIO_FELLSR_OFFSET)
#define SAM_PIOE_REHLSR (SAM_PIOE_VBASE+SAM_PIO_REHLSR_OFFSET)
#define SAM_PIOE_FRLHSR (SAM_PIOE_VBASE+SAM_PIO_FRLHSR_OFFSET)
#define SAM_PIOE_LOCKSR (SAM_PIOE_VBASE+SAM_PIO_LOCKSR_OFFSET)
#define SAM_PIOE_WPMR (SAM_PIOE_VBASE+SAM_PIO_WPMR_OFFSET)
#define SAM_PIOE_WPSR (SAM_PIOE_VBASE+SAM_PIO_WPSR_OFFSET)
#define SAM_PIOE_SCHMITT (SAM_PIOE_VBASE+SAM_PIO_SCHMITT_OFFSET)
#define SAM_PIOE_DRIVER1 (SAM_PIOE_VBASE+SAM_PIO_DRIVER1_OFFSET)
#define SAM_PIOE_DRIVER2 (SAM_PIOE_VBASE+SAM_PIO_DRIVER2_OFFSET)
/* PIO register bit definitions *********************************************************/
/* Common bit definitions for ALMOST all IO registers (exceptions follow) */
#define PIO(n) (1 << (n)) /* Bit n: PIO n */
/* PIO Slow Clock Divider Debouncing Register */
#define PIO_SCDR_MASK (0x3fff) /* Bit 0-13: Slow Clock Divider Selection for Debouncing */
/* PIO Write Protect Mode Register */
#define PIO_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
#define PIO_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
#define PIO_WPMR_WPKEY_MASK (0xffffff << PIO_WPMR_WPKEY_SHIFT)
# define PIO_WPMR_WPKEY (0x50494f << PIO_WPMR_WPKEY_SHIFT)
/* PIO Write Protect Status Register */
#define PIO_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */
#define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define PIO_WPSR_WPVSRC_MASK (0xffff << PIO_WPSR_WPVSRC_SHIFT)
/* I/O Drive Register 1 */
#define PIO_LO_DRIVE (0) /* Low drive */
#define PIO_ME_DRIVE (2) /* Medium drive */
#define PIO_HI_DRIVE (3) /* High drive */
#define PIO_DRIVER1_LINE_SHIFT(n) ((n) << 1)
#define PIO_DRIVER1_LINE_MASK(n) (3 << PIO_DRIVER1_LINE_SHIFT(n))
# define PIO_DRIVER1_LINE(n,d) ((d) << PIO_DRIVER1_LINE_SHIFT(n))
#define PIO_DRIVER1_LINE0_SHIFT (0) /* Bit 0-1: Line 0 drive */
#define PIO_DRIVER1_LINE0_MASK (3 <<PIO_DRIVER1_LINE0_SHIFT)
# define PIO_DRIVER1_LINE0(d) ((d) << PIO_DRIVER1_LINE0_SHIFT)
#define PIO_DRIVER1_LINE1_SHIFT (0) /* Bit 0-1: Line 1 drive */
#define PIO_DRIVER1_LINE1_MASK (3 <<PIO_DRIVER1_LINE1_SHIFT)
# define PIO_DRIVER1_LINE1(d) ((d) << PIO_DRIVER1_LINE1_SHIFT)
#define PIO_DRIVER1_LINE2_SHIFT (0) /* Bit 0-1: Line 2 drive */
#define PIO_DRIVER1_LINE2_MASK (3 <<PIO_DRIVER1_LINE2_SHIFT)
# define PIO_DRIVER1_LINE2(d) ((d) << PIO_DRIVER1_LINE2_SHIFT)
#define PIO_DRIVER1_LINE3_SHIFT (0) /* Bit 0-1: Line 3 drive */
#define PIO_DRIVER1_LINE3_MASK (3 <<PIO_DRIVER1_LINE3_SHIFT)
# define PIO_DRIVER1_LINE3(d) ((d) << PIO_DRIVER1_LINE3_SHIFT)
#define PIO_DRIVER1_LINE4_SHIFT (0) /* Bit 0-1: Line 4 drive */
#define PIO_DRIVER1_LINE4_MASK (3 <<PIO_DRIVER1_LINE4_SHIFT)
# define PIO_DRIVER1_LINE4(d) ((d) << PIO_DRIVER1_LINE4_SHIFT)
#define PIO_DRIVER1_LINE5_SHIFT (0) /* Bit 0-1: Line 5 drive */
#define PIO_DRIVER1_LINE5_MASK (3 <<PIO_DRIVER1_LINE5_SHIFT)
# define PIO_DRIVER1_LINE5(d) ((d) << PIO_DRIVER1_LINE5_SHIFT)
#define PIO_DRIVER1_LINE6_SHIFT (0) /* Bit 0-1: Line 6 drive */
#define PIO_DRIVER1_LINE6_MASK (3 <<PIO_DRIVER1_LINE6_SHIFT)
# define PIO_DRIVER1_LINE6(d) ((d) << PIO_DRIVER1_LINE6_SHIFT)
#define PIO_DRIVER1_LINE7_SHIFT (0) /* Bit 0-1: Line 7 drive */
#define PIO_DRIVER1_LINE7_MASK (3 <<PIO_DRIVER1_LINE7_SHIFT)
# define PIO_DRIVER1_LINE7(d) ((d) << PIO_DRIVER1_LINE7_SHIFT)
#define PIO_DRIVER1_LINE8_SHIFT (0) /* Bit 0-1: Line 8 drive */
#define PIO_DRIVER1_LINE8_MASK (3 <<PIO_DRIVER1_LINE8_SHIFT)
# define PIO_DRIVER1_LINE8(d) ((d) << PIO_DRIVER1_LINE8_SHIFT)
#define PIO_DRIVER1_LINE9_SHIFT (0) /* Bit 0-1: Line 9 drive */
#define PIO_DRIVER1_LINE9_MASK (3 <<PIO_DRIVER1_LINE9_SHIFT)
# define PIO_DRIVER1_LINE9(d) ((d) << PIO_DRIVER1_LINE9_SHIFT)
#define PIO_DRIVER1_LINE10_SHIFT (0) /* Bit 0-1: Line 10 drive */
#define PIO_DRIVER1_LINE10_MASK (3 <<PIO_DRIVER1_LINE10_SHIFT)
# define PIO_DRIVER1_LINE10(d) ((d) << PIO_DRIVER1_LINE10_SHIFT)
#define PIO_DRIVER1_LINE11_SHIFT (0) /* Bit 0-1: Line 11 drive */
#define PIO_DRIVER1_LINE11_MASK (3 <<PIO_DRIVER1_LINE11_SHIFT)
# define PIO_DRIVER1_LINE11(d) ((d) << PIO_DRIVER1_LINE11_SHIFT)
#define PIO_DRIVER1_LINE12_SHIFT (0) /* Bit 0-1: Line 12 drive */
#define PIO_DRIVER1_LINE12_MASK (3 <<PIO_DRIVER1_LINE12_SHIFT)
# define PIO_DRIVER1_LINE12(d) ((d) << PIO_DRIVER1_LINE12_SHIFT)
#define PIO_DRIVER1_LINE13_SHIFT (0) /* Bit 0-1: Line 13 drive */
#define PIO_DRIVER1_LINE13_MASK (3 <<PIO_DRIVER1_LINE13_SHIFT)
# define PIO_DRIVER1_LINE13(d) ((d) << PIO_DRIVER1_LINE13_SHIFT)
#define PIO_DRIVER1_LINE14_SHIFT (0) /* Bit 0-1: Line 14 drive */
#define PIO_DRIVER1_LINE14_MASK (3 <<PIO_DRIVER1_LINE14_SHIFT)
# define PIO_DRIVER1_LINE14(d) ((d) << PIO_DRIVER1_LINE14_SHIFT)
#define PIO_DRIVER1_LINE15_SHIFT (0) /* Bit 0-1: Line 15 drive */
#define PIO_DRIVER1_LINE15_MASK (3 <<PIO_DRIVER1_LINE15_SHIFT)
# define PIO_DRIVER1_LINE15(d) ((d) << PIO_DRIVER1_LINE15_SHIFT)
/* I/O Drive Register 2 */
#define PIO_DRIVER2_
#define PIO_DRIVER2_LINE_SHIFT(n) (((n)-32) << 1)
#define PIO_DRIVER2_LINE_MASK(n) (3 << PIO_DRIVER2_LINE_SHIFT(n))
# define PIO_DRIVER2_LINE(n,d) ((d) << PIO_DRIVER2_LINE_SHIFT(n))
#define PIO_DRIVER2_LINE16_SHIFT (0) /* Bit 0-1: Line 16 drive */
#define PIO_DRIVER2_LINE16_MASK (3 <<PIO_DRIVER2_LINE16_SHIFT)
# define PIO_DRIVER2_LINE16(d) ((d) << PIO_DRIVER2_LINE16_SHIFT)
#define PIO_DRIVER2_LINE17_SHIFT (0) /* Bit 0-1: Line 17 drive */
#define PIO_DRIVER2_LINE17_MASK (3 <<PIO_DRIVER2_LINE17_SHIFT)
# define PIO_DRIVER2_LINE17(d) ((d) << PIO_DRIVER2_LINE17_SHIFT)
#define PIO_DRIVER2_LINE18_SHIFT (0) /* Bit 0-1: Line 18 drive */
#define PIO_DRIVER2_LINE18_MASK (3 <<PIO_DRIVER2_LINE18_SHIFT)
# define PIO_DRIVER2_LINE18(d) ((d) << PIO_DRIVER2_LINE18_SHIFT)
#define PIO_DRIVER2_LINE19_SHIFT (0) /* Bit 0-1: Line 19 drive */
#define PIO_DRIVER2_LINE19_MASK (3 <<PIO_DRIVER2_LINE19_SHIFT)
# define PIO_DRIVER2_LINE19(d) ((d) << PIO_DRIVER2_LINE19_SHIFT)
#define PIO_DRIVER2_LINE20_SHIFT (0) /* Bit 0-1: Line 20 drive */
#define PIO_DRIVER2_LINE20_MASK (3 <<PIO_DRIVER2_LINE20_SHIFT)
# define PIO_DRIVER2_LINE20(d) ((d) << PIO_DRIVER2_LINE20_SHIFT)
#define PIO_DRIVER2_LINE21_SHIFT (0) /* Bit 0-1: Line 21 drive */
#define PIO_DRIVER2_LINE21_MASK (3 <<PIO_DRIVER2_LINE21_SHIFT)
# define PIO_DRIVER2_LINE21(d) ((d) << PIO_DRIVER2_LINE21_SHIFT)
#define PIO_DRIVER2_LINE22_SHIFT (0) /* Bit 0-1: Line 22 drive */
#define PIO_DRIVER2_LINE22_MASK (3 <<PIO_DRIVER2_LINE22_SHIFT)
# define PIO_DRIVER2_LINE22(d) ((d) << PIO_DRIVER2_LINE22_SHIFT)
#define PIO_DRIVER2_LINE23_SHIFT (0) /* Bit 0-1: Line 23 drive */
#define PIO_DRIVER2_LINE23_MASK (3 <<PIO_DRIVER2_LINE23_SHIFT)
# define PIO_DRIVER2_LINE23(d) ((d) << PIO_DRIVER2_LINE23_SHIFT)
#define PIO_DRIVER2_LINE24_SHIFT (0) /* Bit 0-1: Line 24 drive */
#define PIO_DRIVER2_LINE24_MASK (3 <<PIO_DRIVER2_LINE24_SHIFT)
# define PIO_DRIVER2_LINE24(d) ((d) << PIO_DRIVER2_LINE24_SHIFT)
#define PIO_DRIVER2_LINE25_SHIFT (0) /* Bit 0-1: Line 25 drive */
#define PIO_DRIVER2_LINE25_MASK (3 <<PIO_DRIVER2_LINE25_SHIFT)
# define PIO_DRIVER2_LINE25(d) ((d) << PIO_DRIVER2_LINE25_SHIFT)
#define PIO_DRIVER2_LINE26_SHIFT (0) /* Bit 0-1: Line 26 drive */
#define PIO_DRIVER2_LINE26_MASK (3 <<PIO_DRIVER2_LINE26_SHIFT)
# define PIO_DRIVER2_LINE26(d) ((d) << PIO_DRIVER2_LINE26_SHIFT)
#define PIO_DRIVER2_LINE27_SHIFT (0) /* Bit 0-1: Line 27 drive */
#define PIO_DRIVER2_LINE27_MASK (3 <<PIO_DRIVER2_LINE27_SHIFT)
# define PIO_DRIVER2_LINE27(d) ((d) << PIO_DRIVER2_LINE27_SHIFT)
#define PIO_DRIVER2_LINE28_SHIFT (0) /* Bit 0-1: Line 28 drive */
#define PIO_DRIVER2_LINE28_MASK (3 <<PIO_DRIVER2_LINE28_SHIFT)
# define PIO_DRIVER2_LINE28(d) ((d) << PIO_DRIVER2_LINE28_SHIFT)
#define PIO_DRIVER2_LINE29_SHIFT (0) /* Bit 0-1: Line 29 drive */
#define PIO_DRIVER2_LINE29_MASK (3 <<PIO_DRIVER2_LINE29_SHIFT)
# define PIO_DRIVER2_LINE29(d) ((d) << PIO_DRIVER2_LINE29_SHIFT)
#define PIO_DRIVER2_LINE30_SHIFT (0) /* Bit 0-1: Line 30 drive */
#define PIO_DRIVER2_LINE30_MASK (3 <<PIO_DRIVER2_LINE30_SHIFT)
# define PIO_DRIVER2_LINE30(d) ((d) << PIO_DRIVER2_LINE30_SHIFT)
#define PIO_DRIVER2_LINE31_SHIFT (0) /* Bit 0-1: Line 31 drive */
#define PIO_DRIVER2_LINE31_MASK (3 <<PIO_DRIVER2_LINE31_SHIFT)
# define PIO_DRIVER2_LINE31(d) ((d) << PIO_DRIVER2_LINE31_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PIO_H */

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arch/arm/src/sama5/chip/sama5d3x_memorymap.h
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@ -65,102 +65,103 @@
/* SAMA5 Physical (unmapped) Memory Map */
#define SAM_INTMEM_PSECTION 0x00000000 /* 0x00000000-0x0fffffff: Internal Memories */
#define SAM_EBICS0_PSECTION 0x10000000 /* 0x10000000-0x1fffffff: EBI Chip select 0 */
#define SAM_DDRCS_PSECTION 0x20000000 /* 0x20000000-0x3fffffff: EBI DDRCS */
#define SAM_EBICS1_PSECTION 0x40000000 /* 0x40000000-0x4fffffff: EBI Chip select 1 */
#define SAM_EBICS2_PSECTION 0x50000000 /* 0x50000000-0x5fffffff: EBI Chip select 2 */
#define SAM_EBICS3_PSECTION 0x60000000 /* 0x60000000-0x6fffffff: EBI Chip select 2 */
#define SAM_NFCCR_PSECTION 0x70000000 /* 0x70000000-0x7fffffff: NFC Command Registers */
/* 0x80000000-0xefffffff: Undefined */
#define SAM_PERIPH_PSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
#define SAM_INTMEM_PSECTION 0x00000000 /* 0x00000000-0x0fffffff: Internal Memories */
#define SAM_EBICS0_PSECTION 0x10000000 /* 0x10000000-0x1fffffff: EBI Chip select 0 */
#define SAM_DDRCS_PSECTION 0x20000000 /* 0x20000000-0x3fffffff: EBI DDRCS */
#define SAM_EBICS1_PSECTION 0x40000000 /* 0x40000000-0x4fffffff: EBI Chip select 1 */
#define SAM_EBICS2_PSECTION 0x50000000 /* 0x50000000-0x5fffffff: EBI Chip select 2 */
#define SAM_EBICS3_PSECTION 0x60000000 /* 0x60000000-0x6fffffff: EBI Chip select 2 */
#define SAM_NFCCR_PSECTION 0x70000000 /* 0x70000000-0x7fffffff: NFC Command Registers */
/* 0x80000000-0xefffffff: Undefined */
#define SAM_PERIPH_PSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
/* SAMA5 Internal Memories */
#define SAM_BOOTMEM_PSECTION 0x00000000 /* 0x00000000-0x000fffff: Boot memory */
#define SAM_ROM_PSECTION 0x00100000 /* 0x00100000-0x001fffff: ROM */
#define SAM_NFCSRAM_PSECTION 0x00200000 /* 0x00200000-0x002fffff: NFC SRAM */
#define SAM_ISRAM_PSECTION 0x00300000 /* 0x00300000-0x0030ffff: SRAM */
# define SAM_ISRAM0_PADDR 0x00300000 /* 0x00300000-0x0030ffff: SRAM0 */
# define SAM_ISRAM1_PADDR 0x00310000 /* 0x00310000-0x003fffff: SRAM1 */
#define SAM_SMD_PSECTION 0x00400000 /* 0x00400000-0x004fffff: SMD */
#define SAM_UDPHSRAM_PSECTION 0x00500000 /* 0x00500000-0x005fffff: UDPH SRAM */
#define SAM_UHPOHCI_PSECTION 0x00600000 /* 0x00600000-0x006fffff: UHP OHCI */
#define SAM_UHPEHCI_PSECTION 0x00700000 /* 0x00700000-0x007fffff: UHP EHCI */
#define SAM_AXIMATRIX_PSECTION 0x00800000 /* 0x00800000-0x008fffff: AXI Matr */
#define SAM_DAP_PSECTION 0x00900000 /* 0x00900000-0x009fffff: DAP */
/* 0x000a0000-0x0fffffff: Undefined */
#define SAM_BOOTMEM_PSECTION 0x00000000 /* 0x00000000-0x000fffff: Boot memory */
#define SAM_ROM_PSECTION 0x00100000 /* 0x00100000-0x001fffff: ROM */
#define SAM_NFCSRAM_PSECTION 0x00200000 /* 0x00200000-0x002fffff: NFC SRAM */
#define SAM_ISRAM_PSECTION 0x00300000 /* 0x00300000-0x0030ffff: SRAM */
# define SAM_ISRAM0_PADDR 0x00300000 /* 0x00300000-0x0030ffff: SRAM0 */
# define SAM_ISRAM1_PADDR 0x00310000 /* 0x00310000-0x003fffff: SRAM1 */
#define SAM_SMD_PSECTION 0x00400000 /* 0x00400000-0x004fffff: SMD */
#define SAM_UDPHSRAM_PSECTION 0x00500000 /* 0x00500000-0x005fffff: UDPH SRAM */
#define SAM_UHPOHCI_PSECTION 0x00600000 /* 0x00600000-0x006fffff: UHP OHCI */
#define SAM_UHPEHCI_PSECTION 0x00700000 /* 0x00700000-0x007fffff: UHP EHCI */
#define SAM_AXIMATRIX_PSECTION 0x00800000 /* 0x00800000-0x008fffff: AXI Matr */
#define SAM_DAP_PSECTION 0x00900000 /* 0x00900000-0x009fffff: DAP */
/* 0x000a0000-0x0fffffff: Undefined */
/* SAMA5 Internal Peripheral Offsets */
#define SAM_PERIPHA_PSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
# define SAM_HSMCI0_OFFSET 0x00000000 /* 0x00000000-0x00003fff: HSMCI0 */
# define SAM_SPI0_OFFSET 0x00004000 /* 0x00004000-0x00007fff: SPI0 */
# define SAM_SSC0_OFFSET 0x00008000 /* 0x00008000-0x0000bfff: SSC0 */
# define SAM_CAN0_OFFSET 0x0000c000 /* 0x0000c000-0x0000ffff: CAN0 */
# define SAM_TC012_OFFSET 0x00010000 /* 0x00010000-0x00013fff: TC0, TC1, TC2 */
# define SAM_TWI0_OFFSET 0x00014000 /* 0x00014000-0x00017fff: TWI0 */
# define SAM_TWI1_OFFSET 0x00018000 /* 0x00018000-0x0001bfff: TWI1 */
# define SAM_USART0_OFFSET 0x0001c000 /* 0x0001c000-0x0001ffff: USART0 */
# define SAM_USART1_OFFSET 0x00020000 /* 0x00020000-0x00023fff: USART1 */
# define SAM_UART0_OFFSET 0x00024000 /* 0x00024000-0x00027fff: UART0 */
# define SAM_GMAC_OFFSET 0x00028000 /* 0x00028000-0x0002bfff: GMAC */
# define SAM_PWMC_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: PWMC */
# define SAM_LCDC_OFFSET 0x00030000 /* 0x00030000-0x00033fff: LCDC */
# define SAM_ISI_OFFSET 0x00034000 /* 0x00034000-0x00037fff: ISI */
# define SAM_SFR_OFFSET 0x00038000 /* 0x00038000-0x0003bfff: SFR */
/* 0x0003c000-0x07ffffff: Reserved */
#define SAM_PERIPHA_PSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
# define SAM_HSMCI0_OFFSET 0x00000000 /* 0x00000000-0x00003fff: HSMCI0 */
# define SAM_SPI0_OFFSET 0x00004000 /* 0x00004000-0x00007fff: SPI0 */
# define SAM_SSC0_OFFSET 0x00008000 /* 0x00008000-0x0000bfff: SSC0 */
# define SAM_CAN0_OFFSET 0x0000c000 /* 0x0000c000-0x0000ffff: CAN0 */
# define SAM_TC012_OFFSET 0x00010000 /* 0x00010000-0x00013fff: TC0, TC1, TC2 */
# define SAM_TWI0_OFFSET 0x00014000 /* 0x00014000-0x00017fff: TWI0 */
# define SAM_TWI1_OFFSET 0x00018000 /* 0x00018000-0x0001bfff: TWI1 */
# define SAM_USART0_OFFSET 0x0001c000 /* 0x0001c000-0x0001ffff: USART0 */
# define SAM_USART1_OFFSET 0x00020000 /* 0x00020000-0x00023fff: USART1 */
# define SAM_UART0_OFFSET 0x00024000 /* 0x00024000-0x00027fff: UART0 */
# define SAM_GMAC_OFFSET 0x00028000 /* 0x00028000-0x0002bfff: GMAC */
# define SAM_PWMC_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: PWMC */
# define SAM_LCDC_OFFSET 0x00030000 /* 0x00030000-0x00033fff: LCDC */
# define SAM_ISI_OFFSET 0x00034000 /* 0x00034000-0x00037fff: ISI */
# define SAM_SFR_OFFSET 0x00038000 /* 0x00038000-0x0003bfff: SFR */
/* 0x0003c000-0x07ffffff: Reserved */
#define SAM_PERIPHB_PSECTION 0xf8000000 /* 0xf8000000-0xffffbfff: Internal Peripherals B */
# define SAM_HSMCI1_OFFSET 0x00000000 /* 0x00000000-0x00000fff: HSMCI1 */
# define SAM_HSMCI2_OFFSET 0x00004000 /* 0x00004000-0x00007fff: HSMCI2 */
# define SAM_SPI1_OFFSET 0x00008000 /* 0x00008000-0x0000bfff: SPI1 */
# define SAM_SSC1_OFFSET 0x0000c000 /* 0x0000c000-0x0000ffff: SSC1 */
# define SAM_CAN1_OFFSET 0x00010000 /* 0x00010000-0x00013fff: CAN1 */
# define SAM_TC345_OFFSET 0x00014000 /* 0x00014000-0x00017fff: TC3, TC4, TC5 */
# define SAM_TSADC_OFFSET 0x00018000 /* 0x00018000-0x0001bfff: TSADC */
# define SAM_TWI2_OFFSET 0x0001c000 /* 0x0001c000-0x0001ffff: TWI2 */
# define SAM_USART2_OFFSET 0x00020000 /* 0x00020000-0x00023fff: USART2 */
# define SAM_USART3_OFFSET 0x00024000 /* 0x00024000-0x00027fff: USART3 */
# define SAM_UART1_OFFSET 0x00028000 /* 0x00028000-0x0002bfff: UART1 */
# define SAM_EMAC_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: EMAC */
# define SAM_UDPHS_OFFSET 0x00030000 /* 0x00030000-0x00033fff: UDPHS */
# define SAM_SHA_OFFSET 0x00034000 /* 0x00034000-0x00037fff: SHA */
# define SAM_AES_OFFSET 0x00038000 /* 0x00038000-0x0003bfff: AES */
# define SAM_TDES_OFFSET 0x0003c000 /* 0x0003c000-0x0003ffff: TDES */
# define SAM_TRNG_OFFSET 0x00040000 /* 0x00040000-0x00043fff: TRNG */
/* 0x00044000-0x00ffbfff: Reserved */
#define SAM_SYSC_PSECTION 0xff000000 /* 0xff000000-0xffffffff: System Controller */
#define SAM_SYSC_PADDR 0xffffc000 /* 0xffffc000-0xffffffff: System Controller */
# define SAM_SYSC_OFFSET 0x00000000 /* 0x0fffc000-0x0fffffff: System Controller */
#define SAM_PERIPHB_PSECTION 0xf8000000 /* 0xf8000000-0xffffbfff: Internal Peripherals B */
# define SAM_HSMCI1_OFFSET 0x00000000 /* 0x00000000-0x00000fff: HSMCI1 */
# define SAM_HSMCI2_OFFSET 0x00004000 /* 0x00004000-0x00007fff: HSMCI2 */
# define SAM_SPI1_OFFSET 0x00008000 /* 0x00008000-0x0000bfff: SPI1 */
# define SAM_SSC1_OFFSET 0x0000c000 /* 0x0000c000-0x0000ffff: SSC1 */
# define SAM_CAN1_OFFSET 0x00010000 /* 0x00010000-0x00013fff: CAN1 */
# define SAM_TC345_OFFSET 0x00014000 /* 0x00014000-0x00017fff: TC3, TC4, TC5 */
# define SAM_TSADC_OFFSET 0x00018000 /* 0x00018000-0x0001bfff: TSADC */
# define SAM_TWI2_OFFSET 0x0001c000 /* 0x0001c000-0x0001ffff: TWI2 */
# define SAM_USART2_OFFSET 0x00020000 /* 0x00020000-0x00023fff: USART2 */
# define SAM_USART3_OFFSET 0x00024000 /* 0x00024000-0x00027fff: USART3 */
# define SAM_UART1_OFFSET 0x00028000 /* 0x00028000-0x0002bfff: UART1 */
# define SAM_EMAC_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: EMAC */
# define SAM_UDPHS_OFFSET 0x00030000 /* 0x00030000-0x00033fff: UDPHS */
# define SAM_SHA_OFFSET 0x00034000 /* 0x00034000-0x00037fff: SHA */
# define SAM_AES_OFFSET 0x00038000 /* 0x00038000-0x0003bfff: AES */
# define SAM_TDES_OFFSET 0x0003c000 /* 0x0003c000-0x0003ffff: TDES */
# define SAM_TRNG_OFFSET 0x00040000 /* 0x00040000-0x00043fff: TRNG */
/* 0x00044000-0x00ffbfff: Reserved */
#define SAM_SYSC_PSECTION 0xff000000 /* 0xff000000-0xffffffff: System Controller */
#define SAM_SYSC_PADDR 0xffffc000 /* 0xffffc000-0xffffffff: System Controller */
# define SAM_SYSC_OFFSET 0x00000000 /* 0x0fffc000-0x0fffffff: System Controller */
/* System Controller Peripheral Offsets */
#define SAM_HSMC_OFFSET 0x00ffc000 /* 0x0fffc000-0x0fffcfff: HSMC */
/* 0x0fffd000-0x0fffe3ff: Reserved */
#define SAM_FUSE_OFFSET 0x00ffe400 /* 0x0fffe400-0x0fffe5ff: FUSE */
#define SAM_DMAC0_OFFSET 0x00ffe600 /* 0x0fffe600-0x0fffe7ff: DMAC0 */
#define SAM_DMAC1_OFFSET 0x00ffe800 /* 0x0fffe800-0x0fffe9ff: DMAC1 */
#define SAM_MPDDRC_OFFSET 0x00ffea00 /* 0x0fffea00-0x0fffebff: MPDDRC */
#define SAM_MATRIX_OFFSET 0x00ffec00 /* 0x0fffec00-0x0fffedff: MATRIX */
#define SAM_DBGU_OFFSET 0x00ffee00 /* 0x0fffee00-0x0fffefff: DBGU */
#define SAM_AIC_OFFSET 0x00fff000 /* 0x0ffff000-0x0ffff1ff: AIC */
#define SAM_PIOA_OFFSET 0x00fff200 /* 0x0ffff200-0x0ffff3ff: PIOA */
#define SAM_PIOB_OFFSET 0x00fff400 /* 0x0ffff400-0x0ffff5ff: PIOB */
#define SAM_PIOC_OFFSET 0x00fff600 /* 0x0ffff600-0x0ffff7ff: PIOC */
#define SAM_PIOD_OFFSET 0x00fff800 /* 0x0ffff800-0x0ffff9ff: PIOD */
#define SAM_PIOE_OFFSET 0x00fffa00 /* 0x0ffffa00-0x0ffffbff: PIOE */
#define SAM_PMC_OFFSET 0x00fffc00 /* 0x0ffffc00-0x0ffffdff: PMC */
#define SAM_RSTC_OFFSET 0x00fffe00 /* 0x0ffffe00-0x0ffffe0f: RSTC */
#define SAM_SHDC_OFFSET 0x00fffe10 /* 0x0ffffe10-0x0ffffe1f: SHDC */
/* 0x0ffffe20-0x0ffffe2f: Reserved */
#define SAM_PITC_OFFSET 0x00fffe30 /* 0x0ffffe30-0x0ffffe3f: PITC */
#define SAM_WDT_OFFSET 0x00fffe40 /* 0x0ffffe40-0x0ffffe4f: WDT */
#define SAM_SCKCR_OFFSET 0x00fffe50 /* 0x0ffffe50-0x0ffffe53: SCKCR */
#define SAM_BSC_OFFSET 0x00fffe54 /* 0x0ffffe54-0x0ffffe5f: BSC */
#define SAM_GPBR_OFFSET 0x00fffe60 /* 0x0ffffe60-0x0ffffe6f: GPBR */
/* 0x0ffffe70-0x0ffffeaf: Reserved */
#define SAM_RTCC_OFFSET 0x00fffeb0 /* 0x0ffffeb0-0x0ffffedf: RTCC */
/* 0x0ffffee0-0x0fffffff: Reserved */
#define SAM_HSMC_OFFSET 0x00ffc000 /* 0x0fffc000-0x0fffcfff: HSMC */
/* 0x0fffd000-0x0fffe3ff: Reserved */
#define SAM_FUSE_OFFSET 0x00ffe400 /* 0x0fffe400-0x0fffe5ff: FUSE */
#define SAM_DMAC0_OFFSET 0x00ffe600 /* 0x0fffe600-0x0fffe7ff: DMAC0 */
#define SAM_DMAC1_OFFSET 0x00ffe800 /* 0x0fffe800-0x0fffe9ff: DMAC1 */
#define SAM_MPDDRC_OFFSET 0x00ffea00 /* 0x0fffea00-0x0fffebff: MPDDRC */
#define SAM_MATRIX_OFFSET 0x00ffec00 /* 0x0fffec00-0x0fffedff: MATRIX */
#define SAM_DBGU_OFFSET 0x00ffee00 /* 0x0fffee00-0x0fffefff: DBGU */
#define SAM_AIC_OFFSET 0x00fff000 /* 0x0ffff000-0x0ffff1ff: AIC */
#define SAM_PION_OFFSET(n) (0x00fff200+((n) << 9))
#define SAM_PIOA_OFFSET 0x00fff200 /* 0x0ffff200-0x0ffff3ff: PIOA */
#define SAM_PIOB_OFFSET 0x00fff400 /* 0x0ffff400-0x0ffff5ff: PIOB */
#define SAM_PIOC_OFFSET 0x00fff600 /* 0x0ffff600-0x0ffff7ff: PIOC */
#define SAM_PIOD_OFFSET 0x00fff800 /* 0x0ffff800-0x0ffff9ff: PIOD */
#define SAM_PIOE_OFFSET 0x00fffa00 /* 0x0ffffa00-0x0ffffbff: PIOE */
#define SAM_PMC_OFFSET 0x00fffc00 /* 0x0ffffc00-0x0ffffdff: PMC */
#define SAM_RSTC_OFFSET 0x00fffe00 /* 0x0ffffe00-0x0ffffe0f: RSTC */
#define SAM_SHDC_OFFSET 0x00fffe10 /* 0x0ffffe10-0x0ffffe1f: SHDC */
/* 0x0ffffe20-0x0ffffe2f: Reserved */
#define SAM_PITC_OFFSET 0x00fffe30 /* 0x0ffffe30-0x0ffffe3f: PITC */
#define SAM_WDT_OFFSET 0x00fffe40 /* 0x0ffffe40-0x0ffffe4f: WDT */
#define SAM_SCKCR_OFFSET 0x00fffe50 /* 0x0ffffe50-0x0ffffe53: SCKCR */
#define SAM_BSC_OFFSET 0x00fffe54 /* 0x0ffffe54-0x0ffffe5f: BSC */
#define SAM_GPBR_OFFSET 0x00fffe60 /* 0x0ffffe60-0x0ffffe6f: GPBR */
/* 0x0ffffe70-0x0ffffeaf: Reserved */
#define SAM_RTCC_OFFSET 0x00fffeb0 /* 0x0ffffeb0-0x0ffffedf: RTCC */
/* 0x0ffffee0-0x0fffffff: Reserved */
/* Sizes of memory regions in bytes.
*
@ -168,27 +169,27 @@
* region. The implemented sizes of the EBI CS0-3 and DDRCS regions
* are not known apriori and must be specified with configuration settings.
*/
/* 0x00000000-0x0fffffff: Internal Memories */
#define SAM_BOOTMEM_SIZE (1*1024*1024) /* 0x00000000-0x000fffff: Boot memory */
#define SAM_ROM_SIZE (1*1024*1024) /* 0x00100000-0x001fffff: ROM */
#define SAM_NFCSRAM_SIZE (1*1024*1024) /* 0x00200000-0x002fffff: NFC SRAM */
/* 0x00300000-0x003fffff: SRAM0 and SRAM1 */
#define SAM_ISRAM_SIZE (64*1024 + SAM_ISRAM1_SIZE)
#define SAM_SMD_SIZE (1*1024*1024) /* 0x00400000-0x004fffff: SMD */
#define SAM_UDPHSRAM_SIZE (1*1024*1024) /* 0x00500000-0x005fffff: UDPH SRAM */
#define SAM_UHPOHCI_SIZE (1*1024*1024) /* 0x00600000-0x006fffff: UHP OHCI */
#define SAM_UHPEHCI_SIZE (1*1024*1024) /* 0x00700000-0x007fffff: UHP EHCI */
#define SAM_AXIMATRIX_SIZE (1*1024*1024) /* 0x00800000-0x008fffff: AXI Matr */
#define SAM_DAP_SIZE (1*1024*1024) /* 0x00900000-0x009fffff: DAP */
#define SAM_NFCCR_SIZE (256*1024*1024) /* 0x70000000-0x7fffffff: NFC Command Registers */
/* 0xf0000000-0xffffffff: Internal Peripherals */
#define SAM_PERIPHA_SIZE (15*1024) /* 0xf0000000-0xf003bfff: Internal Peripherals */
#define SAM_PERIPHB_SIZE (272*1024) /* 0xf8000000-0xf8043fff: Internal Peripherals */
#define SAM_SYSC_SIZE (1*1024*1024) /* 0xff000000-0x0ffffedf: Internal Peripherals */
/* 0x00000000-0x0fffffff: Internal Memories */
#define SAM_BOOTMEM_SIZE (1*1024*1024) /* 0x00000000-0x000fffff: Boot memory */
#define SAM_ROM_SIZE (1*1024*1024) /* 0x00100000-0x001fffff: ROM */
#define SAM_NFCSRAM_SIZE (1*1024*1024) /* 0x00200000-0x002fffff: NFC SRAM */
/* 0x00300000-0x003fffff: SRAM0 and SRAM1 */
#define SAM_ISRAM_SIZE (64*1024 + SAM_ISRAM1_SIZE)
#define SAM_SMD_SIZE (1*1024*1024) /* 0x00400000-0x004fffff: SMD */
#define SAM_UDPHSRAM_SIZE (1*1024*1024) /* 0x00500000-0x005fffff: UDPH SRAM */
#define SAM_UHPOHCI_SIZE (1*1024*1024) /* 0x00600000-0x006fffff: UHP OHCI */
#define SAM_UHPEHCI_SIZE (1*1024*1024) /* 0x00700000-0x007fffff: UHP EHCI */
#define SAM_AXIMATRIX_SIZE (1*1024*1024) /* 0x00800000-0x008fffff: AXI Matr */
#define SAM_DAP_SIZE (1*1024*1024) /* 0x00900000-0x009fffff: DAP */
#define SAM_NFCCR_SIZE (256*1024*1024) /* 0x70000000-0x7fffffff: NFC Command Registers */
/* 0xf0000000-0xffffffff: Internal Peripherals */
#define SAM_PERIPHA_SIZE (15*1024) /* 0xf0000000-0xf003bfff: Internal Peripherals */
#define SAM_PERIPHB_SIZE (272*1024) /* 0xf8000000-0xf8043fff: Internal Peripherals */
#define SAM_SYSC_SIZE (1*1024*1024) /* 0xff000000-0x0ffffedf: Internal Peripherals */
/* Convert size in bytes to number of sections (in Mb). */
#define _NSECTIONS(b) (((b)+0x000fffff) >> 20)
#define _NSECTIONS(b) (((b)+0x000fffff) >> 20)
/* Sizes of memory regions in sections.
*
@ -198,51 +199,51 @@
* region.
*/
#define SAM_BOOTMEM_NSECTIONS _NSECTIONS(SAM_BOOTMEM_SIZE)
#define SAM_ROM_NSECTIONS _NSECTIONS(SAM_ROM_SIZE)
#define SAM_NFCSRAM_NSECTIONS _NSECTIONS(SAM_NFCSRAM_SIZE)
#define SAM_ISRAM_NSECTIONS _NSECTIONS(SAM_ISRAM_SIZE)
#define SAM_SMD_NSECTIONS _NSECTIONS(SAM_SMD_SIZE)
#define SAM_UDPHSRAM_NSECTIONS _NSECTIONS(SAM_UDPHSRAM_SIZE)
#define SAM_UHPOHCI_NSECTIONS _NSECTIONS(SAM_UHPOHCI_SIZE)
#define SAM_UHPEHCI_NSECTIONS _NSECTIONS(SAM_UHPEHCI_SIZE)
#define SAM_AXIMATRIX_NSECTIONS _NSECTIONS(SAM_AXIMATRIX_SIZE)
#define SAM_DAP_NSECTIONS _NSECTIONS(SAM_DAP_SIZE)
#define SAM_BOOTMEM_NSECTIONS _NSECTIONS(SAM_BOOTMEM_SIZE)
#define SAM_ROM_NSECTIONS _NSECTIONS(SAM_ROM_SIZE)
#define SAM_NFCSRAM_NSECTIONS _NSECTIONS(SAM_NFCSRAM_SIZE)
#define SAM_ISRAM_NSECTIONS _NSECTIONS(SAM_ISRAM_SIZE)
#define SAM_SMD_NSECTIONS _NSECTIONS(SAM_SMD_SIZE)
#define SAM_UDPHSRAM_NSECTIONS _NSECTIONS(SAM_UDPHSRAM_SIZE)
#define SAM_UHPOHCI_NSECTIONS _NSECTIONS(SAM_UHPOHCI_SIZE)
#define SAM_UHPEHCI_NSECTIONS _NSECTIONS(SAM_UHPEHCI_SIZE)
#define SAM_AXIMATRIX_NSECTIONS _NSECTIONS(SAM_AXIMATRIX_SIZE)
#define SAM_DAP_NSECTIONS _NSECTIONS(SAM_DAP_SIZE)
#define SAM_EBICS0_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC0_SIZE)
#define SAM_DDRCS_NSECTIONS _NSECTIONS(CONFIG_SAMA5_DDRCS_SIZE)
#define SAM_EBICS1_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC1_SIZE)
#define SAM_EBICS2_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC2_SIZE)
#define SAM_EBICS3_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC3_SIZE)
#define SAM_NFCCR_NSECTIONS _NSECTIONS(SAM_NFCCR_SIZE)
#define SAM_EBICS0_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC0_SIZE)
#define SAM_DDRCS_NSECTIONS _NSECTIONS(CONFIG_SAMA5_DDRCS_SIZE)
#define SAM_EBICS1_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC1_SIZE)
#define SAM_EBICS2_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC2_SIZE)
#define SAM_EBICS3_NSECTIONS _NSECTIONS(CONFIG_SAMA5_EBISC3_SIZE)
#define SAM_NFCCR_NSECTIONS _NSECTIONS(SAM_NFCCR_SIZE)
#define SAM_PERIPHA_NSECTIONS _NSECTIONS(SAM_PERIPHA_SIZE)
#define SAM_PERIPHB_NSECTIONS _NSECTIONS(SAM_PERIPHB_SIZE)
#define SAM_SYSC_NSECTIONS _NSECTIONS(SAM_SYSC_SIZE)
#define SAM_PERIPHA_NSECTIONS _NSECTIONS(SAM_PERIPHA_SIZE)
#define SAM_PERIPHB_NSECTIONS _NSECTIONS(SAM_PERIPHB_SIZE)
#define SAM_SYSC_NSECTIONS _NSECTIONS(SAM_SYSC_SIZE)
/* Section MMU Flags */
#define SAM_BOOTMEM_MMUFLAGS MMU_ROMFLAGS
#define SAM_ROM_MMUFLAGS MMU_ROMFLAGS
#define SAM_NFCSRAM_MMUFLAGS MMU_IOFLAGS
#define SAM_ISRAM_MMUFLAGS MMU_MEMFLAGS
#define SAM_SMD_MMUFLAGS MMU_MEMFLAGS
#define SAM_UDPHSRAM_MMUFLAGS MMU_IOFLAGS
#define SAM_UHPOHCI_MMUFLAGS MMU_IOFLAGS
#define SAM_UHPEHCI_MMUFLAGS MMU_IOFLAGS
#define SAM_AXIMATRIX_MMUFLAGS MMU_IOFLAGS
#define SAM_DAP_MMUFLAGS MMU_IOFLAGS
#define SAM_BOOTMEM_MMUFLAGS MMU_ROMFLAGS
#define SAM_ROM_MMUFLAGS MMU_ROMFLAGS
#define SAM_NFCSRAM_MMUFLAGS MMU_IOFLAGS
#define SAM_ISRAM_MMUFLAGS MMU_MEMFLAGS
#define SAM_SMD_MMUFLAGS MMU_MEMFLAGS
#define SAM_UDPHSRAM_MMUFLAGS MMU_IOFLAGS
#define SAM_UHPOHCI_MMUFLAGS MMU_IOFLAGS
#define SAM_UHPEHCI_MMUFLAGS MMU_IOFLAGS
#define SAM_AXIMATRIX_MMUFLAGS MMU_IOFLAGS
#define SAM_DAP_MMUFLAGS MMU_IOFLAGS
#define SAM_EBICS0_MMUFLAGS MMU_MEMFLAGS
#define SAM_DDRCS_MMUFLAGS MMU_MEMFLAGS
#define SAM_EBICS1_MMUFLAGS MMU_MEMFLAGS
#define SAM_EBICS2_MMUFLAGS MMU_MEMFLAGS
#define SAM_EBICS3_MMUFLAGS MMU_MEMFLAGS
#define SAM_NFCCR_MMUFLAGS MMU_IOFLAGS
#define SAM_EBICS0_MMUFLAGS MMU_MEMFLAGS
#define SAM_DDRCS_MMUFLAGS MMU_MEMFLAGS
#define SAM_EBICS1_MMUFLAGS MMU_MEMFLAGS
#define SAM_EBICS2_MMUFLAGS MMU_MEMFLAGS
#define SAM_EBICS3_MMUFLAGS MMU_MEMFLAGS
#define SAM_NFCCR_MMUFLAGS MMU_IOFLAGS
#define SAM_PERIPHA_MMUFLAGS MMU_IOFLAGS
#define SAM_PERIPHB_MMUFLAGS MMU_IOFLAGS
#define SAM_SYSC_MMUFLAGS MMU_IOFLAGS
#define SAM_PERIPHA_MMUFLAGS MMU_IOFLAGS
#define SAM_PERIPHB_MMUFLAGS MMU_IOFLAGS
#define SAM_SYSC_MMUFLAGS MMU_IOFLAGS
/* SAMA5 Virtual (mapped) Memory Map
*
@ -333,6 +334,7 @@
#define SAM_MATRIX_VBASE (SAM_SYSC_VSECTION+SAM_MATRIX_OFFSET)
#define SAM_DBGU_VBASE (SAM_SYSC_VSECTION+SAM_DBGU_OFFSET)
#define SAM_AIC_VBASE (SAM_SYSC_VSECTION+SAM_AIC_OFFSET)
#define SAM_PION_VBASE(n) (SAM_SYSC_VSECTION+SAM_PION_OFFSET(n))
#define SAM_PIOA_VBASE (SAM_SYSC_VSECTION+SAM_PIOA_OFFSET)
#define SAM_PIOB_VBASE (SAM_SYSC_VSECTION+SAM_PIOB_OFFSET)
#define SAM_PIOC_VBASE (SAM_SYSC_VSECTION+SAM_PIOC_OFFSET)
@ -356,13 +358,13 @@
*/
#if defined(CONFIG_BOOT_RUNFROMFLASH)
# define NUTTX_START_VADDR CONFIG_SAMA5_NORFLASH_VBASE
# define NUTTX_START_VADDR CONFIG_SAMA5_NORFLASH_VBASE
#elif defined(CONFIG_BOOT_RUNFROMSDRAM)
# define NUTTX_START_VADDR SAM_DDRCS_VSECTION
# define NUTTX_START_VADDR SAM_DDRCS_VSECTION
#elif defined(CONFIG_BOOT_RUNFROMEXTSRAM)
# define NUTTX_START_VADDR CONFIG_SAMA5_SRAM_VBASE
# define NUTTX_START_VADDR CONFIG_SAMA5_SRAM_VBASE
#else /* CONFIG_BOOT_RUNFROMISRAM, CONFIG_PAGING */
# define NUTTX_START_VADDR SAM_ISRAM_VSECTION
# define NUTTX_START_VADDR SAM_ISRAM_VSECTION
#endif
/* MMU Page Table Location
@ -427,7 +429,7 @@
# define PGTABLE_BASE_VADDR (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE)
# endif
# endif
# define PGTABLE_IN_HIGHSRAM 1
# define PGTABLE_IN_HIGHSRAM 1
# else
/* Otherwise, ISRAM1 (or ISRAM0 if ISRAM1 is not available in this
@ -436,11 +438,11 @@
* the first 16Kb of ISRAM0.
*/
# define PGTABLE_BASE_PADDR SAM_ISRAM0_PADDR
# define PGTABLE_BASE_PADDR SAM_ISRAM0_PADDR
# ifndef CONFIG_PAGING
# define PGTABLE_BASE_VADDR SAM_ISRAM0_VADDR
# define PGTABLE_BASE_VADDR SAM_ISRAM0_VADDR
# endif
# define PGTABLE_IN_LOWSRAM 1
# define PGTABLE_IN_LOWSRAM 1
# endif
#endif
@ -454,19 +456,19 @@
* of the page table.
*/
#define PGTABLE_L2_PBASE (PGTABLE_BASE_PADDR+0x00000800)
#define PGTABLE_L2_VBASE (PGTABLE_BASE_VADDR+0x00000800)
#define PGTABLE_L2_PBASE (PGTABLE_BASE_PADDR+0x00000800)
#define PGTABLE_L2_VBASE (PGTABLE_BASE_VADDR+0x00000800)
/* Page table end addresses: */
#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE)
#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE)
#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE)
#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE)
/* Page table sizes */
#define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_VBASE)
#define PGTABLE_L2_SIZE (4*256)
#define PGTABLE_L2_NENTRIES (PGTABLE_L2_ALLOC / PGTABLE_L2_SIZE)
#define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_VBASE)
#define PGTABLE_L2_SIZE (4*256)
#define PGTABLE_L2_NENTRIES (PGTABLE_L2_ALLOC / PGTABLE_L2_SIZE)
/* Base address of the interrupt vector table.
*
@ -475,22 +477,22 @@
* SAM_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000)
*/
#define VECTOR_TABLE_SIZE 0x00010000
#define VECTOR_TABLE_SIZE 0x00010000
#ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */
# define SAM_VECTOR_PADDR SAM_ISRAM0_PADDR
# define SAM_VECTOR_VSRAM SAM_ISRAM0_VADDR
# define SAM_VECTOR_VADDR 0x00000000
# define SAM_VECTOR_VCOARSE 0x00000000
# define SAM_VECTOR_PADDR SAM_ISRAM0_PADDR
# define SAM_VECTOR_VSRAM SAM_ISRAM0_VADDR
# define SAM_VECTOR_VADDR 0x00000000
# define SAM_VECTOR_VCOARSE 0x00000000
#else /* Vectors located at 0xffff:0000 -- this probably does not work */
# ifdef HAVE_ISRAM1
# define SAM_VECTOR_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
# define SAM_VECTOR_VSRAM (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
# define SAM_VECTOR_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
# define SAM_VECTOR_VSRAM (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
# else
# define SAM_VECTOR_PADDR (SAM_ISRAM0_PADDR+SAM_ISRAM0_SIZE-VECTOR_TABLE_SIZE)
# define SAM_VECTOR_VSRAM (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-VECTOR_TABLE_SIZE)
# define SAM_VECTOR_PADDR (SAM_ISRAM0_PADDR+SAM_ISRAM0_SIZE-VECTOR_TABLE_SIZE)
# define SAM_VECTOR_VSRAM (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-VECTOR_TABLE_SIZE)
# endif
# define SAM_VECTOR_VADDR 0xffff0000
# define SAM_VECTOR_VCOARSE 0xfff00000
# define SAM_VECTOR_VADDR 0xffff0000
# define SAM_VECTOR_VCOARSE 0xfff00000
#endif
/************************************************************************************

547
arch/arm/src/sama5/sam_gpio.c Normal file
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@ -0,0 +1,547 @@
/****************************************************************************
* arch/arm/src/sama5/sam_gpio.c
* General Purpose Input/Output (GPIO) logic for the SAMA5
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "up_internal.h"
#include "up_arch.h"
#include "chip.h"
#include "sam_gpio.h"
#include "chip/sam_pio.h"
/****************************************************************************
* Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_DEBUG_GPIO
static const char g_portchar[4] = { 'A', 'B', 'C', 'D' };
#endif
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: sam_gpiobase
*
* Description:
* Return the base address of the GPIO register set
*
****************************************************************************/
static inline uintptr_t sam_gpiobase(gpio_pinset_t cfgset)
{
int port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
return SAM_PION_VBASE(port);
}
/****************************************************************************
* Name: sam_gpiopin
*
* Description:
* Returun the base address of the GPIO register set
*
****************************************************************************/
static inline int sam_gpiopin(gpio_pinset_t cfgset)
{
return 1 << ((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
}
/****************************************************************************
* Name: sam_configinput
*
* Description:
* Configure a GPIO input pin based on bit-encoded description of the pin.
*
****************************************************************************/
static inline int sam_configinput(uintptr_t base, uint32_t pin,
gpio_pinset_t cfgset)
{
#if defined(GPIO_HAVE_SCHMITT) || defined(GPIO_HAVE_DRIVE)
uint32_t regval;
#endif
#if defined(GPIO_HAVE_DRIVE)
uint32_t offset;
uint32_t mask;
uint32_t drive;
int shift;
#endif
/* Disable interrupts on the pin */
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
/* Enable/disable the pull-up as requested */
if ((cfgset & GPIO_CFG_PULLUP) != 0)
{
putreg32(pin, base + SAM_PIO_PUER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
}
#ifdef GPIO_HAVE_PULLDOWN
/* Enable/disable the pull-down as requested */
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
{
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
}
#endif
/* Check if filtering should be enabled */
if ((cfgset & GPIO_CFG_DEGLITCH) != 0)
{
putreg32(pin, base + SAM_PIO_IFER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_IFDR_OFFSET);
}
#ifdef GPIO_HAVE_SCHMITT
/* Enable/disable the Schmitt trigger */
regval = getreg32(base + SAM_PIO_SCHMITT_OFFSET);
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
{
regval |= pin;
}
else
{
regval &= ~pin;
}
putreg32(regval, base + SAM_PIO_SCHMITT_OFFSET);
#endif
#ifdef GPIO_HAVE_DRIVE
/* Configure drive strength */
drive = (cfgset & GPIO_DRIVE_MASK) >> GPIO_DRIVE_SHIFT;
if (pin < 32)
{
offset = SAM_PIO_DRIVER1_OFFSET;
mask = PIO_DRIVER1_LINE_MASK(pin);
shift = PIO_DRIVER1_LINE_SHIFT(pin);
}
else
{
offset = SAM_PIO_DRIVER2_OFFSET;
mask = PIO_DRIVER2_LINE_MASK(pin);
shift = PIO_DRIVER2_LINE_SHIFT(pin);
}
regval = getreg32(base + offset);
regval &= ~mask;
regval |= drive << shift;
putreg32(regval, base + offset);
#endif
/* Configure the pin as an input and enable the GPIO function */
putreg32(pin, base + SAM_PIO_ODR_OFFSET);
putreg32(pin, base + SAM_PIO_PER_OFFSET);
/* To-Do: If DEGLITCH is selected, need to configure DIFSR, SCIFSR, and
* IFDGSR registers. This would probably best be done with
* another, new API... perhaps sam_configfilter()
*/
return OK;
}
/****************************************************************************
* Name: sam_configoutput
*
* Description:
* Configure a GPIO output pin based on bit-encoded description of the pin.
*
****************************************************************************/
static inline int sam_configoutput(uintptr_t base, uint32_t pin,
gpio_pinset_t cfgset)
{
/* Disable interrupts on the pin */
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
/* Enable/disable the pull-up as requested */
if ((cfgset & GPIO_CFG_PULLUP) != 0)
{
putreg32(pin, base + SAM_PIO_PUER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
}
#ifdef GPIO_HAVE_PULLDOWN
/* Enable/disable the pull-down as requested */
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
{
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
}
#endif
/* Enable the open drain driver if requrested */
if ((cfgset & GPIO_CFG_OPENDRAIN) != 0)
{
putreg32(pin, base + SAM_PIO_MDER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_MDDR_OFFSET);
}
/* Set default value */
if ((cfgset & GPIO_OUTPUT_SET) != 0)
{
putreg32(pin, base + SAM_PIO_SODR_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_CODR_OFFSET);
}
/* Configure the pin as an output and enable the GPIO function */
putreg32(pin, base + SAM_PIO_OER_OFFSET);
putreg32(pin, base + SAM_PIO_PER_OFFSET);
return OK;
}
/****************************************************************************
* Name: sam_configperiph
*
* Description:
* Configure a GPIO pin driven by a peripheral A or B signal based on
* bit-encoded description of the pin.
*
****************************************************************************/
static inline int sam_configperiph(uintptr_t base, uint32_t pin,
gpio_pinset_t cfgset)
{
uint32_t regval;
/* Disable interrupts on the pin */
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
/* Enable/disable the pull-up as requested */
if ((cfgset & GPIO_CFG_PULLUP) != 0)
{
putreg32(pin, base + SAM_PIO_PUER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
}
#ifdef GPIO_HAVE_PULLDOWN
/* Enable/disable the pull-down as requested */
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
{
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
}
#endif
#ifdef GPIO_HAVE_PERIPHCD
/* Configure pin, depending upon the peripheral A, B, C or D
*
* PERIPHA: ABCDSR1[n] = 0 ABCDSR2[n] = 0
* PERIPHB: ABCDSR1[n] = 1 ABCDSR2[n] = 0
* PERIPHC: ABCDSR1[n] = 0 ABCDSR2[n] = 1
* PERIPHD: ABCDSR1[n] = 1 ABCDSR2[n] = 1
*/
regval = getreg32(base + SAM_PIO_ABCDSR1_OFFSET);
if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA ||
(cfgset & GPIO_MODE_MASK) == GPIO_PERIPHC)
{
regval &= ~pin;
}
else
{
regval |= pin;
}
putreg32(regval, base + SAM_PIO_ABCDSR1_OFFSET);
regval = getreg32(base + SAM_PIO_ABCDSR2_OFFSET);
if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA ||
(cfgset & GPIO_MODE_MASK) == GPIO_PERIPHB)
{
regval &= ~pin;
}
else
{
regval |= pin;
}
putreg32(regval, base + SAM_PIO_ABCDSR2_OFFSET);
#else
/* Configure pin, depending upon the peripheral A or B:
*
* PERIPHA: ABSR[n] = 0
* PERIPHB: ABSR[n] = 1
*/
regval = getreg32(base + SAM_PIO_ABSR_OFFSET);
if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA)
{
regval &= ~pin;
}
else
{
regval |= pin;
}
putreg32(regval, base + SAM_PIO_ABSR_OFFSET);
#endif
/* Disable PIO functionality */
putreg32(pin, base + SAM_PIO_PDR_OFFSET);
return OK;
}
/****************************************************************************
* Global Functions
****************************************************************************/
/****************************************************************************
* Name: sam_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
*
****************************************************************************/
int sam_configgpio(gpio_pinset_t cfgset)
{
uintptr_t base = sam_gpiobase(cfgset);
uint32_t pin = sam_gpiopin(cfgset);
irqstate_t flags;
int ret;
/* Disable interrupts to prohibit re-entrance. */
flags = irqsave();
/* Enable writing to GPIO registers */
putreg32(PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
/* Handle the pin configuration according to pin type */
switch (cfgset & GPIO_MODE_MASK)
{
case GPIO_INPUT:
ret = sam_configinput(base, pin, cfgset);
break;
case GPIO_OUTPUT:
ret = sam_configoutput(base, pin, cfgset);
break;
case GPIO_PERIPHA:
case GPIO_PERIPHB:
#ifdef GPIO_HAVE_PERIPHCD
case GPIO_PERIPHC:
case GPIO_PERIPHD:
#endif
ret = sam_configperiph(base, pin, cfgset);
break;
default:
ret = -EINVAL;
break;
}
/* Disable writing to GPIO registers */
putreg32(PIO_WPMR_WPEN | PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
irqrestore(flags);
return ret;
}
/****************************************************************************
* Name: sam_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void sam_gpiowrite(gpio_pinset_t pinset, bool value)
{
uintptr_t base = sam_gpiobase(pinset);
uint32_t pin = sam_gpiopin(pinset);
if (value)
{
putreg32(pin, base + SAM_PIO_SODR_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_CODR_OFFSET);
}
}
/****************************************************************************
* Name: sam_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool sam_gpioread(gpio_pinset_t pinset)
{
uintptr_t base = sam_gpiobase(pinset);
uint32_t pin = sam_gpiopin(pinset);
uint32_t regval;
if ((pinset & GPIO_MODE_MASK) == GPIO_OUTPUT)
{
regval = getreg32(base + SAM_PIO_ODSR_OFFSET);
}
else
{
regval = getreg32(base + SAM_PIO_PDSR_OFFSET);
}
return (regval & pin) != 0;
}
/************************************************************************************
* Function: sam_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the base address of the provided pinset.
*
************************************************************************************/
#ifdef CONFIG_DEBUG_GPIO
int sam_dumpgpio(uint32_t pinset, const char *msg)
{
irqstate_t flags;
uintptr_t base;
unsigned int pin;
unsigned int port;
/* Get the base address associated with the PIO port */
pin = sam_gpiopin(pinset);
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
base = SAM_PION_BASE(port);
/* The following requires exclusive access to the GPIO registers */
flags = irqsave();
lldbg("PIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
lldbg(" PSR: %08x OSR: %08x IFSR: %08x ODSR: %08x\n",
getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET));
lldbg(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n",
getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
lldbg(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n",
getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIOC_PPDSR));
lldbg(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n",
getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET));
lldbg(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n",
getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET),
getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET));
lldbg(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n",
getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
lldbg(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
lldbg("SCHMITT: %08x\n",
getreg32(base + SAM_PIO_SCHMITT_OFFSET));
irqrestore(flags);
return OK;
}
#endif

340
arch/arm/src/sama5/sam_gpio.h Normal file
View File

@ -0,0 +1,340 @@
/************************************************************************************
* arch/arm/src/sama5/sam_gpio.h
* General Purpose Input/Output (GPIO) definitions for the SAM4S
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_GPIO_H
#define __ARCH_ARM_SRC_SAMA5_SAM_GPIO_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
/************************************************************************************
* Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#if defined(CONFIG_PIOA_IRQ) || defined(CONFIG_PIOB_IRQ) || \
defined(CONFIG_PIOC_IRQ) || defined(CONFIG_PIOD_IRQ) || \
defined(CONFIG_PIOD_IRQ)
# define CONFIG_PIO_IRQ 1
#else
# undef CONFIG_PIO_IRQ
#endif
#ifndef CONFIG_DEBUG
# undef CONFIG_DEBUG_GPIO
#endif
#define GPIO_HAVE_PULLDOWN 1
#define GPIO_HAVE_PERIPHCD 1
#define GPIO_HAVE_SCHMITT 1
#define GPIO_HAVE_DRIVE 1
/* Bit-encoded input to sam_configgpio() ********************************************/
/* 32-bit Encoding:
*
* ..MM MCCC CCDD IIIV PPPB BBBB
*/
/* Input/Output mode:
*
* ..MM M... .... .... .... ....
*/
#define GPIO_MODE_SHIFT (19) /* Bits 19-21: GPIO mode */
#define GPIO_MODE_MASK (7 << GPIO_MODE_SHIFT)
# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input */
# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* Output */
# define GPIO_PERIPHA (2 << GPIO_MODE_SHIFT) /* Controlled by periph A signal */
# define GPIO_PERIPHB (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */
# define GPIO_PERIPHC (4 << GPIO_MODE_SHIFT) /* Controlled by periph C signal */
# define GPIO_PERIPHD (5 << GPIO_MODE_SHIFT) /* Controlled by periph D signal */
/* These bits set the configuration of the pin:
* NOTE: No definitions for parallel capture mode
*
* .... .CCC CC.. .... .... ....
*/
#define GPIO_CFG_SHIFT (14) /* Bits 14-18: GPIO configuration bits */
#define GPIO_CFG_MASK (31 << GPIO_CFG_SHIFT)
# define GPIO_CFG_DEFAULT (0 << GPIO_CFG_SHIFT) /* Default, no attribute */
# define GPIO_CFG_PULLUP (1 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-up */
# define GPIO_CFG_PULLDOWN (2 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-down */
# define GPIO_CFG_DEGLITCH (4 << GPIO_CFG_SHIFT) /* Bit 12: Internal glitch filter */
# define GPIO_CFG_OPENDRAIN (8 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */
# define GPIO_CFG_SCHMITT (16 << GPIO_CFG_SHIFT) /* Bit 13: Schmitt trigger */
/* Drive Strength:
*
* .... .... ..DD .... .... ....
*/
#define GPIO_DRIVE_SHIFT (12) /* Bits 12-13: Drive strength */
#define GPIO_DRIVE_MASK (7 << GPIO_DRIVE_SHIFT)
# define GPIO_DRIVE_LOW (0 << GPIO_DRIVE_SHIFT)
# define GPIO_DRIVE_MEDIUM (2 << GPIO_DRIVE_SHIFT)
# define GPIO_DRIVE_HIGH (3 << GPIO_DRIVE_SHIFT)
/* Additional interrupt modes:
*
* .... .... .... III. .... ....
*/
#define GPIO_INT_SHIFT (9) /* Bits 9-11: GPIO interrupt bits */
#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT)
# define _GIO_INT_AIM (1 << 10) /* Bit 10: Additional Interrupt modes */
# define _GPIO_INT_LEVEL (1 << 9) /* Bit 9: Level detection interrupt */
# define _GPIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */
# define _GPIO_INT_RH (1 << 8) /* Bit 9: Rising edge/High level detection interrupt */
# define _GPIO_INT_FL (0) /* (vs. Falling edge/Low level detection interrupt) */
# define GPIO_INT_HIGHLEVEL (_GIO_INT_AIM | _GPIO_INT_LEVEL | _GPIO_INT_RH)
# define GPIO_INT_LOWLEVEL (_GIO_INT_AIM | _GPIO_INT_LEVEL | _GPIO_INT_FL)
# define GPIO_INT_RISING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_RH)
# define GPIO_INT_FALLING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_FL)
# define GPIO_INT_BOTHEDGES (0)
/* If the pin is an GPIO output, then this identifies the initial output value:
*
* .... .... .... ...V .... ....
*/
#define GPIO_OUTPUT_SET (1 << 8) /* Bit 8: Inital value of output */
#define GPIO_OUTPUT_CLEAR (0)
/* This identifies the GPIO port:
*
* .... .... .... .... PPP. ....
*/
#define GPIO_PORT_SHIFT (5) /* Bit 5-7: Port number */
#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
# define GPIO_PORT_PIOA (0 << GPIO_PORT_SHIFT)
# define GPIO_PORT_PIOB (1 << GPIO_PORT_SHIFT)
# define GPIO_PORT_PIOC (2 << GPIO_PORT_SHIFT)
# define GPIO_PORT_PIOD (3 << GPIO_PORT_SHIFT)
# define GPIO_PORT_PIOE (4 << GPIO_PORT_SHIFT)
/* This identifies the bit in the port:
*
* .... .... .... .... ...B BBBB
*/
#define GPIO_PIN_SHIFT (0) /* Bits 0-4: GPIO number: 0-31 */
#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT)
#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT)
#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT)
#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT)
#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT)
#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT)
#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT)
#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT)
#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT)
#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT)
#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT)
#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT)
#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT)
#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT)
#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
/************************************************************************************
* Public Types
************************************************************************************/
/* Must be big enough to hold the 32-bit encoding */
typedef uint32_t gpio_pinset_t;
/************************************************************************************
* Inline Functions
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Data
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: sam_gpioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for GPIO pins.
*
************************************************************************************/
#ifdef CONFIG_PIO_IRQ
void sam_gpioirqinitialize(void);
#else
# define sam_gpioirqinitialize()
#endif
/************************************************************************************
* Name: sam_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
*
************************************************************************************/
int sam_configgpio(gpio_pinset_t cfgset);
/************************************************************************************
* Name: sam_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
************************************************************************************/
void sam_gpiowrite(gpio_pinset_t pinset, bool value);
/************************************************************************************
* Name: sam_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
************************************************************************************/
bool sam_gpioread(gpio_pinset_t pinset);
/************************************************************************************
* Name: sam_gpioirq
*
* Description:
* Configure an interrupt for the specified GPIO pin.
*
************************************************************************************/
#ifdef CONFIG_PIO_IRQ
void sam_gpioirq(gpio_pinset_t pinset);
#else
# define sam_gpioirq(pinset)
#endif
/************************************************************************************
* Name: sam_gpioirqenable
*
* Description:
* Enable the interrupt for specified GPIO IRQ
*
************************************************************************************/
#ifdef CONFIG_PIO_IRQ
void sam_gpioirqenable(int irq);
#else
# define sam_gpioirqenable(irq)
#endif
/************************************************************************************
* Name: sam_gpioirqdisable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
************************************************************************************/
#ifdef CONFIG_PIO_IRQ
void sam_gpioirqdisable(int irq);
#else
# define sam_gpioirqdisable(irq)
#endif
/************************************************************************************
* Function: sam_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the base address of the provided pinset.
*
************************************************************************************/
#ifdef CONFIG_DEBUG_GPIO
int sam_dumpgpio(uint32_t pinset, const char *msg);
#else
# define sam_dumpgpio(p,m)
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_GPIO_H */

26
arch/arm/src/sama5/sam_lowputc.c
View File

@ -140,37 +140,37 @@
/* Select USART parameters for the selected console */
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
# define SAM_CONSOLE_BASE SAM_UART0_BASE
# define SAM_CONSOLE_VBASE SAM_UART0_VBASE
# define SAM_CONSOLE_BAUD CONFIG_UART0_BAUD
# define SAM_CONSOLE_BITS CONFIG_UART0_BITS
# define SAM_CONSOLE_PARITY CONFIG_UART0_PARITY
# define SAM_CONSOLE_2STOP CONFIG_UART0_2STOP
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
# define SAM_CONSOLE_BASE SAM_UART1_BASE
# define SAM_CONSOLE_VBASE SAM_UART1_VBASE
# define SAM_CONSOLE_BAUD CONFIG_UART1_BAUD
# define SAM_CONSOLE_BITS CONFIG_UART1_BITS
# define SAM_CONSOLE_PARITY CONFIG_UART1_PARITY
# define SAM_CONSOLE_2STOP CONFIG_UART1_2STOP
#elif defined(CONFIG_USART0_SERIAL_CONSOLE)
# define SAM_CONSOLE_BASE SAM_USART0_BASE
# define SAM_CONSOLE_VBASE SAM_USART0_VBASE
# define SAM_CONSOLE_BAUD CONFIG_USART0_BAUD
# define SAM_CONSOLE_BITS CONFIG_USART0_BITS
# define SAM_CONSOLE_PARITY CONFIG_USART0_PARITY
# define SAM_CONSOLE_2STOP CONFIG_USART0_2STOP
#elif defined(CONFIG_USART1_SERIAL_CONSOLE)
# define SAM_CONSOLE_BASE SAM_USART1_BASE
# define SAM_CONSOLE_VBASE SAM_USART1_VBASE
# define SAM_CONSOLE_BAUD CONFIG_USART1_BAUD
# define SAM_CONSOLE_BITS CONFIG_USART1_BITS
# define SAM_CONSOLE_PARITY CONFIG_USART1_PARITY
# define SAM_CONSOLE_2STOP CONFIG_USART1_2STOP
#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
# define SAM_CONSOLE_BASE SAM_USART2_BASE
# define SAM_CONSOLE_VBASE SAM_USART2_VBASE
# define SAM_CONSOLE_BAUD CONFIG_USART2_BAUD
# define SAM_CONSOLE_BITS CONFIG_USART2_BITS
# define SAM_CONSOLE_PARITY CONFIG_USART2_PARITY
# define SAM_CONSOLE_2STOP CONFIG_USART2_2STOP
#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
# define SAM_CONSOLE_BASE SAM_USART3_BASE
# define SAM_CONSOLE_VBASE SAM_USART3_VBASE
# define SAM_CONSOLE_BAUD CONFIG_USART3_BAUD
# define SAM_CONSOLE_BITS CONFIG_USART3_BITS
# define SAM_CONSOLE_PARITY CONFIG_USART3_PARITY
@ -249,11 +249,11 @@ void up_lowputc(char ch)
{
/* Wait for the transmitter to be available */
while ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) == 0);
while ((getreg32(SAM_CONSOLE_VBASE + SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) == 0);
/* Send the character */
putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET);
putreg32((uint32_t)ch, SAM_CONSOLE_VBASE + SAM_UART_THR_OFFSET);
}
/**************************************************************************
@ -350,27 +350,27 @@ void sam_lowsetup(void)
/* Reset and disable receiver and transmitter */
putreg32((UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS),
SAM_CONSOLE_BASE + SAM_UART_CR_OFFSET);
SAM_CONSOLE_VBASE + SAM_UART_CR_OFFSET);
/* Disable all interrupts */
putreg32(0xffffffff, SAM_CONSOLE_BASE + SAM_UART_IDR_OFFSET);
putreg32(0xffffffff, SAM_CONSOLE_VBASE + SAM_UART_IDR_OFFSET);
/* Set up the mode register */
putreg32(MR_VALUE, SAM_CONSOLE_BASE + SAM_UART_MR_OFFSET);
putreg32(MR_VALUE, SAM_CONSOLE_VBASE + SAM_UART_MR_OFFSET);
/* Configure the console baud. NOTE: Oversampling by 8 is not supported.
* This may limit BAUD rates for lower USART clocks.
*/
putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / (SAM_CONSOLE_BAUD << 4)),
SAM_CONSOLE_BASE + SAM_UART_BRGR_OFFSET);
SAM_CONSOLE_VBASE + SAM_UART_BRGR_OFFSET);
/* Enable receiver & transmitter */
putreg32((UART_CR_RXEN | UART_CR_TXEN),
SAM_CONSOLE_BASE + SAM_UART_CR_OFFSET);
SAM_CONSOLE_VBASE + SAM_UART_CR_OFFSET);
#endif
}

2
arch/arm/src/sama5/sam_periphclks.h
View File

@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include "chip/sam3u_pmc.h"
#include "chip/sam_pmc.h"
/************************************************************************************
* Pre-processor Definitions

16
arch/arm/src/sama5/sam_serial.c
View File

@ -391,7 +391,7 @@ static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE];
#ifdef CONFIG_SAM34_UART0
static struct up_dev_s g_uart0priv =
{
.usartbase = SAM_UART0_BASE,
.usartbase = SAM_UART0_VBASE,
.baud = CONFIG_UART0_BAUD,
.irq = SAM_IRQ_UART0,
.parity = CONFIG_UART0_PARITY,
@ -421,7 +421,7 @@ static uart_dev_t g_uart0port =
#ifdef CONFIG_SAM34_UART1
static struct up_dev_s g_uart1priv =
{
.usartbase = SAM_UART1_BASE,
.usartbase = SAM_UART1_VBASE,
.baud = CONFIG_UART1_BAUD,
.irq = SAM_IRQ_UART1,
.parity = CONFIG_UART1_PARITY,
@ -451,7 +451,7 @@ static uart_dev_t g_uart1port =
#ifdef CONFIG_SAM34_USART0
static struct up_dev_s g_usart0priv =
{
.usartbase = SAM_USART0_BASE,
.usartbase = SAM_USART0_VBASE,
.baud = CONFIG_USART0_BAUD,
.irq = SAM_IRQ_USART0,
.parity = CONFIG_USART0_PARITY,
@ -481,7 +481,7 @@ static uart_dev_t g_usart0port =
#ifdef CONFIG_SAM34_USART1
static struct up_dev_s g_usart1priv =
{
.usartbase = SAM_USART1_BASE,
.usartbase = SAM_USART1_VBASE,
.baud = CONFIG_USART1_BAUD,
.irq = SAM_IRQ_USART1,
.parity = CONFIG_USART1_PARITY,
@ -511,7 +511,7 @@ static uart_dev_t g_usart1port =
#ifdef CONFIG_SAM34_USART2
static struct up_dev_s g_usart2priv =
{
.usartbase = SAM_USART2_BASE,
.usartbase = SAM_USART2_VBASE,
.baud = CONFIG_USART2_BAUD,
.irq = SAM_IRQ_USART2,
.parity = CONFIG_USART2_PARITY,
@ -541,7 +541,7 @@ static uart_dev_t g_usart2port =
#ifdef CONFIG_SAM34_USART3
static struct up_dev_s g_usart3priv =
{
.usartbase = SAM_USART3_BASE,
.usartbase = SAM_USART3_VBASE,
.baud = CONFIG_USART3_BAUD,
.irq = SAM_IRQ_USART3,
.parity = CONFIG_USART3_PARITY,
@ -669,10 +669,10 @@ static int up_setup(struct uart_dev_s *dev)
#ifdef HAVE_USART
else if (priv->bits == 9
#if defined(CONFIG_SAM34_UART0)
&& priv->usartbase != SAM_UART0_BASE
&& priv->usartbase != SAM_UART0_VBASE
#endif
#if defined(CONFIG_SAM34_UART1)
&& priv->usartbase != SAM_UART1_BASE
&& priv->usartbase != SAM_UART1_VBASE
#endif
)
{