Removed unused ARMv7-A cache function
This commit is contained in:
Gregory Nutt
parent
efa21b82bc
commit
f0e3011fc3
@ -98,7 +98,6 @@
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.globl cp15_invalidate_dcache_for_dma
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.globl cp15_clean_dcache_for_dma
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.globl cp15_flush_dcache_for_dma
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.globl cp15_flush_kern_dcache_for_dma
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/****************************************************************************
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* Public Functions
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@ -302,44 +301,4 @@ cp15_flush_dcache_for_dma:
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dsb
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bx lr
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.size cp15_flush_dcache_for_dma, . - cp15_flush_dcache_for_dma
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/****************************************************************************
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* Name: cp15_flush_kern_dcache_for_dma
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*
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* Description:
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* Ensure that the data held in the page kaddr is written back to the page
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* in question.
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*
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* Input Parameters:
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* start - virtual start address of region
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* end - virtual end address of region
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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.globl cp15_flush_kern_dcache_for_dma
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.type cp15_flush_kern_dcache_for_dma, function
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cp15_flush_kern_dcache_for_dma:
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mrc CP15_TR(r3) /* Read the Cache Type Register */
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lsr r3, r3, #16 /* Isolate the DMinLine field */
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and r3, r3, #0xf
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mov r2, #4
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mov r2, r2, lsl r3 /* Get the cache line size in bytes */
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add r1, r0, r1
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sub r3, r2, #1 /* R3=Cache line size mask */
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bic r0, r0, r3 /* R0=aligned start address */
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mcrne CP15_DCCIMVAC(r0) /* Clean and invalidate data cache line by VA to PoC */
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add r0, r0, r2 /* R12=Next cache line */
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cmp r0, r1 /* Loop until all cache lines have been cleaned */
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blo 1b /* Merge with loop flushing each D cache line to memory */
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dsb
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bx lr
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.size cp15_flush_kern_dcache_for_dma, . - cp15_flush_kern_dcache_for_dma
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.end
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@ -61,11 +61,6 @@ README
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32kHz RTC Yes Yes Yes Yes
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Packages LFBGA324_A LFBGA324_A LFBGA324_A LFBGA324_A
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Contents
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========
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- Configurations
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Contents
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========
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@ -76,7 +71,8 @@ Contents
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- NuttX EABI "buildroot" Toolchain
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- NuttX OABI "buildroot" Toolchain
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- NXFLAT Toolchain
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- Loading Code
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- Loading Code into SRAM with J-Link
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- Writing to FLASH using SAM-BA
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- Buttons and LEDs
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- Serial Consoles
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- SAMA5D3x-EK Configuration Options
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@ -282,8 +278,8 @@ NXFLAT Toolchain
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8. Edit setenv.h, if necessary, so that the PATH variable includes
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the path to the newly built NXFLAT binaries.
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Loading Code
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============
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Loading Code into SRAM with J-Link
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==================================
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Loading code with the Segger tools and GDB
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------------------------------------------
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@ -307,6 +303,42 @@ Loading Code
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J-Link> setpc <address of __start>
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J-Link> ... start debugging ...
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Writing to FLASH using SAM-BA
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=============================
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Assumed starting configuration:
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1. You have installed the J-Lnk CDC USB driver (Windows only, there is
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no need to install a driver on any regular Linux distribution),
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2. You have the USB connected to DBGU poort (J14)
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3. Terminal configuration: 115200 8N1
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Using SAM-BA to write to FLASH:
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1. Exit the terminal emulation program and remove the USB cable from
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the DBGU port (J14)
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2. Connect the USB cable to the device USB port (J20)
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3. JP9 must open so that (BMS == 1) to boot from on-chip Boot ROM
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4. Press and maintain PB4 CS_BOOT button and power up the board. PB4
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CS_BOOT button prevents booting from Nand or serial Flash by
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disabling Flash Chip Selects after having powered the board, you can
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release the PB4 BS_BOOT button.
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5. On Windows you may need to wait for a device driver to be installed.
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6. Start the SAM-BA application, selecting (1) the correct USB serial
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port, and (2) board = at91sama5d3x-ek.
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7. The SAM-BA menu should appear.
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8. Select the FLASH bank that you want to use and the address to write
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to and "Execute"
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9. When you are finished writing to FLASH, remove the USB cable from J20
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and re-connect the serial link on USB CDC / DBGU connector (J14) and
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re-open the terminal emulator program.
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10. Power cycle the board.
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NOTES: By closing JP9 (BMS == 0), you can force the board to boot
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directly to NOR FLASH. Executing from other memories will require that
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you provide a special code header so that you code can be recognized as a
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boot-able image by the ROM bootloader.
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Buttons and LEDs
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================
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@ -52,7 +52,7 @@
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*
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* MAINOSC: Frequency = 12MHz (crysta)
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* PLLA: PLL Divider = 1, Multiplier = 66 to generate PLLACK = 792MHz
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* Master Clock (MCK): Source = PLLACK/2, Prescalar = 1, MDIV = to generate
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* Master Clock (MCK): Source = PLLACK/2, Prescalar = 1, MDIV = 3 to generate
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* MCK = 132MHz
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* CPU clock = 396MHz
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*/
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@ -88,7 +88,7 @@
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* Prescaler input = 792MHz / 2 = 396MHz
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* Prescaler output = 792MHz / 1 = 396MHz
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* Processor Clock (PCK) = 396MHz
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* Master clock (MCK) = 396MHz / 3 = 132MHz
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* Master clock (MCK) = 396MHz / 3 = 132MHz
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*/
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#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
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