Add logic to initialize clocks
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1108 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -32,6 +32,35 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Features:
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*
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* - MCU: STR711FR2T6 16/32 bit ARM7TDMI™ with 256K Bytes Program Flash,
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* 64K Bytes RAM, USB 2.0, RTC, 12 bit ADC, 4x UARTs, 2x I2C,2x SPI,
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* 5x 32bit TIMERS, 2x PWM, 2x CCR, WDT, up to 50MHz operation
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* - Standard JTAG connector with ARM 2x10 pin layout for programming/debugging
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* with ARM-JTAG
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* - USB connector
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* - Two channel RS232 interface and drivers
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* - SD/MMC card connector
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* - Two buttons
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* - Trimpot connected to ADC
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* - Two status LEDs
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* - Buzzer
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* - UEXT - 10 pin extension connector for Olimex addon peripherials like MP3,
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* RF2.4Ghz, RFID etc. modules
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* - 2x SPI connectors
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* - I2C connector
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* - On board voltage regulator 3.3V with up to 800mA current
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* - Single power supply: 6V AC or DC required, USB port can power the board
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* - Power supply LED
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* - Power supply filtering capacitor
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* - RESET circuit
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* - RESET button
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* - 4 Mhz crystal oscillator
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* - 32768 Hz crystal and RTC
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*
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****************************************************************************/
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#ifndef _CONFIGS_OLIMEX_STRP711_BOARD_H
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#define _CONFIGS_OLIMEX_STRP711_BOARD_H
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@ -43,6 +72,7 @@
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#ifndef __ASSEMBLY__
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# include <sys/types.h>
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#endif
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#include "chip.h"
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/****************************************************************************
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* Definitions
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@ -50,9 +80,46 @@
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/* Clocking *****************************************************************/
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/* RTC Oscillator Frequency value = 32,768 Hz */
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/* Main Oscillator Frequency = 4MHz */
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#define STR71X_RCCU_RTC_OSC (32768)
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#define STR71X_RCCU_MAIN_OSC (4000000)
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/* RTC Oscillator Frequency = 32,768 Hz */
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#define STR71X_RCCU_RTC_OSC (32768)
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/* HCLK driving PLL2 */
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#define STR71X_PCU_HCLK_OSC (4000000) /* ? */
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/* PLL1 Setup:
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*
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* PLL1 input clock: CLK2 = Main OSC = 4MHz
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* PLL1 output clock: PLL1OUT = 16 * CLK2 / 2 = 32MHz
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* PLL1 output: CLK3 = PLL1OUT = 32MHz (hard coded selection)
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* RCLK = CLK3 = 32MHz (hard coded selection)
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* APB1 peripheral clock: PCLK1 = RCLK = 32MHz
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* APB2 peripheral clock: PCLK2 = RCLK = 32MHz
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* Main system clock: MCLK = RCLK = 32MHz
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*/
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#undef STR71X_PLL1IN_DIV2 /* Don't divide main OSC by two */
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#define STR71X_PLL1OUT_MUL STR71X_RCCUPLL1CR_MUL16 /* PLL1OUT = 16 * CLK2 */
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#define STR71X_PLL1OUT_DIV STR71X_RCCUPLL1CR_DIV2 /* PLL1OUT = CLK2 / 2 */
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#define STR71X_APB1_DIV STR71X_PCUPDIVR_APB1DIV1 /* PCLK1 = RCLK */
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#define STR71X_APB2_DIV STR71X_PCUPDIVR_APB1DIV1 /* PCLK2 = RCLK */
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#define STR71X_MCLK_DIV STR71X_PCUMDIVR_DIV1 /* MCLK = RCLK */
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/* PLL2 Setup -- only needed for HDLC or USB
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*
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* USB input: USB clock
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* HCLK = 4MHz?
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* USB clock = 12 * HCLK / 1 = 48 MHz
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*/
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#undef STR71X_USBIN_PLL2 /* USB input is USB clock */
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#define STR71X_PLL2OUT_MUL STR71X_PCUPPL2CR_MUL12 /* PLL2OUT = 12 * HCLK */
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#define STR71X_PLL2OUT_DIV STR71X_PCUPPL2CR_DIV1 /* PLL2OUT = HCLK / 1 */
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/* LED definitions **********************************************************/
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@ -72,18 +72,48 @@ CONFIG_ARCH_STACKDUMP=y
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#
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# STR71x specific boot/build settings
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#
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# CONFIG_STR71X_I2C0, CONFIG_STR71X_I2C1, CONFIG_STR71X_UART0, CONFIG_STR71X_UART1,
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# CONFIG_STR71X_UART2, CONFIG_STR71X_UART3, CONFIG_STR71X_USB, CONFIG_STR71X_CAN,
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# CONFIG_STR71X_BSPI0, CONFIG_STR71X_BSPI1, CONFIG_STR71X_HDLC, CONFIG_STR71X_XTI,
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# CONFIG_STR71X_GPIO0, CONFIG_STR71X_GPIO1, CONFIG_STR71X_GPIO2, CONFIG_STR71X_ADC12,
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# CONFIG_STR71X_CKOUT, CONFIG_STR71X_TIM1, CONFIG_STR71X_TIM2, CONFIG_STR71X_TIM3, and
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# CONFIG_STR71X_RTC
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# Select peripherals to initialize (Timer0 and EIC are always initialized)
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# CONFIG_STR71X_BANK0, CONFIG_STR71X_BANK1, CONFIG_STR71X_BANK2, and CONFIG_STR71X_BANK3
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# Enable initialize of external memory banks 0-3.
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# CONFIG_STR71X_BANK0_SIZE, CONFIG_STR71X_BANK1_SIZE, CONFIG_STR71X_BANK2_SIZE, and CONFIG_STR71X_BANK3_SIZE
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# CONFIG_STR71X_BANK0_SIZE, CONFIG_STR71X_BANK1_SIZE, CONFIG_STR71X_BANK2_SIZE, and
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# CONFIG_STR71X_BANK3_SIZE
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# If a particular external memory bank is configured, then its width must be provided.
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# 8 and 16 (bits) are the only valid options.
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# CONFIG_STR71X_BANK0_WAITSTATES, CONFIG_STR71X_BANK1_WAITSTATES, CONFIG_STR71X_BANK2_WAITSTATES, and CONFIG_STR71X_BANK3_WAITSTATES
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# CONFIG_STR71X_BANK0_WAITSTATES, CONFIG_STR71X_BANK1_WAITSTATES,
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# CONFIG_STR71X_BANK2_WAITSTATES, and CONFIG_STR71X_BANK3_WAITSTATES
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# If a particular external memory bank is configured, then the number of waistates
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# for the bank must also be provided. Valid options are {0, .., 15}
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# CONFIG_STR71X_BIGEXTMEM
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# The default is to provide 20 bits of address for all external memory regions. If
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# any memory region is larger than 1Mb, then this option should be selected. In this
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# case, 24 bits of addressing will be used
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CONFIG_STR71X_I2C0=n
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CONFIG_STR71X_I2C1=n
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CONFIG_STR71X_UART0=y
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CONFIG_STR71X_UART1=y
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CONFIG_STR71X_UART2=n
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CONFIG_STR71X_UART3=n
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CONFIG_STR71X_USB=n
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CONFIG_STR71X_CAN=n
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CONFIG_STR71X_BSPI0=n
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CONFIG_STR71X_BSPI1=n
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CONFIG_STR71X_HDLC=n
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CONFIG_STR71X_XTI=n
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CONFIG_STR71X_GPIO0=y
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CONFIG_STR71X_GPIO1=n
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CONFIG_STR71X_GPIO2=n
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CONFIG_STR71X_ADC12=n
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CONFIG_STR71X_CKOUT=n
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CONFIG_STR71X_TIM1=n
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CONFIG_STR71X_TIM2=n
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CONFIG_STR71X_TIM3=n
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CONFIG_STR71X_RTC=n
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CONFIG_STR71X_BANK0=n
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CONFIG_STR71X_BANK0_SIZE=16
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CONFIG_STR71X_BANK0_WAITSTATES=0
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@ -114,18 +144,32 @@ CONFIG_STR71X_BIGEXTMEM=n
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#
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CONFIG_UART0_SERIAL_CONSOLE=y
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CONFIG_UART1_SERIAL_CONSOLE=n
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CONFIG_UART2_SERIAL_CONSOLE=n
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CONFIG_UART3_SERIAL_CONSOLE=n
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CONFIG_UART0_TXBUFSIZE=256
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CONFIG_UART1_TXBUFSIZE=256
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CONFIG_UART2_TXBUFSIZE=256
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CONFIG_UART3_TXBUFSIZE=256
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CONFIG_UART0_RXBUFSIZE=256
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CONFIG_UART1_RXBUFSIZE=256
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CONFIG_UART2_RXBUFSIZE=256
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CONFIG_UART3_RXBUFSIZE=256
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CONFIG_UART0_BAUD=38400
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CONFIG_UART1_BAUD=38400
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CONFIG_UART2_BAUD=38400
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CONFIG_UART3_BAUD=38400
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CONFIG_UART0_BITS=8
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CONFIG_UART1_BITS=8
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CONFIG_UART2_BITS=8
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CONFIG_UART3_BITS=8
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CONFIG_UART0_PARITY=0
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CONFIG_UART1_PARITY=0
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CONFIG_UART2_PARITY=0
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CONFIG_UART3_PARITY=0
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CONFIG_UART0_2STOP=0
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CONFIG_UART1_2STOP=0
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CONFIG_UART2_2STOP=0
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CONFIG_UART3_2STOP=0
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#
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# General build options
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