Merge branch 'master' of https://bitbucket.org/nuttx/arch
This commit is contained in:
Anton D. Kachalov
commit
f10b7ff09a
@ -278,7 +278,8 @@
|
||||
#endif
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||||
|
||||
#ifdef CONFIG_SAMV7_GPIOC_IRQ
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||||
# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
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# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + \
|
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SAM_NGPIOBIRQS)
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||||
# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */
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# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */
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||||
# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */
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@ -317,7 +318,8 @@
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#endif
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#ifdef CONFIG_SAMV7_GPIOD_IRQ
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# define SAM_IRQ_GPIOD_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
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# define SAM_IRQ_GPIOD_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + \
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SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)
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# define SAM_IRQ_PD0 (SAM_IRQ_GPIOD_PINS+0) /* GPIOD, PIN 0 */
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# define SAM_IRQ_PD1 (SAM_IRQ_GPIOD_PINS+1) /* GPIOD, PIN 1 */
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# define SAM_IRQ_PD2 (SAM_IRQ_GPIOD_PINS+2) /* GPIOD, PIN 2 */
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@ -356,7 +358,8 @@
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#endif
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#ifdef CONFIG_SAMV7_GPIOE_IRQ
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# define SAM_IRQ_GPIOE_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
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# define SAM_IRQ_GPIOE_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + \
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SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + SAM_NGPIODIRQS)
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# define SAM_IRQ_PE0 (SAM_IRQ_GPIOE_PINS+0) /* GPIOE, PIN 0 */
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# define SAM_IRQ_PE1 (SAM_IRQ_GPIOE_PINS+1) /* GPIOE, PIN 1 */
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# define SAM_IRQ_PE2 (SAM_IRQ_GPIOE_PINS+2) /* GPIOE, PIN 2 */
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@ -108,7 +108,7 @@ ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),ATOLLIC)
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ifneq ($(CONFIG_WINDOWS_NATIVE),y)
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WINTOOL = y
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endif
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ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -march=armv6-m -mfloat-abi=soft
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ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -mfloat-abi=soft
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endif
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# NuttX buildroot under Linux or Cygwin
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@ -124,7 +124,7 @@ endif
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ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),CODEREDL)
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CROSSDEV ?= arm-none-eabi-
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ARCROSSDEV ?= arm-none-eabi-
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ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -march=armv6-m -mfloat-abi=soft
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ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -mfloat-abi=soft
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endif
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||||
# Code Red RedSuite under Windows
|
||||
@ -135,7 +135,7 @@ ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),CODEREDW)
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ifneq ($(CONFIG_WINDOWS_NATIVE),y)
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WINTOOL = y
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endif
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ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -march=armv6-m -mfloat-abi=soft
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ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -mfloat-abi=soft
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endif
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# CodeSourcery under Linux
|
||||
@ -143,7 +143,7 @@ endif
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ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),CODESOURCERYL)
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CROSSDEV ?= arm-none-eabi-
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ARCROSSDEV ?= arm-none-eabi-
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ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -march=armv6-m -mfloat-abi=soft
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ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -mfloat-abi=soft
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||||
endif
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|
||||
# CodeSourcery under Windows
|
||||
@ -154,7 +154,7 @@ ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),CODESOURCERYW)
|
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ifneq ($(CONFIG_WINDOWS_NATIVE),y)
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WINTOOL = y
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endif
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ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -march=armv6-m -mfloat-abi=soft
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ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -mfloat-abi=soft
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endif
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# devkitARM under Windows
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@ -165,7 +165,7 @@ ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),DEVKITARM)
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ifneq ($(CONFIG_WINDOWS_NATIVE),y)
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WINTOOL = y
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endif
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ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -march=armv6-m -mfloat-abi=soft
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ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -mfloat-abi=soft
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endif
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# Generic GNU EABI toolchain on OS X, Linux or any typical Posix system
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@ -173,7 +173,7 @@ endif
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ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),GNU_EABIL)
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CROSSDEV ?= arm-none-eabi-
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ARCROSSDEV ?= arm-none-eabi-
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ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -march=armv6-m -mfloat-abi=soft
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ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -mfloat-abi=soft
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||||
endif
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ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),GNU_EABIW)
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@ -182,7 +182,7 @@ ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),GNU_EABIW)
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ifneq ($(CONFIG_WINDOWS_NATIVE),y)
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WINTOOL = y
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endif
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -march=armv6-m -mfloat-abi=soft
|
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ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -mfloat-abi=soft
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endif
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||||
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# Individual tools may limit the optimizatin level but, by default, the
|
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|
||||
@ -164,7 +164,7 @@ ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),ATOLLIC)
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CROSSDEV ?= arm-atollic-eabi-
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ARCROSSDEV ?= arm-atollic-eabi-
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MAXOPTIMIZATION ?= -Os
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ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MFLOAT)
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ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MFLOAT)
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ifneq ($(CONFIG_WINDOWS_NATIVE),y)
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WINTOOL = y
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endif
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@ -176,11 +176,11 @@ ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),BUILDROOT)
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ifeq ($(CONFIG_ARMV7M_OABI_TOOLCHAIN),y)
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CROSSDEV ?= arm-nuttx-elf-
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ARCROSSDEV ?= arm-nuttx-elf-
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ARCHCPUFLAGS = $(TOOLCHAIN_MTUNE) $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MFLOAT)
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ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) $(TOOLCHAIN_MFLOAT)
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else
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||||
CROSSDEV ?= arm-nuttx-eabi-
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ARCROSSDEV ?= arm-nuttx-eabi-
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ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MFLOAT)
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ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MFLOAT)
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endif
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MAXOPTIMIZATION ?= -Os
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endif
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@ -191,7 +191,7 @@ ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),CODEREDL)
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CROSSDEV ?= arm-none-eabi-
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ARCROSSDEV ?= arm-none-eabi-
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MAXOPTIMIZATION ?= -Os
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||||
ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MFLOAT)
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ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MFLOAT)
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endif
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||||
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||||
# Code Red RedSuite under Windows
|
||||
@ -200,7 +200,7 @@ ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),CODEREDW)
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||||
CROSSDEV ?= arm-none-eabi-
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ARCROSSDEV ?= arm-none-eabi-
|
||||
MAXOPTIMIZATION ?= -Os
|
||||
ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MFLOAT)
|
||||
ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MFLOAT)
|
||||
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
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WINTOOL = y
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||||
endif
|
||||
@ -212,7 +212,7 @@ ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),CODESOURCERYL)
|
||||
CROSSDEV ?= arm-none-eabi-
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||||
ARCROSSDEV ?= arm-none-eabi-
|
||||
MAXOPTIMIZATION ?= -O2
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||||
ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MFLOAT)
|
||||
ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MFLOAT)
|
||||
endif
|
||||
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||||
# CodeSourcery under Windows
|
||||
@ -221,7 +221,7 @@ ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),CODESOURCERYW)
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||||
CROSSDEV ?= arm-none-eabi-
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ARCROSSDEV ?= arm-none-eabi-
|
||||
MAXOPTIMIZATION ?= -Os
|
||||
ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MFLOAT)
|
||||
ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MFLOAT)
|
||||
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
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WINTOOL = y
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||||
endif
|
||||
@ -244,7 +244,7 @@ ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),GNU_EABIL)
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CROSSDEV ?= arm-none-eabi-
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||||
ARCROSSDEV ?= arm-none-eabi-
|
||||
MAXOPTIMIZATION ?= -Os
|
||||
ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MFLOAT)
|
||||
ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MFLOAT)
|
||||
endif
|
||||
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||||
# Generic GNU EABI toolchain under Windows
|
||||
@ -253,7 +253,7 @@ ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),GNU_EABIW)
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CROSSDEV ?= arm-none-eabi-
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ARCROSSDEV ?= arm-none-eabi-
|
||||
MAXOPTIMIZATION ?= -Os
|
||||
ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MFLOAT)
|
||||
ARCHCPUFLAGS = $(TOOLCHAIN_MCPU) -mthumb $(TOOLCHAIN_MFLOAT)
|
||||
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
|
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WINTOOL = y
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endif
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||||
@ -1183,7 +1183,7 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
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regval = CAN_MCR_MDLC(msg->cm_hdr.ch_dlc) | CAN_MCR_MTCR;
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can_putreg(priv, SAM_CAN_MnCR_OFFSET(mbndx), regval);
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/* If we have not been asked to suppress TX interrupts, then dnable
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/* If we have not been asked to suppress TX interrupts, then enable
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* interrupts from this mailbox now.
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||||
*/
|
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||||
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@ -65,7 +65,7 @@ config ARCH_CHIP_SAMV71Q
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bool
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default n
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select ARCH_CHIP_SAMV71
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select SAMV7_HAVE_CAN1
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select SAMV7_HAVE_MCAN1
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select SAMV7_HAVE_DAC1
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select SAMV7_HAVE_EBI
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select SAMV7_HAVE_HSMCI0
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@ -82,7 +82,7 @@ config ARCH_CHIP_SAMV71N
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||||
bool
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default n
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select ARCH_CHIP_SAMV71
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||||
select SAMV7_HAVE_CAN1
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select SAMV7_HAVE_MCAN1
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select SAMV7_HAVE_DAC1
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select SAMV7_HAVE_HSMCI0
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select SAMV7_HAVE_SPI0
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@ -102,7 +102,11 @@ config ARCH_CHIP_SAMV71J
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||||
# Chip Capabilities
|
||||
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config SAMV7_HAVE_CAN1
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config SAMV7_MCAN
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bool
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default n
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||||
config SAMV7_HAVE_MCAN1
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bool
|
||||
default n
|
||||
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||||
@ -143,10 +147,6 @@ config SAMV7_HAVE_SDRAMC
|
||||
bool
|
||||
default n
|
||||
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||||
config SAMV7_HAVE_SPI
|
||||
bool
|
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default n
|
||||
|
||||
config SAMV7_HAVE_SPI0
|
||||
bool
|
||||
default n
|
||||
@ -187,6 +187,18 @@ config SAMV7_HAVE_USART2
|
||||
bool
|
||||
default n
|
||||
|
||||
config SAMV7_SPI
|
||||
bool
|
||||
default n
|
||||
|
||||
config SAMV7_SPI_MASTER
|
||||
bool
|
||||
default n
|
||||
|
||||
config SAMV7_SPI_SLAVE
|
||||
bool
|
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default n
|
||||
|
||||
# Peripheral Selection
|
||||
|
||||
menu "SAMV7 Peripheral Selection"
|
||||
@ -207,14 +219,18 @@ config SAMV7_AFEC1
|
||||
bool "Analog Front End 1 (AFEC1)"
|
||||
default n
|
||||
|
||||
config SAMV7_CAN0
|
||||
bool "CAN0"
|
||||
config SAMV7_MCAN0
|
||||
bool "CAN controller 0 (MCAN0)"
|
||||
default n
|
||||
select CAN
|
||||
select SAMV7_MCAN
|
||||
|
||||
config SAMV7_CAN1
|
||||
bool "CAN1"
|
||||
config SAMV7_MCAN1
|
||||
bool "CAN controller 1 (MCAN1)"
|
||||
default n
|
||||
depends on SAMV7_HAVE_CAN1
|
||||
depends on SAMV7_HAVE_MCAN1
|
||||
select CAN
|
||||
select SAMV7_MCAN
|
||||
|
||||
config SAMV7_DAC0
|
||||
bool "Digital To Analog Converter 0 (DAC0)"
|
||||
@ -291,14 +307,14 @@ config SAMV7_SPI0
|
||||
bool "Serial Peripheral Interface 0 (SPI0)"
|
||||
default n
|
||||
depends on SAMV7_HAVE_SPI0
|
||||
select SAMV7_HAVE_SPI
|
||||
select SAMV7_SPI
|
||||
select SPI
|
||||
|
||||
config SAMV7_SPI1
|
||||
bool "Serial Peripheral Interface 1 (SPI1)"
|
||||
default n
|
||||
depends on SAMV7_HAVE_SPI1
|
||||
select SAMV7_HAVE_SPI
|
||||
select SAMV7_SPI
|
||||
select SPI
|
||||
|
||||
config SAMV7_SSC0
|
||||
@ -518,8 +534,51 @@ config SAMV7_SDRAMHEAP
|
||||
|
||||
endmenu # SDRAM Configuration
|
||||
|
||||
menu "SAMV7 SPI device driver options"
|
||||
depends on AMV7_SPI0 || SAMV7_SPI1
|
||||
menu "SPI Device Driver Configuration"
|
||||
depends on SAMV7_SPI
|
||||
|
||||
choice
|
||||
prompt "SPI0 Configuration"
|
||||
default SAMV7_SPI0_MASTER
|
||||
depends on SAMV7_SPI0
|
||||
|
||||
config SAMV7_SPI0_MASTER
|
||||
bool "Master"
|
||||
select SAMV7_SPI_MASTER
|
||||
---help---
|
||||
Configure SPI0 as an SPI master driver. Default: Master
|
||||
|
||||
config SAMV7_SPI0_SLAVE
|
||||
bool "Slave"
|
||||
depends on EXPERIMENTAL
|
||||
select SAMV7_SPI_SLAVE
|
||||
---help---
|
||||
Configure SPI0 as an SPI slave driver. Default: Master
|
||||
|
||||
endchoice # SPI0 Configuration
|
||||
|
||||
choice
|
||||
prompt "SPI1 Configuration"
|
||||
default SAMV7_SPI1_MASTER
|
||||
depends on SAMV7_SPI1
|
||||
|
||||
config SAMV7_SPI1_MASTER
|
||||
bool "Master"
|
||||
select SAMV7_SPI_MASTER
|
||||
---help---
|
||||
Configure SPI1 as an SPI master driver. Default: Master
|
||||
|
||||
config SAMV7_SPI1_SLAVE
|
||||
bool "Slave"
|
||||
depends on EXPERIMENTAL
|
||||
select SAMV7_SPI_SLAVE
|
||||
---help---
|
||||
Configure SPI1 as an SPI slave driver. Default: Master
|
||||
|
||||
endchoice # SPI1 Configuration
|
||||
|
||||
if SAMV7_SPI_MASTER
|
||||
comment "SPI Master Configuration"
|
||||
|
||||
config SAMV7_SPI_DMA
|
||||
bool "SPI DMA"
|
||||
@ -547,6 +606,20 @@ config SAMV7_SPI_DMADEBUG
|
||||
registers at key points in the data transfer and then dumps all of
|
||||
the registers at the end of the transfer.
|
||||
|
||||
endif # SAMV7_SPI_MASTER
|
||||
|
||||
if SAMV7_SPI_SLAVE
|
||||
comment "SPI Slave Configuration"
|
||||
|
||||
config SAMV7_SPI_SLAVE_QSIZE
|
||||
int "Output queue size"
|
||||
default 8
|
||||
---help---
|
||||
The number of words that an be retained in the controller driver's
|
||||
output queue.
|
||||
|
||||
endif # SAMV7_SPI_SLAVE
|
||||
|
||||
config SAMV7_SPI_REGDEBUG
|
||||
bool "SPI Register level debug"
|
||||
depends on DEBUG
|
||||
@ -729,7 +802,7 @@ config SAMV7_SSC0_TX_FSLEN
|
||||
default 1
|
||||
range 0 255
|
||||
---help---
|
||||
This setting define the length of the Transmit Frame Sync signal in
|
||||
This setting defines the length of the Transmit Frame Sync signal in
|
||||
units of transmit clock periods. A value of zero disables this
|
||||
feature. In that case the TD line is driven with the default value
|
||||
during the Transmit Frame Sync signal.
|
||||
@ -901,7 +974,7 @@ config SAMV7_SSC1_TX_FSLEN
|
||||
default 1
|
||||
range 0 255
|
||||
---help---
|
||||
This setting define the length of the Transmit Frame Sync signal in
|
||||
This setting defines the length of the Transmit Frame Sync signal in
|
||||
units of transmit clock periods. A value of zero disables this
|
||||
feature. In that case the TD line is driven with the default value
|
||||
during the Transmit Frame Sync signal.
|
||||
@ -1296,3 +1369,671 @@ config SAMV7_USBHS_REGDEBUG
|
||||
depends on DEBUG
|
||||
|
||||
endmenu # USB High Speed Device Controller driver (DCD) options
|
||||
|
||||
if SAMV7_MCAN
|
||||
|
||||
menu "MCAN device driver options"
|
||||
|
||||
choice
|
||||
prompt "MCAN clock source (PCK5)"
|
||||
default SAMV7_MCAN_CLKSRC_MAIN
|
||||
|
||||
config SAMV7_MCAN_CLKSRC_SLOW
|
||||
bool "Slow clock"
|
||||
|
||||
config SAMV7_MCAN_CLKSRC_MAIN
|
||||
bool "Main clock"
|
||||
|
||||
config SAMV7_MCAN_CLKSRC_PLLA
|
||||
bool "PLLA clock"
|
||||
|
||||
config SAMV7_MCAN_CLKSRC_UPLL
|
||||
bool "UPLL clock"
|
||||
|
||||
config SAMV7_MCAN_CLKSRC_MCK
|
||||
bool "Master clock"
|
||||
|
||||
endchoice # MCAN clock source
|
||||
|
||||
config SAMV7_MCAN_CLKSRC_PRESCALER
|
||||
int "MCAN clock prescaler"
|
||||
default 1
|
||||
range 1 256
|
||||
|
||||
menu "MCAN0 device driver options"
|
||||
depends on SAMV7_MCAN0
|
||||
|
||||
choice
|
||||
prompt "MCAN0 mode"
|
||||
default SAMV7_MCAN0_ISO11899_1
|
||||
|
||||
config SAMV7_MCAN0_ISO11899_1
|
||||
bool "ISO11898-1"
|
||||
---help---
|
||||
Enable ISO11898-1 mode
|
||||
|
||||
config SAMV7_MCAN0_FD
|
||||
bool "FD"
|
||||
depends on CAN_FD
|
||||
---help---
|
||||
Enable FD mode
|
||||
|
||||
config SAMV7_MCAN0_FD_BSW
|
||||
bool "FD with fast bit rate switching"
|
||||
depends on CAN_FD
|
||||
---help---
|
||||
Enable FD mode with fast bit rate switching mode.
|
||||
|
||||
endchoice # MCAN0 mode
|
||||
|
||||
config SAMV7_MCAN0_LOOPBACK
|
||||
bool "Enable MCAN0 loopback mode"
|
||||
default n
|
||||
---help---
|
||||
Enable the MCAN0 local loopback mode for testing purposes.
|
||||
|
||||
config SAMV7_MCAN0_BITRATE
|
||||
int "MCAN0 bitrate"
|
||||
default 500000
|
||||
---help---
|
||||
MCAN0 bitrate in bits per second. Required if SAMV7_MCAN0 is defined.
|
||||
|
||||
config SAMV7_MCAN0_PROPSEG
|
||||
int "MCAN0 PropSeg"
|
||||
default 2
|
||||
range 1 63
|
||||
---help---
|
||||
The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
|
||||
|
||||
config SAMV7_MCAN0_PHASESEG1
|
||||
int "MCAN0 PhaseSeg1"
|
||||
default 11
|
||||
range 1 63
|
||||
---help---
|
||||
The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
|
||||
|
||||
config SAMV7_MCAN0_PHASESEG2
|
||||
int "MCAN0 PhaseSeg2"
|
||||
default 11
|
||||
range 1 63
|
||||
---help---
|
||||
The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
|
||||
|
||||
config SAMV7_MCAN0_FSJW
|
||||
int "MCAN0 synchronization jump width"
|
||||
default 4
|
||||
range 1 5
|
||||
---help---
|
||||
The duration of a synchronization jump is Tcan_clk x FSJW.
|
||||
|
||||
config SAMV7_MCAN0_FBITRATE
|
||||
int "MCAN0 fast bitrate"
|
||||
default 2000000
|
||||
---help---
|
||||
MCAN0 bitrate in bits per second. Required if SAMV7_MCAN0 is
|
||||
defined.
|
||||
|
||||
config SAMV7_MCAN0_FPROPSEG
|
||||
int "MCAN0 fast PropSeg"
|
||||
default 2
|
||||
range 1 63
|
||||
---help---
|
||||
The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
|
||||
|
||||
config SAMV7_MCAN0_FPHASESEG1
|
||||
int "MCAN0 fast PhaseSeg1"
|
||||
default 4
|
||||
range 1 63
|
||||
---help---
|
||||
The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
|
||||
|
||||
config SAMV7_MCAN0_FPHASESEG2
|
||||
int "MCAN0 fast PhaseSeg2"
|
||||
default 4
|
||||
range 1 63
|
||||
---help---
|
||||
The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
|
||||
|
||||
config SAMV7_MCAN0_FFSJW
|
||||
int "MCAN0 fast synchronization jump width"
|
||||
default 2
|
||||
range 1 5
|
||||
---help---
|
||||
The duration of a synchronization jump is Tcan_clk x FSJW.
|
||||
|
||||
config SAMV7_MCAN0_NSTDFILTERS
|
||||
int "MCAN0 number of standard filters"
|
||||
default 8
|
||||
range 0 128
|
||||
---help---
|
||||
Number of standard message ID filters.
|
||||
|
||||
config SAMV7_MCAN0_NEXTFILTERS
|
||||
int "MCAN0 number of extended filters"
|
||||
default 8
|
||||
range 0 64
|
||||
---help---
|
||||
Number of extended message ID filters.
|
||||
|
||||
choice
|
||||
prompt "MCAN0 RX FIFO0 element size"
|
||||
default SAMV7_MCAN0_RXFIFO0_8BYTES
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO0_8BYTES
|
||||
bool "8 bytes"
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO0_12BYTES
|
||||
bool "12 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO0_16BYTES
|
||||
bool "16 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO0_20BYTES
|
||||
bool "20 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO0_24BYTES
|
||||
bool "24 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO0_32BYTES
|
||||
bool "32 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO0_48BYTES
|
||||
bool "48 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO0_64BYTES
|
||||
bool "64 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
endchoice # MCAN0 RX buffer element size
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO0_SIZE
|
||||
int "MCAN0 RX FIFO0 size"
|
||||
default 12
|
||||
range 0 64
|
||||
---help---
|
||||
Number of receive FIFO 0 elements. Zero disables FIFO 0.
|
||||
|
||||
choice
|
||||
prompt "MCAN0 RX FIFO1 element size"
|
||||
default SAMV7_MCAN0_RXFIFO1_8BYTES
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO1_8BYTES
|
||||
bool "8 bytes"
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO1_12BYTES
|
||||
bool "12 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO1_16BYTES
|
||||
bool "16 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO1_20BYTES
|
||||
bool "20 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO1_24BYTES
|
||||
bool "24 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO1_32BYTES
|
||||
bool "32 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO1_48BYTES
|
||||
bool "48 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO1_64BYTES
|
||||
bool "64 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
endchoice # MCAN0 RX buffer element size
|
||||
|
||||
config SAMV7_MCAN0_RXFIFO1_SIZE
|
||||
int "MCAN0 RX FIFO1 size"
|
||||
default 0
|
||||
range 0 64
|
||||
---help---
|
||||
Number of receive FIFO 1 elements for MCAN0. Zero disables FIFO 1.
|
||||
|
||||
choice
|
||||
prompt "MCAN0 RX buffer element size"
|
||||
default SAMV7_MCAN0_RXBUFFER_8BYTES
|
||||
|
||||
config SAMV7_MCAN0_RXBUFFER_8BYTES
|
||||
bool "8 bytes"
|
||||
|
||||
config SAMV7_MCAN0_RXBUFFER_12BYTES
|
||||
bool "12 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXBUFFER_16BYTES
|
||||
bool "16 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXBUFFER_20BYTES
|
||||
bool "20 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXBUFFER_24BYTES
|
||||
bool "24 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXBUFFER_32BYTES
|
||||
bool "32 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXBUFFER_48BYTES
|
||||
bool "48 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_RXBUFFER_64BYTES
|
||||
bool "64 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
endchoice # MCAN0 RX buffer element size
|
||||
|
||||
config SAMV7_MCAN0_DEDICATED_RXBUFFER_SIZE
|
||||
int "MCAN0 dedicated RX buffer size"
|
||||
default 0
|
||||
range 0 64
|
||||
depends on EXPERIMENTAL
|
||||
---help---
|
||||
Number of dedicated RX buffer elements for MCAN0.
|
||||
|
||||
NOTE: Dedicated RX buffers are not used in the current MCAN design.
|
||||
|
||||
choice
|
||||
prompt "MCAN0 TX buffer element size"
|
||||
default SAMV7_MCAN0_TXBUFFER_8BYTES
|
||||
|
||||
config SAMV7_MCAN0_TXBUFFER_8BYTES
|
||||
bool "8 bytes"
|
||||
|
||||
config SAMV7_MCAN0_TXBUFFER_12BYTES
|
||||
bool "12 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_TXBUFFER_16BYTES
|
||||
bool "16 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_TXBUFFER_20BYTES
|
||||
bool "20 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_TXBUFFER_24BYTES
|
||||
bool "24 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_TXBUFFER_32BYTES
|
||||
bool "32 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_TXBUFFER_48BYTES
|
||||
bool "48 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
config SAMV7_MCAN0_TXBUFFER_64BYTES
|
||||
bool "64 bytes"
|
||||
depends on SAMV7_MCAN0_FD
|
||||
|
||||
endchoice # MCAN0 TX buffer element size
|
||||
|
||||
config SAMV7_MCAN0_DEDICATED_TXBUFFER_SIZE
|
||||
int "MCAN0 dedicated TX buffer size"
|
||||
default 0
|
||||
range 0 32
|
||||
depends on EXPERIMENTAL
|
||||
---help---
|
||||
Number of dedicated TX buffer elements for MCAN0.
|
||||
|
||||
NOTE: Dedicated TX buffers are not used in the current MCAN design.
|
||||
|
||||
config SAMV7_MCAN0_TXFIFOQ_SIZE
|
||||
int "MCAN0 TX FIFO queue size"
|
||||
default 4
|
||||
range 0 32
|
||||
---help---
|
||||
Number of dedicated TX buffer elements for MCAN0.
|
||||
|
||||
config SAMV7_MCAN0_TXEVENTFIFO_SIZE
|
||||
int "MCAN0 TX event FIFO size"
|
||||
default 0
|
||||
range 0 32
|
||||
---help---
|
||||
Number of TX event FIFO elements for MCAN0. Zero disables TX event FIFO.
|
||||
|
||||
endmenu # MCAN0 device driver options
|
||||
|
||||
menu "MCAN1 device driver options"
|
||||
depends on SAMV7_MCAN1
|
||||
|
||||
choice
|
||||
prompt "MCAN1 mode"
|
||||
default SAMV7_MCAN1_ISO11899_1
|
||||
|
||||
config SAMV7_MCAN1_ISO11899_1
|
||||
bool "ISO11898-1"
|
||||
---help---
|
||||
Enable ISO11898-1 mode
|
||||
|
||||
config SAMV7_MCAN1_FD
|
||||
bool "FD"
|
||||
depends on CAN_FD
|
||||
---help---
|
||||
Enable FD mode
|
||||
|
||||
config SAMV7_MCAN1_FD_BSW
|
||||
bool "FD with fast bit rate switching"
|
||||
depends on CAN_FD
|
||||
---help---
|
||||
Enable FD mode with fast bit rate switching mode.
|
||||
|
||||
endchoice # MCAN0 mode
|
||||
|
||||
config SAMV7_MCAN1_LOOPBACK
|
||||
bool "Enable MCAN1 loopback mode"
|
||||
default n
|
||||
---help---
|
||||
Enable the MCAN1 local loopback mode for testing purposes.
|
||||
|
||||
config SAMV7_MCAN1_BITRATE
|
||||
int "MCAN1 bitrate"
|
||||
default 500000
|
||||
---help---
|
||||
MCAN1 bitrate in bits per second. Required if SAMV7_MCAN1 is
|
||||
defined.
|
||||
|
||||
config SAMV7_MCAN1_PROPSEG
|
||||
int "MCAN1 PropSeg"
|
||||
default 2
|
||||
range 1 63
|
||||
---help---
|
||||
The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
|
||||
|
||||
config SAMV7_MCAN1_PHASESEG1
|
||||
int "MCAN1 PhaseSeg1"
|
||||
default 11
|
||||
range 1 63
|
||||
---help---
|
||||
The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
|
||||
|
||||
config SAMV7_MCAN1_PHASESEG2
|
||||
int "MCAN1 PhaseSeg2"
|
||||
default 11
|
||||
range 1 63
|
||||
---help---
|
||||
The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
|
||||
|
||||
config SAMV7_MCAN1_FSJW
|
||||
int "MCAN1 synchronization jump width"
|
||||
default 4
|
||||
range 1 5
|
||||
---help---
|
||||
The duration of a synchronization jump is Tcan_clk x FSJW.
|
||||
|
||||
config SAMV7_MCAN1_FBITRATE
|
||||
int "MCAN1 fast bitrate"
|
||||
default 2000000
|
||||
---help---
|
||||
MCAN1 bitrate in bits per second. Required if SAMV7_MCAN1 is
|
||||
defined.
|
||||
|
||||
config SAMV7_MCAN1_FPROPSEG
|
||||
int "MCAN1 fast PropSeg"
|
||||
default 2
|
||||
range 1 63
|
||||
---help---
|
||||
The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
|
||||
|
||||
config SAMV7_MCAN1_FPHASESEG1
|
||||
int "MCAN1 fast PhaseSeg1"
|
||||
default 4
|
||||
range 1 63
|
||||
---help---
|
||||
The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
|
||||
|
||||
config SAMV7_MCAN1_FPHASESEG2
|
||||
int "MCAN1 fast PhaseSeg2"
|
||||
default 4
|
||||
range 1 63
|
||||
---help---
|
||||
The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
|
||||
|
||||
config SAMV7_MCAN1_FFSJW
|
||||
int "MCAN1 fast synchronization jump width"
|
||||
default 2
|
||||
range 1 5
|
||||
---help---
|
||||
The duration of a synchronization jump is Tcan_clk x FSJW.
|
||||
|
||||
config SAMV7_MCAN1_NSTDFILTERS
|
||||
int "MCAN1 number of standard filters"
|
||||
default 8
|
||||
range 0 128
|
||||
---help---
|
||||
Number of standard message ID filters.
|
||||
|
||||
config SAMV7_MCAN1_NEXTFILTERS
|
||||
int "MCAN1 number of extended filters"
|
||||
default 8
|
||||
range 0 64
|
||||
---help---
|
||||
Number of extended message ID filters.
|
||||
|
||||
choice
|
||||
prompt "MCAN1 RX FIFO0 element size"
|
||||
default SAMV7_MCAN1_RXFIFO0_8BYTES
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO0_8BYTES
|
||||
bool "8 bytes"
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO0_12BYTES
|
||||
bool "12 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO0_16BYTES
|
||||
bool "16 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO0_20BYTES
|
||||
bool "20 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO0_24BYTES
|
||||
bool "24 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO0_32BYTES
|
||||
bool "32 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO0_48BYTES
|
||||
bool "48 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO0_64BYTES
|
||||
bool "64 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
endchoice # MCAN1 RX buffer element size
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO0_SIZE
|
||||
int "MCAN1 RX FIFO0 size"
|
||||
default 0
|
||||
range 0 64
|
||||
---help---
|
||||
Number of receive FIFO 0 elements. Zero disables FIFO 0.
|
||||
|
||||
choice
|
||||
prompt "MCAN1 RX FIFO1 element size"
|
||||
default SAMV7_MCAN1_RXFIFO1_8BYTES
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO1_8BYTES
|
||||
bool "8 bytes"
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO1_12BYTES
|
||||
bool "12 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO1_16BYTES
|
||||
bool "16 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO1_20BYTES
|
||||
bool "20 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO1_24BYTES
|
||||
bool "24 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO1_32BYTES
|
||||
bool "32 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO1_48BYTES
|
||||
bool "48 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO1_64BYTES
|
||||
bool "64 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
endchoice # MCAN1 RX buffer element size
|
||||
|
||||
config SAMV7_MCAN1_RXFIFO1_SIZE
|
||||
int "MCAN1 RX FIFO1 size"
|
||||
default 0
|
||||
range 0 64
|
||||
---help---
|
||||
Number of receive FIFO 1 elements for MCAN1. Zero disables FIFO 1.
|
||||
|
||||
choice
|
||||
prompt "MCAN1 RX buffer element size"
|
||||
default SAMV7_MCAN1_RXBUFFER_8BYTES
|
||||
|
||||
config SAMV7_MCAN1_RXBUFFER_8BYTES
|
||||
bool "8 bytes"
|
||||
|
||||
config SAMV7_MCAN1_RXBUFFER_12BYTES
|
||||
bool "12 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXBUFFER_16BYTES
|
||||
bool "16 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXBUFFER_20BYTES
|
||||
bool "20 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXBUFFER_24BYTES
|
||||
bool "24 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXBUFFER_32BYTES
|
||||
bool "32 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXBUFFER_48BYTES
|
||||
bool "48 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_RXBUFFER_64BYTES
|
||||
bool "64 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
endchoice # MCAN1 RX buffer element size
|
||||
|
||||
config SAMV7_MCAN1_DEDICATED_RXBUFFER_SIZE
|
||||
int "MCAN1 dedicated RX buffer size"
|
||||
default 0
|
||||
range 0 64
|
||||
depends on EXPERIMENTAL
|
||||
---help---
|
||||
Number of dedicated RX buffer elements for MCAN1.
|
||||
|
||||
NOTE: Dedicated RX buffers are not used in the current MCAN design.
|
||||
|
||||
choice
|
||||
prompt "MCAN1 TX buffer element size"
|
||||
default SAMV7_MCAN1_TXBUFFER_8BYTES
|
||||
|
||||
config SAMV7_MCAN1_TXBUFFER_8BYTES
|
||||
bool "8 bytes"
|
||||
|
||||
config SAMV7_MCAN1_TXBUFFER_12BYTES
|
||||
bool "12 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_TXBUFFER_16BYTES
|
||||
bool "16 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_TXBUFFER_20BYTES
|
||||
bool "20 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_TXBUFFER_24BYTES
|
||||
bool "24 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_TXBUFFER_32BYTES
|
||||
bool "32 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_TXBUFFER_48BYTES
|
||||
bool "48 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
config SAMV7_MCAN1_TXBUFFER_64BYTES
|
||||
bool "64 bytes"
|
||||
depends on SAMV7_MCAN1_FD
|
||||
|
||||
endchoice # MCAN1 TX buffer element size
|
||||
|
||||
config SAMV7_MCAN1_TXEVENTFIFO_SIZE
|
||||
int "MCAN1 TX event FIFO size"
|
||||
default 0
|
||||
range 0 32
|
||||
---help---
|
||||
Number of TX event FIFO elements for MCAN1. Zero disables TX event FIFO.
|
||||
|
||||
config SAMV7_MCAN1_DEDICATED_TXBUFFER_SIZE
|
||||
int "MCAN1 dedicated TX buffer size"
|
||||
default 0
|
||||
range 0 32
|
||||
depends on EXPERIMENTAL
|
||||
---help---
|
||||
Number of dedicated TX buffer elements for MCAN1.
|
||||
|
||||
NOTE: Dedicated TX buffers are not used in the current MCAN design.
|
||||
|
||||
config SAMV7_MCAN1_TXFIFOQ_SIZE
|
||||
int "MCAN1 dedicated TX FIFO queue"
|
||||
default 4
|
||||
range 0 32
|
||||
---help---
|
||||
Number of dedicated TX buffer elements for MCAN1.
|
||||
|
||||
endmenu # MCAN1 device driver options
|
||||
|
||||
config SAMV7_MCAN_REGDEBUG
|
||||
bool "CAN Register level debug"
|
||||
depends on DEBUG
|
||||
default n
|
||||
---help---
|
||||
Output detailed register-level CAN device debug information.
|
||||
Requires also DEBUG.
|
||||
|
||||
endmenu # CAN device driver options
|
||||
endif # SAMV7_MCAN
|
||||
|
||||
@ -124,12 +124,14 @@ ifeq ($(CONFIG_SAMV7_XDMAC),y)
|
||||
CHIP_CSRCS += sam_xdmac.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SAMV7_SPI0),y)
|
||||
CHIP_CSRCS += sam_spi.c
|
||||
else ifeq ($(CONFIG_SAMV7_SPI1),y)
|
||||
ifeq ($(CONFIG_SAMV7_SPI_MASTER),y)
|
||||
CHIP_CSRCS += sam_spi.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SAMV7_SPI_SLAVE),y)
|
||||
CHIP_CSRCS += sam_spi_slave.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SAMV7_TWIHS0),y)
|
||||
CHIP_CSRCS += sam_twihs.c
|
||||
else ifeq ($(CONFIG_SAMV7_TWIHS1),y)
|
||||
@ -150,6 +152,10 @@ ifeq ($(CONFIG_SAMV7_EMAC),y)
|
||||
CHIP_CSRCS += sam_emac.c sam_ethernet.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SAMV7_MCAN),y)
|
||||
CHIP_CSRCS += sam_mcan.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SAMV7_USBDEVHS),y)
|
||||
CHIP_CSRCS += sam_usbdevhs.c
|
||||
endif
|
||||
|
||||
@ -36,8 +36,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMAC_H
|
||||
#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMAC_H
|
||||
#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_EMAC_H
|
||||
#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_EMAC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@ -1043,4 +1043,4 @@ struct emac_txdesc_s
|
||||
};
|
||||
|
||||
#endif /* SAMV7_NEMAC > 0 */
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMAC_H */
|
||||
#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_EMAC_H */
|
||||
|
||||
@ -258,6 +258,7 @@
|
||||
|
||||
/* CAN0 Configuration Register */
|
||||
|
||||
#define MATRIX_CAN0_RESERVED 0x000001ff /* Bits 0-9: Reserved */
|
||||
#define MATRIX_CAN0_CAN0DMABA_MASK 0xffff0000 /* Bits 16-31: CAN0 DMA Base Address */
|
||||
|
||||
/* System I/O and CAN1 Configuration Register */
|
||||
@ -268,7 +269,7 @@
|
||||
# define MATRIX_CCFG_SYSIO_SYSIO6 (1 << 6) /* Bit 6: PB6 or TMS/SWDIO Assignment */
|
||||
# define MATRIX_CCFG_SYSIO_SYSIO7 (1 << 7) /* Bit 7: PB7 or TCK/SWCLK Assignment */
|
||||
# define MATRIX_CCFG_SYSIO_SYSIO12 (1 << 12) /* Bit 12: PB12 or ERASE Assignment */
|
||||
#define MATRIX_CAN0_CAN1DMABA_MASK 0xffff0000 /* Bits 16-31: CAN1 DMA Base Address */
|
||||
#define MATRIX_CCFG_CAN1DMABA_MASK 0xffff0000 /* Bits 16-31: CAN1 DMA Base Address */
|
||||
|
||||
/* SMC Chip Select NAND Flash Assignment Register */
|
||||
|
||||
|
||||
@ -67,7 +67,7 @@
|
||||
#define SAM_MCAN_ECR_OFFSET 0x0040 /* Error Counter Register */
|
||||
#define SAM_MCAN_PSR_OFFSET 0x0044 /* Protocol Status Register */
|
||||
/* 0x0048-0x004c Reserved */
|
||||
#define SAM_MCAN_IR_OFFSET 0x0050 /* Interrupt Register*/
|
||||
#define SAM_MCAN_IR_OFFSET 0x0050 /* Interrupt Register*/
|
||||
#define SAM_MCAN_IE_OFFSET 0x0054 /* Interrupt Enable Register */
|
||||
#define SAM_MCAN_ILS_OFFSET 0x0058 /* Interrupt Line Select Register */
|
||||
#define SAM_MCAN_ILE_OFFSET 0x005c /* Interrupt Line Enable Register */
|
||||
@ -214,7 +214,7 @@
|
||||
#define MCAN_FBTP_FBRP_SHIFT (16) /* Bits 16-20: Fast Baud Rate Prescaler */
|
||||
#define MCAN_FBTP_FBRP_MASK (31 << MCAN_FBTP_FBRP_SHIFT)
|
||||
# define MCAN_FBTP_FBRP(n) ((uint32_t)(n) << MCAN_FBTP_FBRP_SHIFT)
|
||||
#define MCAN_FBTP_TDCO (1 << 23) /* Bit: 23: Transceiver Delay Compensation */
|
||||
#define MCAN_FBTP_TDC (1 << 23) /* Bit: 23: Transceiver Delay Compensation */
|
||||
#define MCAN_FBTP_TDCO_SHIFT (24) /* Bits 24-28: Transceiver Delay Compensation Offset */
|
||||
#define MCAN_FBTP_TDCO_MASK (31 << MCAN_FBTP_TDC_SHIFT)
|
||||
# define MCAN_FBTP_TDCO(n) ((uint32_t)(n) << MCAN_FBTP_TDC_SHIFT)
|
||||
@ -360,7 +360,7 @@
|
||||
|
||||
/* Common bit definitions for Interrupt Register, Interrupt Enable Register, Interrupt
|
||||
* Line Select Register
|
||||
*/
|
||||
*/
|
||||
|
||||
#define MCAN_INT_RF0N (1 << 0) /* Bit 0: Receive FIFO 0 New Message */
|
||||
#define MCAN_INT_RF0W (1 << 1) /* Bit 1: Receive FIFO 0 Watermark Reached */
|
||||
@ -370,7 +370,7 @@
|
||||
#define MCAN_INT_RF1W (1 << 5) /* Bit 5: Receive FIFO 1 Watermark Reached */
|
||||
#define MCAN_INT_RF1F (1 << 6) /* Bit 6: Receive FIFO 1 Full */
|
||||
#define MCAN_INT_RF1L (1 << 7) /* Bit 7: Receive FIFO 1 Message Lost */
|
||||
#define MCAN_INT_HPM (1 << 8) /* Bit 8: High Priority Message */
|
||||
#define MCAN_INT_HPM (1 << 8) /* Bit 8: High Priority Message Received */
|
||||
#define MCAN_INT_TC (1 << 9) /* Bit 9: Transmission Completed */
|
||||
#define MCAN_INT_TCF (1 << 10) /* Bit 10: Transmission Cancellation Finished */
|
||||
#define MCAN_INT_TFE (1 << 11) /* Bit 11: Tx FIFO Empty */
|
||||
@ -387,12 +387,14 @@
|
||||
#define MCAN_INT_EW (1 << 24) /* Bit 24: Warning Status */
|
||||
#define MCAN_INT_BO (1 << 25) /* Bit 25: Bus_Off Status */
|
||||
#define MCAN_INT_WDI (1 << 26) /* Bit 26: Watchdog Interrupt */
|
||||
#define MCAN_INT_CRCE (1 << 27) /* Bit 27: CRC Error */
|
||||
#define MCAN_INT_CRCE (1 << 27) /* Bit 27: Receive CRC Error */
|
||||
#define MCAN_INT_BE (1 << 28) /* Bit 28: Bit Error */
|
||||
#define MCAN_INT_ACKE (1 << 29) /* Bit 29: Acknowledge Error */
|
||||
#define MCAN_INT_FOE (1 << 30) /* Bit 30: Format Error */
|
||||
#define MCAN_INT_STE (1 << 31) /* Bit 31: Stuff Error */
|
||||
|
||||
#define MCAN_INT_ALL (0xffcfffff)
|
||||
|
||||
/* Interrupt Line Enable Register */
|
||||
|
||||
#define MCAN_ILE_EINT0 (1 << 0) /* Bit 0: Enable Interrupt Line 0 */
|
||||
@ -442,10 +444,10 @@
|
||||
# define MCAN_HPMS_BIDX(n) ((uint32_t)(n) << MCAN_HPMS_BIDX_SHIFT)
|
||||
#define MCAN_HPMS_MSI_SHIFT (6) /* Bits 6-7: Message Storage Indicator */
|
||||
#define MCAN_HPMS_MSI_MASK (3 << MCAN_HPMS_MSI_SHIFT)
|
||||
# define MCAN_HPMS_MSI_ NOFIFO (0 << MCAN_HPMS_MSI_SHIFT) /* No FIFO selected. */
|
||||
# define MCAN_HPMS_MSI_ LOST (1 << MCAN_HPMS_MSI_SHIFT) /* FIFO message. */
|
||||
# define MCAN_HPMS_MSI_ FIFO0 (2 << MCAN_HPMS_MSI_SHIFT) /* Message stored in FIFO 0. */
|
||||
# define MCAN_HPMS_MSI_ FIFO1 (3 << MCAN_HPMS_MSI_SHIFT) /* Message stored in FIFO 1. */
|
||||
# define MCAN_HPMS_MSI_NOFIFO (0 << MCAN_HPMS_MSI_SHIFT) /* No FIFO selected. */
|
||||
# define MCAN_HPMS_MSI_LOST (1 << MCAN_HPMS_MSI_SHIFT) /* FIFO message. */
|
||||
# define MCAN_HPMS_MSI_FIFO0 (2 << MCAN_HPMS_MSI_SHIFT) /* Message stored in FIFO 0. */
|
||||
# define MCAN_HPMS_MSI_FIFO1 (3 << MCAN_HPMS_MSI_SHIFT) /* Message stored in FIFO 1. */
|
||||
#define MCAN_HPMS_FIDX_SHIFT (8) /* Bits 8-14: Filter Index */
|
||||
#define MCAN_HPMS_FIDX_MASK (0x7f << MCAN_HPMS_FIDX_SHIFT)
|
||||
# define MCAN_HPMS_FIDX(n) ((uint32_t)(n) << MCAN_HPMS_FIDX_SHIFT)
|
||||
@ -535,6 +537,7 @@
|
||||
|
||||
#define MCAN_RXESC_F0DS_SHIFT (0) /* Bits 0-2: Receive FIFO 0 Data Field Size */
|
||||
#define MCAN_RXESC_F0DS_MASK (7 << MCAN_RXESC_F0DS_SHIFT)
|
||||
# define MCAN_RXESC_F0DS(n) ((uint32_t)(n) << MCAN_RXESC_F0DS_SHIFT)
|
||||
# define MCAN_RXESC_F0DS_8B (0 << MCAN_RXESC_F0DS_SHIFT) /* 8-byte data field */
|
||||
# define MCAN_RXESC_F0DS_12B (1 << MCAN_RXESC_F0DS_SHIFT) /* 12-byte data field */
|
||||
# define MCAN_RXESC_F0DS_16B (2 << MCAN_RXESC_F0DS_SHIFT) /* 16-byte data field */
|
||||
@ -545,6 +548,7 @@
|
||||
# define MCAN_RXESC_F0DS_64B (7 << MCAN_RXESC_F0DS_SHIFT) /* 64-byte data field */
|
||||
#define MCAN_RXESC_F1DS_SHIFT (4) /* Bits 4-6: Receive FIFO 1 Data Field Size */
|
||||
#define MCAN_RXESC_F1DS_MASK (7 << MCAN_RXESC_F1DS_SHIFT)
|
||||
# define MCAN_RXESC_F1DS(n) ((uint32_t)(n) << MCAN_RXESC_F1DS_SHIFT)
|
||||
# define MCAN_RXESC_F1DS_8B (0 << MCAN_RXESC_F1DS_SHIFT) /* 8-byte data field */
|
||||
# define MCAN_RXESC_F1DS_12B (1 << MCAN_RXESC_F1DS_SHIFT) /* 12-byte data field */
|
||||
# define MCAN_RXESC_F1DS_16B (2 << MCAN_RXESC_F1DS_SHIFT) /* 16-byte data field */
|
||||
@ -555,6 +559,7 @@
|
||||
# define MCAN_RXESC_F1DS_64B (7 << MCAN_RXESC_F1DS_SHIFT) /* 64-byte data field */
|
||||
#define MCAN_RXESC_RBDS_SHIFT (8) /* Bits 8-10: Receive Buffer Data Field Size */
|
||||
#define MCAN_RXESC_RBDS_MASK (7 << MCAN_RXESC_RBDS_SHIFT)
|
||||
# define MCAN_RXESC_RBDS(n) ((uint32_t)(n) << MCAN_RXESC_RBDS_SHIFT)
|
||||
# define MCAN_RXESC_RBDS_8B (0 << MCAN_RXESC_RBDS_SHIFT) /* 8-byte data field */
|
||||
# define MCAN_RXESC_RBDS_12B (1 << MCAN_RXESC_RBDS_SHIFT) /* 12-byte data field */
|
||||
# define MCAN_RXESC_RBDS_16B (2 << MCAN_RXESC_RBDS_SHIFT) /* 16-byte data field */
|
||||
@ -594,6 +599,7 @@
|
||||
|
||||
#define MCAN_TXESC_TBDS_SHIFT (0) /* Bits 0-2: Tx Buffer Data Field Size */
|
||||
#define MCAN_TXESC_TBDS_MASK (7 << MCAN_TXESC_TBDS_SHIFT)
|
||||
# define MCAN_TXESC_TBDS(n) ((uint32_t)(n) << MCAN_TXESC_TBDS_SHIFT)
|
||||
# define MCAN_TXESC_TBDS_8B (0 << MCAN_TXESC_TBDS_SHIFT) /* 8-byte data field */
|
||||
# define MCAN_TXESC_TBDS_12B (1 << MCAN_TXESC_TBDS_SHIFT) /* 12-byte data field */
|
||||
# define MCAN_TXESC_TBDS_16B (2 << MCAN_TXESC_TBDS_SHIFT) /* 16-byte data field */
|
||||
@ -661,6 +667,137 @@
|
||||
|
||||
#define MCAN_TXEFA_MASK 0x0000001f /* Event fifo acknowledge index mask */
|
||||
|
||||
/* Message RAM Definitions **************************************************************/
|
||||
/* Common Buffer and FIFO element bit definitions:
|
||||
*
|
||||
* --------------- ------------------- --------------------------------
|
||||
* RESOURCE R0 R1
|
||||
* --------------- ------------------- --------------------------------
|
||||
* RX Buffer: ESI, XTD, RTR, ID, ANMF, FIDX, EDL, BRS, DLC, RXTS
|
||||
* RX FIFO: ESI, XTD, RTR, ID, ANMF, FIDX, EDL, BRS, DLC, RXTS
|
||||
* TX buffer: XTD, RTR, ID, MM, EFC, DLC
|
||||
* TX Event FIFO: ESI, XTD, RTR, ID, MM, ET, EDL, BRS, DLC, TXTS
|
||||
* --------------- ------------------- --------------------------------
|
||||
*/
|
||||
|
||||
/* Common */
|
||||
|
||||
#define BUFFER_R0_EXTID_SHIFT (0) /* Bits 0-28: Extended identifer */
|
||||
#define BUFFER_R0_EXTID_MASK (0x1fffffff << BUFFER_R0_EXTID_SHIFT)
|
||||
# define BUFFER_R0_EXTID(n) ((uint32_t)(n) << BUFFER_R0_EXTID_SHIFT)
|
||||
#define BUFFER_R0_STDID_SHIFT (18) /* Bits 18-28: Standard idendifier */
|
||||
#define BUFFER_R0_STDID_MASK (0x7ff << BUFFER_R0_STDID_SHIFT)
|
||||
# define BUFFER_R0_STDID(n) ((uint32_t)(n) << BUFFER_R0_STDID_SHIFT)
|
||||
#define BUFFER_R0_RTR (1 << 29) /* Bit 29: Remote Transmission Request */
|
||||
#define BUFFER_R0_XTD (1 << 30) /* Bit 30: Extended Identifier */
|
||||
#define BUFFER_R0_ESI (1 << 31) /* Bit 31: Error State Indicator */
|
||||
|
||||
/* Common */
|
||||
|
||||
#define BUFFER_R1_DLC_SHIFT (16) /* Bits 16-19: Date length code */
|
||||
#define BUFFER_R1_DLC_MASK (15 << BUFFER_R1_DLC_SHIFT)
|
||||
# define BUFFER_R1_DLC(n) ((uint32_t)(n) << BUFFER_R1_DLC_SHIFT)
|
||||
#define BUFFER_R1_BRS (1 << 20) /* Bit 20: Bit Rate Switch */
|
||||
#define BUFFER_R1_EDL (1 << 21) /* Bit 21: Extended Data Length */
|
||||
|
||||
/* RX buffer/RX FIFOs */
|
||||
|
||||
#define BUFFER_R1_RXTS_SHIFT (0) /* Bits 0-15: RX Timestamp */
|
||||
#define BUFFER_R1_RXTS_MASK (0xffff << BUFFER_R1_RXTS_SHIFT)
|
||||
# define BUFFER_R1_RXTS(n) ((uint32_t)(n) << BUFFER_R1_RXTS_SHIFT)
|
||||
#define BUFFER_R1_FIDX_SHIFT (24) /* Bits 24-30: Filter index */
|
||||
#define BUFFER_R1_FIDX_MASK (0x7f << BUFFER_R1_FIDX_SHIFT)
|
||||
# define BUFFER_R1_FIDX(n) ((uint32_t)(n) << BUFFER_R1_FIDX_SHIFT)
|
||||
#define BUFFER_R1_ANMF (1 << 31) /* Bit 31: Accepted Non-matching Frame */
|
||||
|
||||
/* TX buffer/TX Event FIFO */
|
||||
|
||||
#define BUFFER_R1_MM_SHIFT (24) /* Bits 24-31: Message Marker */
|
||||
#define BUFFER_R1_MM_MASK (0xffff << BUFFER_R1_MM_SHIFT)
|
||||
# define BUFFER_R1_MM(n) ((uint32_t)(n) << BUFFER_R1_MM_SHIFT)
|
||||
|
||||
/* TX buffer */
|
||||
|
||||
#define BUFFER_R1_EFC (1 << 23) /* Bit 23: Event FIFO Control */
|
||||
|
||||
/* TX Event FIFO */
|
||||
|
||||
#define BUFFER_R1_TXTS_SHIFT (0) /* Bits 0-15: TX Timestamp */
|
||||
#define BUFFER_R1_TXTS_MASK (0xffff << BUFFER_R1_TXTS_SHIFT)
|
||||
# define BUFFER_R1_TXTS(n) ((uint32_t)(n) << BUFFER_R1_TXTS_SHIFT)
|
||||
#define BUFFER_R1_ET_SHIFT (22) /* Bits 22-23: Event Type */
|
||||
#define BUFFER_R1_ET_MASK (15 << BUFFER_R1_ET_SHIFT)
|
||||
# define BUFFER_R1_ET_TXEVENT (1 << BUFFER_R1_ET_SHIFT) /* Tx event */
|
||||
# define BUFFER_R1_ET_TXCANCEL (2 << BUFFER_R1_ET_SHIFT) /* Transmission despite cancellation */
|
||||
|
||||
/* Standard Message ID Filter Element */
|
||||
|
||||
#define STDFILTER_S0_SFID2_SHIFT (0) /* Bits 0-10: Standard Filter ID 2 */
|
||||
#define STDFILTER_S0_SFID2_MASK (0x3ff << STDFILTER_S0_SFID2_SHIFT)
|
||||
# define STDFILTER_S0_SFID2(n) ((uint32_t)(n) << STDFILTER_S0_SFID2_SHIFT)
|
||||
#define STDFILTER_S0_BUFFER_SHIFT (0) /* Bits 0-5: RX buffer start address */
|
||||
#define STDFILTER_S0_BUFFER_MASK (0x3f << STDFILTER_S0_BUFFER_SHIFT)
|
||||
# define STDFILTER_S0_BUFFER(n) ((uint32_t)(n) << STDFILTER_S0_BUFFER_SHIFT)
|
||||
#define STDFILTER_S0_ACTION_SHIFT (9) /* Bits 9-10: Action taken */
|
||||
#define STDFILTER_S0_ACTION_MASK (3 << STDFILTER_S0_ACTION_SHIFT)
|
||||
# define STDFILTER_S0_RXBUFFER (0 << STDFILTER_S0_ACTION_SHIFT) /* Store message in a Rx buffer */
|
||||
# define STDFILTER_S0_DEBUGA (1 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message A */
|
||||
# define STDFILTER_S0_DEBUGB (2 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message B */
|
||||
# define STDFILTER_S0_DEBUGC (3 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message C */
|
||||
#define STDFILTER_S0_SFID1_SHIFT (16) /* Bits 16-26: Standard Filter ID 2 */
|
||||
#define STDFILTER_S0_SFID1_MASK (0x3ff << STDFILTER_S0_SFID1_SHIFT)
|
||||
# define STDFILTER_S0_SFID1(n) ((uint32_t)(n) << STDFILTER_S0_SFID1_SHIFT)
|
||||
#define STDFILTER_S0_SFEC_SHIFT (17) /* Bits 27-29: Standard Filter Element Configuration */
|
||||
#define STDFILTER_S0_SFEC_MASK (7 << STDFILTER_S0_SFEC_SHIFT)
|
||||
# define STDFILTER_S0_SFEC_DISABLE (0 << STDFILTER_S0_SFEC_SHIFT) /* Disable filter element */
|
||||
# define STDFILTER_S0_SFEC_FIFO0 (1 << STDFILTER_S0_SFEC_SHIFT) /* Store in Rx FIFO 0 on match */
|
||||
# define STDFILTER_S0_SFEC_FIFO1 (2 << STDFILTER_S0_SFEC_SHIFT) /* Store in Rx FIFO 1 on match */
|
||||
# define STDFILTER_S0_SFEC_REJECT (3 << STDFILTER_S0_SFEC_SHIFT) /* Reject ID on match */
|
||||
# define STDFILTER_S0_SFEC_PRIORITY (4 << STDFILTER_S0_SFEC_SHIFT) /* Set priority ion match */
|
||||
# define STDFILTER_S0_SFEC_PRIOFIFO0 (5 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 0 on match */
|
||||
# define STDFILTER_S0_SFEC_PRIOFIFO1 (6 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 1 on match */
|
||||
# define STDFILTER_S0_SFEC_BUFFER (7 << STDFILTER_S0_SFEC_SHIFT) /* Store into Rx Buffer or as debug message */
|
||||
#define STDFILTER_S0_SFT_SHIFT (30) /* Bits 30-31: Standard Filter Type */
|
||||
#define STDFILTER_S0_SFT_MASK (3 << STDFILTER_S0_SFT_SHIFT)
|
||||
# define STDFILTER_S0_SFT_RANGE (0 << STDFILTER_S0_SFT_SHIFT) /* Range filter from SF1ID to SF2ID */
|
||||
# define STDFILTER_S0_SFT_DUAL (1 << STDFILTER_S0_SFT_SHIFT) /* Dual ID filter for SF1ID or SF2ID */
|
||||
# define STDFILTER_S0_SFT_CLASSIC (2 << STDFILTER_S0_SFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */
|
||||
|
||||
/* Extended Message ID Filter Element */
|
||||
|
||||
#define EXTFILTER_F0_EFID1_SHIFT (0) /* Bits 0-28: Extended Filter ID 1 */
|
||||
#define EXTFILTER_F0_EFID1_MASK (0x1fffffff << EXTFILTER_F0_EFID1_SHIFT)
|
||||
# define EXTFILTER_F0_EFID1(n) ((uint32_t)(n) << EXTFILTER_F0_EFID1_SHIFT)
|
||||
#define EXTFILTER_F0_EFEC_SHIFT (29) /* Bits 29-31: Extended Filter Element Configuration */
|
||||
#define EXTFILTER_F0_EFEC_MASK (7 << EXTFILTER_F0_EFEC_SHIFT)
|
||||
# define EXTFILTER_F0_EFEC_DISABLE (0 << EXTFILTER_F0_EFEC_SHIFT) /* Disable filter element */
|
||||
# define EXTFILTER_F0_EFEC_FIFO0 (1 << EXTFILTER_F0_EFEC_SHIFT) /* Store in Rx FIFO 0 on match */
|
||||
# define EXTFILTER_F0_EFEC_FIFO1 (2 << EXTFILTER_F0_EFEC_SHIFT) /* Store in Rx FIFO 1 on match */
|
||||
# define EXTFILTER_F0_EFEC_REJECT (3 << EXTFILTER_F0_EFEC_SHIFT) /* Reject ID on match */
|
||||
# define EXTFILTER_F0_EFEC_PRIORITY (4 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority on match */
|
||||
# define EXTFILTER_F0_EFEC_PRIOFIFO0 (5 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority and store in FIFO 0 on match */
|
||||
# define EXTFILTER_F0_EFEC_PRIOFIFO1 (6 << EXTFILTER_F0_EFEC_SHIFT) /* Set priority and store in FIFO 1 on match */
|
||||
# define EXTFILTER_F0_EFEC_BUFFER (7 << EXTFILTER_F0_EFEC_SHIFT) /* Store into Rx Buffer or as debug message */
|
||||
|
||||
#define EXTFILTER_F1_EFID2_SHIFT (0) /* Bits 0-28: Extended Filter ID 2 */
|
||||
#define EXTFILTER_F1_EFID2_MASK (0x1fffffff << EXTFILTER_F1_EFID2_SHIFT)
|
||||
# define EXTFILTER_F1_EFID2(n) ((uint32_t)(n) << EXTFILTER_F1_EFID2_SHIFT)
|
||||
#define EXTFILTER_F1_BUFFER_SHIFT (0) /* Bits 0-5: RX buffer start address */
|
||||
#define EXTFILTER_F1_BUFFER_MASK (0x3f << EXTFILTER_F1_BUFFER_SHIFT)
|
||||
# define EXTFILTER_F1_BUFFER(n) ((uint32_t)(n) << EXTFILTER_F1_BUFFER_SHIFT)
|
||||
#define EXTFILTER_F1_ACTION_SHIFT (9) /* Bits 9-10: Action taken */
|
||||
#define EXTFILTER_F1_ACTION_MASK (3 << EXTFILTER_F1_ACTION_SHIFT)
|
||||
# define EXTFILTER_F1_RXBUFFER (0 << EXTFILTER_F1_ACTION_SHIFT) /* Store message in a Rx buffer */
|
||||
# define EXTFILTER_F1_DEBUGA (1 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message A */
|
||||
# define EXTFILTER_F1_DEBUGB (2 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message B */
|
||||
# define EXTFILTER_F1_DEBUGC (3 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message C */
|
||||
#define EXTFILTER_F1_EFT_SHIFT (30) /* Bits 30-31: Extended Filter Type */
|
||||
#define EXTFILTER_F1_EFT_MASK (3 << EXTFILTER_F1_EFT_SHIFT)
|
||||
# define EXTFILTER_F1_EFT_RANGE (0 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from SF1ID to SF2ID */
|
||||
# define EXTFILTER_F1_EFT_DUAL (1 << EXTFILTER_F1_EFT_SHIFT) /* Dual ID filter for SF1ID or SF2ID */
|
||||
# define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */
|
||||
# define EXTFILTER_F1_EFT_NOXIDAM (2 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************/
|
||||
|
||||
@ -120,7 +120,8 @@
|
||||
|
||||
/* SPI Mode Register */
|
||||
|
||||
#define SPI_MR_MSTR (1 << 0) /* Bit 0: Master/Slave Mode */
|
||||
#define SPI_MR_MSTR (1 << 0) /* Bit 0: 1=Master Mode */
|
||||
# define SPI_MR_SLAVE (0) /* 0=Slave Mode */
|
||||
#define SPI_MR_PS (1 << 1) /* Bit 1: Peripheral Select */
|
||||
#define SPI_MR_PCSDEC (1 << 2) /* Bit 2: Chip Select Decode */
|
||||
#define SPI_MR_MODFDIS (1 << 4) /* Bit 4: Mode Fault Detection */
|
||||
|
||||
@ -152,14 +152,14 @@
|
||||
#define GPIO_AFE0_ADTRG (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN8)
|
||||
#define GPIO_AFE1_ADTRG (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN9)
|
||||
|
||||
/* CAN */
|
||||
/* MCAN */
|
||||
|
||||
#define GPIO_CAN0_RX (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3)
|
||||
#define GPIO_CAN0_TX (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2)
|
||||
#define GPIO_CAN1_RX_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN28)
|
||||
#define GPIO_CAN1_RX_2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12)
|
||||
#define GPIO_CAN1_TX_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN12)
|
||||
#define GPIO_CAN1_TX_2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14)
|
||||
#define GPIO_MCAN0_RX (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN3)
|
||||
#define GPIO_MCAN0_TX (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN2)
|
||||
#define GPIO_MCAN1_RX_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN28)
|
||||
#define GPIO_MCAN1_RX_2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12)
|
||||
#define GPIO_MCAN1_TX_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN12)
|
||||
#define GPIO_MCAN1_TX_2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14)
|
||||
|
||||
/* Digital-to-Analog Convert (DAC) */
|
||||
|
||||
|
||||
@ -255,22 +255,60 @@
|
||||
/* SPI ******************************************************************************/
|
||||
/* Don't enable SPI peripherals not supported by the chip. */
|
||||
|
||||
#if CHIP_NSPI < 1
|
||||
#if SAMV7_NSPI < 1
|
||||
# undef CONFIG_SAMV7_SPI0
|
||||
# undef CONFIG_SAMV7_SPI0_MASTER
|
||||
# undef CONFIG_SAMV7_SPI0_SLAVE
|
||||
# undef CONFIG_SAMV7_SPI1
|
||||
#elif CHIP_NSPI < 2
|
||||
# undef CONFIG_SAMV7_SPI1_MASTER
|
||||
# undef CONFIG_SAMV7_SPI1_SLAVE
|
||||
#elif SAMV7_NSPI < 2
|
||||
# undef CONFIG_SAMV7_SPI1
|
||||
# undef CONFIG_SAMV7_SPI1_MASTER
|
||||
# undef CONFIG_SAMV7_SPI1_SLAVE
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SAMV7_HAVE_SPI
|
||||
#ifndef CONFIG_SAMV7_SPI
|
||||
# undef CONFIG_SAMV7_SPI0
|
||||
# undef CONFIG_SAMV7_SPI0_MASTER
|
||||
# undef CONFIG_SAMV7_SPI0_SLAVE
|
||||
# undef CONFIG_SAMV7_SPI1
|
||||
# undef CONFIG_SAMV7_SPI1_MASTER
|
||||
# undef CONFIG_SAMV7_SPI1_SLAVE
|
||||
#endif
|
||||
|
||||
/* Are any SPI peripherals enabled? */
|
||||
|
||||
#if !defined(CONFIG_SAMV7_SPI0) && !defined(CONFIG_SAMV7_SPI0)
|
||||
# undef CONFIG_SAMV7_HAVE_SPI
|
||||
# undef CONFIG_SAMV7_SPI
|
||||
# undef CONFIG_SAMV7_SPI_MASTER
|
||||
# undef CONFIG_SAMV7_SPI_SLAVE
|
||||
#endif
|
||||
|
||||
/* Each SPI peripheral must be enabled as a MASTER or as a SLAVE */
|
||||
|
||||
#ifndef CONFIG_SAMV7_SPI_MASTER
|
||||
# undef CONFIG_SAMV7_SPI0_MASTER
|
||||
# undef CONFIG_SAMV7_SPI1_MASTER
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SAMV7_SPI0_MASTER) && !defined(CONFIG_SAMV7_SPI1_MASTER)
|
||||
# undef CONFIG_SAMV7_SPI_MASTER
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SAMV7_SPI_SLAVE
|
||||
# undef CONFIG_SAMV7_SPI0_SLAVE
|
||||
# undef CONFIG_SAMV7_SPI1_SLAVE
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SAMV7_SPI0_SLAVE) && !defined(CONFIG_SAMV7_SPI1_SLAVE)
|
||||
# undef CONFIG_SAMV7_SPI_SLAVE
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SAMV7_SPI_MASTER) && !defined(CONFIG_SAMV7_SPI_SLAVE)
|
||||
# undef CONFIG_SAMV7_SPI
|
||||
# undef CONFIG_SAMV7_SPI0
|
||||
# undef CONFIG_SAMV7_SPI1
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
@ -350,7 +350,7 @@
|
||||
* the 8-byte (2 word boundaries). However, if the data cache is enabled
|
||||
* the a higher level of alignment is required. That is because the data
|
||||
* will need to be invalidated and that cache invalidation will occur in
|
||||
* multiples of full change lines.
|
||||
* multiples of full cache lines.
|
||||
*
|
||||
* In addition, padding may be required at the ends of the descriptors and
|
||||
* buffers to protect data after the end of from invalidation.
|
||||
|
||||
3520
arch/arm/src/samv7/sam_mcan.c
Normal file
3520
arch/arm/src/samv7/sam_mcan.c
Normal file
File diff suppressed because it is too large
Load Diff
110
arch/arm/src/samv7/sam_mcan.h
Normal file
110
arch/arm/src/samv7/sam_mcan.h
Normal file
@ -0,0 +1,110 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/samv7/sam_mcan.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMV7_SAM_MCAN_H
|
||||
#define __ARCH_ARM_SRC_SAMV7_SAM_MCAN_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/sam_mcan.h"
|
||||
|
||||
#include <nuttx/can.h>
|
||||
|
||||
#if defined(CONFIG_CAN) && (defined(CONFIG_SAMV7_MCAN0) || \
|
||||
defined(CONFIG_SAMV7_MCAN1))
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Port numbers for use with sam_mcan_initialize() */
|
||||
|
||||
#define MCAN0 0
|
||||
#define MCAN1 1
|
||||
|
||||
/***************************************************************************
|
||||
* Public Types
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/***************************************************************************
|
||||
* Public Functions
|
||||
***************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_mcan_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected MCAN port
|
||||
*
|
||||
* Input Parameter:
|
||||
* port - Port number (for hardware that has multiple CAN interfaces),
|
||||
* 0=MCAN0, 1=NCAN1
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid CAN device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct can_dev_s;
|
||||
FAR struct can_dev_s *sam_mcan_initialize(int port);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_CAN && (CONFIG_SAMV7_MCAN0 || CONFIG_SAMV7_MCAN1) */
|
||||
#endif /* __ARCH_ARM_SRC_SAMV7_SAM_MCAN_H */
|
||||
@ -69,7 +69,7 @@
|
||||
#include "chip/sam_spi.h"
|
||||
#include "chip/sam_pinmap.h"
|
||||
|
||||
#if defined(CONFIG_SAMV7_SPI0) || defined(CONFIG_SAMV7_SPI1)
|
||||
#ifdef CONFIG_SAMV7_SPI_MASTER
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -86,13 +86,13 @@
|
||||
|
||||
#ifdef CONFIG_SAMV7_SPI_DMA
|
||||
|
||||
# if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_DMAC0)
|
||||
# if defined(CONFIG_SAMV7_SPI0_MASTER) && defined(CONFIG_SAMV7_DMAC0)
|
||||
# define SAMV7_SPI0_DMA true
|
||||
# else
|
||||
# define SAMV7_SPI0_DMA false
|
||||
# endif
|
||||
|
||||
# if defined(CONFIG_SAMV7_SPI1) && defined(CONFIG_SAMV7_DMAC1)
|
||||
# if defined(CONFIG_SAMV7_SPI1_MASTER) && defined(CONFIG_SAMV7_DMAC1)
|
||||
# define SAMV7_SPI1_DMA true
|
||||
# else
|
||||
# define SAMV7_SPI1_DMA false
|
||||
@ -118,7 +118,7 @@
|
||||
#define DMA_TIMEOUT_TICKS MSEC2TICK(DMA_TIMEOUT_MS)
|
||||
|
||||
/* Debug *******************************************************************/
|
||||
/* Check if SPI debut is enabled (non-standard.. no support in
|
||||
/* Check if SPI debug is enabled (non-standard.. no support in
|
||||
* include/debug.h
|
||||
*/
|
||||
|
||||
@ -170,7 +170,7 @@ struct sam_spics_s
|
||||
#endif
|
||||
uint8_t nbits; /* Width of word in bits (8 to 16) */
|
||||
|
||||
#if defined(CONFIG_SAMV7_SPI0) || defined(CONFIG_SAMV7_SPI1)
|
||||
#if defined(CONFIG_SAMV7_SPI0_MASTER) || defined(CONFIG_SAMV7_SPI1_MASTER)
|
||||
uint8_t spino; /* SPI controller number (0 or 1) */
|
||||
#endif
|
||||
uint8_t cs; /* Chip select number */
|
||||
@ -196,7 +196,7 @@ struct sam_spics_s
|
||||
|
||||
typedef void (*select_t)(enum spi_dev_e devid, bool selected);
|
||||
|
||||
/* Chip select register offsetrs */
|
||||
/* Chip select register offsets */
|
||||
|
||||
/* The overall state of one SPI controller */
|
||||
|
||||
@ -273,7 +273,7 @@ static inline uintptr_t spi_regaddr(struct sam_spics_s *spics,
|
||||
unsigned int offset);
|
||||
#endif
|
||||
|
||||
/* SPI methods */
|
||||
/* SPI master methods */
|
||||
|
||||
#ifndef CONFIG_SPI_OWNBUS
|
||||
static int spi_lock(struct spi_dev_s *dev, bool lock);
|
||||
@ -309,7 +309,7 @@ static const uint8_t g_csroffset[4] =
|
||||
SAM_SPI_CSR2_OFFSET, SAM_SPI_CSR3_OFFSET
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SAMV7_SPI0
|
||||
#ifdef CONFIG_SAMV7_SPI0_MASTER
|
||||
/* SPI0 driver operations */
|
||||
|
||||
static const struct spi_ops_s g_spi0ops =
|
||||
@ -348,7 +348,7 @@ static struct sam_spidev_s g_spi0dev =
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMV7_SPI1
|
||||
#ifdef CONFIG_SAMV7_SPI1_MASTER
|
||||
/* SPI1 driver operations */
|
||||
|
||||
static const struct spi_ops_s g_spi1ops =
|
||||
@ -541,9 +541,9 @@ static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg)
|
||||
|
||||
static inline struct sam_spidev_s *spi_device(struct sam_spics_s *spics)
|
||||
{
|
||||
#if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_SPI1)
|
||||
#if defined(CONFIG_SAMV7_SPI0_MASTER) && defined(CONFIG_SAMV7_SPI1_MASTER)
|
||||
return spics->spino ? &g_spi1dev : &g_spi0dev;
|
||||
#elif defined(CONFIG_SAMV7_SPI0)
|
||||
#elif defined(CONFIG_SAMV7_SPI0_MASTER)
|
||||
return &g_spi0dev;
|
||||
#else
|
||||
return &g_spi1dev;
|
||||
@ -1753,9 +1753,9 @@ struct spi_dev_s *up_spiinitialize(int port)
|
||||
spivdbg("port: %d csno: %d spino: %d\n", port, csno, spino);
|
||||
DEBUGASSERT(csno >= 0 && csno <= SAM_SPI_NCS);
|
||||
|
||||
#if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_SPI1)
|
||||
#if defined(CONFIG_SAMV7_SPI0_MASTER) && defined(CONFIG_SAMV7_SPI1_MASTER)
|
||||
DEBUGASSERT(spino >= 0 && spino <= 1);
|
||||
#elif defined(CONFIG_SAMV7_SPI0)
|
||||
#elif defined(CONFIG_SAMV7_SPI0_MASTER)
|
||||
DEBUGASSERT(spino == 0);
|
||||
#else
|
||||
DEBUGASSERT(spino == 1);
|
||||
@ -1812,9 +1812,9 @@ struct spi_dev_s *up_spiinitialize(int port)
|
||||
|
||||
/* Select the SPI operations */
|
||||
|
||||
#if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_SPI1)
|
||||
#if defined(CONFIG_SAMV7_SPI0_MASTER) && defined(CONFIG_SAMV7_SPI1_MASTER)
|
||||
spics->spidev.ops = spino ? &g_spi1ops : &g_spi0ops;
|
||||
#elif defined(CONFIG_SAMV7_SPI0)
|
||||
#elif defined(CONFIG_SAMV7_SPI0_MASTER)
|
||||
spics->spidev.ops = &g_spi0ops;
|
||||
#else
|
||||
spics->spidev.ops = &g_spi1ops;
|
||||
@ -1823,7 +1823,7 @@ struct spi_dev_s *up_spiinitialize(int port)
|
||||
/* Save the chip select and SPI controller numbers */
|
||||
|
||||
spics->cs = csno;
|
||||
#if defined(CONFIG_SAMV7_SPI0) || defined(CONFIG_SAMV7_SPI1)
|
||||
#if defined(CONFIG_SAMV7_SPI0_MASTER) || defined(CONFIG_SAMV7_SPI1_MASTER)
|
||||
spics->spino = spino;
|
||||
#endif
|
||||
|
||||
@ -1838,10 +1838,10 @@ struct spi_dev_s *up_spiinitialize(int port)
|
||||
/* Enable clocking to the SPI block */
|
||||
|
||||
flags = irqsave();
|
||||
#if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_SPI1)
|
||||
#if defined(CONFIG_SAMV7_SPI0_MASTER) && defined(CONFIG_SAMV7_SPI1_MASTER)
|
||||
if (spino == 0)
|
||||
#endif
|
||||
#if defined(CONFIG_SAMV7_SPI0)
|
||||
#if defined(CONFIG_SAMV7_SPI0_MASTER)
|
||||
{
|
||||
sam_spi0_enableclk();
|
||||
|
||||
@ -1854,10 +1854,10 @@ struct spi_dev_s *up_spiinitialize(int port)
|
||||
sam_configgpio(GPIO_SPI0_SPCK);
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_SPI1)
|
||||
#if defined(CONFIG_SAMV7_SPI0_MASTER) && defined(CONFIG_SAMV7_SPI1_MASTER)
|
||||
else
|
||||
#endif
|
||||
#if defined(CONFIG_SAMV7_SPI1)
|
||||
#if defined(CONFIG_SAMV7_SPI1_MASTER)
|
||||
{
|
||||
sam_spi1_enableclk();
|
||||
|
||||
@ -1938,4 +1938,4 @@ struct spi_dev_s *up_spiinitialize(int port)
|
||||
|
||||
return &spics->spidev;
|
||||
}
|
||||
#endif /* CONFIG_SAMV7_SPI0 || CONFIG_SAMV7_SPI1 */
|
||||
#endif /* CONFIG_SAMV7_SPI_MASTER */
|
||||
|
||||
@ -46,6 +46,7 @@
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "sam_config.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
1183
arch/arm/src/samv7/sam_spi_slave.c
Normal file
1183
arch/arm/src/samv7/sam_spi_slave.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -3114,7 +3114,7 @@ config STM32_TIM14_DAC2
|
||||
endchoice
|
||||
|
||||
menu "ADC Configuration"
|
||||
depends on STM32_ADC1
|
||||
depends on STM32_ADC
|
||||
|
||||
config STM32_ADC1_DMA
|
||||
bool "ADC1 DMA"
|
||||
|
||||
@ -512,7 +512,7 @@
|
||||
#define DMAMAP_TIM8_UP STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
|
||||
@ -1596,7 +1596,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
DEBUGASSERT(priv->nchannels <= ADC_MAX_CHANNELS_NODMA);
|
||||
}
|
||||
|
||||
regval |= (((uint32_t)priv->nchannels-1) << ADC_SQR1_L_SHIFT);
|
||||
regval |= (((uint32_t)priv->nchannels - 1) << ADC_SQR1_L_SHIFT);
|
||||
adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval);
|
||||
|
||||
/* Set the channel index of the first conversion */
|
||||
@ -2284,6 +2284,7 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch)
|
||||
}
|
||||
|
||||
#else
|
||||
priv->nchannels = priv->cchannels;
|
||||
regval = adc_getreg(priv, STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED;
|
||||
for (i = 0, offset = 0; i < priv->nchannels && i < 6; i++, offset += 5)
|
||||
{
|
||||
@ -2320,10 +2321,11 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch)
|
||||
break;
|
||||
}
|
||||
|
||||
regval = adc_getreg(priv, STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED;
|
||||
regval = adc_getreg(priv, STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED;
|
||||
regval &= ~(ADC_SQR1_L_MASK);
|
||||
adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval);
|
||||
priv->current = i;
|
||||
|
||||
priv->current = i;
|
||||
priv->nchannels = 1;
|
||||
return ret;
|
||||
}
|
||||
@ -2761,7 +2763,7 @@ void stm32_adcchange_sample_time(FAR struct adc_dev_s *dev,
|
||||
* Input Parameters:
|
||||
* intf - Could be {1,2,3} for ADC1, ADC2, or ADC3
|
||||
* chanlist - The list of channels
|
||||
* nchannels - Number of channels
|
||||
* cchannels - Number of channels
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid ADC device structure reference on succcess; a NULL on failure
|
||||
@ -2774,7 +2776,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist,
|
||||
FAR struct adc_dev_s *dev;
|
||||
FAR struct stm32_dev_s *priv;
|
||||
|
||||
allvdbg("intf: %d nchannels: %d\n", intf, cchannels);
|
||||
allvdbg("intf: %d cchannels: %d\n", intf, cchannels);
|
||||
|
||||
#ifdef CONFIG_STM32_ADC1
|
||||
if (intf == 1)
|
||||
|
||||
@ -209,11 +209,15 @@
|
||||
#undef ADC_HAVE_DMA
|
||||
#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \
|
||||
defined(CONFIG_STM32_ADC3_DMA) || defined(CONFIG_STM32_ADC4_DMA)
|
||||
# if defined(CONFIG_STM32_STM32F40XX)
|
||||
# if defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
# define ADC_HAVE_DMA 1
|
||||
#else
|
||||
# warning DMA is only supported for the stm32f40xx family
|
||||
# endif
|
||||
# else
|
||||
# warning DMA is only supported for the STM32 F2/F4 family
|
||||
# undef CONFIG_STM32_ADC1_DMA
|
||||
# undef CONFIG_STM32_ADC2_DMA
|
||||
# undef CONFIG_STM32_ADC3_DMA
|
||||
# undef CONFIG_STM32_ADC4_DMA
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_ADC1_DMA
|
||||
|
||||
Loading…
Reference in New Issue
Block a user