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SAMA5D4: Complete MPDDR header file

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This commit is contained in:
Gregory Nutt 2014-06-10 11:16:05 -06:00
parent 021122f921
commit f14775b755
2 changed files with 563 additions and 351 deletions
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2
arch/arm/src/sama5/chip/sama5d3x_mpddrc.h
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@ -292,7 +292,7 @@
#define MPDDRC_LPDDR2_LPR_BK_MASK_PASR_MASK (0xff << MPDDRC_LPDDR2_LPR_BK_MASK_PASR_SHIFT) #define MPDDRC_LPDDR2_LPR_BK_MASK_PASR_MASK (0xff << MPDDRC_LPDDR2_LPR_BK_MASK_PASR_SHIFT)
# define MPDDRC_LPDDR2_LPR_BK_MASK_PASR(n) ((n) << MPDDRC_LPDDR2_LPR_BK_MASK_PASR_SHIFT) # define MPDDRC_LPDDR2_LPR_BK_MASK_PASR(n) ((n) << MPDDRC_LPDDR2_LPR_BK_MASK_PASR_SHIFT)
#define MPDDRC_LPDDR2_LPR_SEG_MASK_SHIFT (8) /* Bits 8-23: Segment Mask*/ #define MPDDRC_LPDDR2_LPR_SEG_MASK_SHIFT (8) /* Bits 8-23: Segment Mask*/
#define MPDDRC_LPDDR2_LPR_SEG_MASK_MASK (0xff << MPDDRC_LPDDR2_LPR_SEG_MASK_SHIFT) #define MPDDRC_LPDDR2_LPR_SEG_MASK_MASK (0xffff << MPDDRC_LPDDR2_LPR_SEG_MASK_SHIFT)
# define MPDDRC_LPDDR2_LPR_SEG_MASK(n) ((n) << MPDDRC_LPDDR2_LPR_SEG_MASK_SHIFT) # define MPDDRC_LPDDR2_LPR_SEG_MASK(n) ((n) << MPDDRC_LPDDR2_LPR_SEG_MASK_SHIFT)
#define MPDDRC_LPDDR2_LPR_DS_SHIFT (24) /* Bits 24-27: Drive strength */ #define MPDDRC_LPDDR2_LPR_DS_SHIFT (24) /* Bits 24-27: Drive strength */
#define MPDDRC_LPDDR2_LPR_DS_MASK (15 << MPDDRC_LPDDR2_LPR_DS_SHIFT) #define MPDDRC_LPDDR2_LPR_DS_MASK (15 << MPDDRC_LPDDR2_LPR_DS_SHIFT)

356
arch/arm/src/sama5/chip/sama5d4x_mpddrc.h
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@ -1,4 +1,4 @@
/************************************************************************************ /********************************************************************************************
* arch/arm/src/sama5/chip/sama5d4x_mpddrc.h * arch/arm/src/sama5/chip/sama5d4x_mpddrc.h
* *
* Copyright (C) 2014 Gregory Nutt. All rights reserved. * Copyright (C) 2014 Gregory Nutt. All rights reserved.
@ -31,22 +31,22 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
************************************************************************************/ ********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAMA5D4X_MPDDRC_H #ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAMA5D4X_MPDDRC_H
#define __ARCH_ARM_SRC_SAMA5_CHIP_SAMA5D4X_MPDDRC_H #define __ARCH_ARM_SRC_SAMA5_CHIP_SAMA5D4X_MPDDRC_H
/************************************************************************************ /********************************************************************************************
* Included Files * Included Files
************************************************************************************/ ********************************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "chip/sam_memorymap.h" #include "chip/sam_memorymap.h"
/************************************************************************************ /********************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ********************************************************************************************/
/* MPDDRC Register Offsets **********************************************************/ /* MPDDRC Register Offsets ******************************************************************/
#define SAM_MPDDRC_MR_OFFSET 0x0000 /* MPDDRC Mode Register */ #define SAM_MPDDRC_MR_OFFSET 0x0000 /* MPDDRC Mode Register */
#define SAM_MPDDRC_RTR_OFFSET 0x0004 /* MPDDRC Refresh Timer Register */ #define SAM_MPDDRC_RTR_OFFSET 0x0004 /* MPDDRC Refresh Timer Register */
@ -72,11 +72,13 @@
#define SAM_MPDDRC_BDW_PORT_0123_OFFSET 0x0054 /* MPDDRC Bandwidth Port 0/1/2/3 Register */ #define SAM_MPDDRC_BDW_PORT_0123_OFFSET 0x0054 /* MPDDRC Bandwidth Port 0/1/2/3 Register */
#define SAM_MPDDRC_BDW_PORT_4567_OFFSET 0x0058 /* MPDDRC Bandwidth Port 4/5/6/7 Register */ #define SAM_MPDDRC_BDW_PORT_4567_OFFSET 0x0058 /* MPDDRC Bandwidth Port 4/5/6/7 Register */
#define SAM_MPDDRC_RD_DATA_PATH_OFFSET 0x005c /* MPDDRC Read Datapath Register */ #define SAM_MPDDRC_RD_DATA_PATH_OFFSET 0x005c /* MPDDRC Read Datapath Register */
#define SAM_MPPDRC_SAW_OFFSET(n) (0x0060+((n) << 2))
#define SAM_MPDDRC_SAW0_OFFSET 0x0060 /* MPDDRC Smart Adaptation Wrapper 0 Register */ #define SAM_MPDDRC_SAW0_OFFSET 0x0060 /* MPDDRC Smart Adaptation Wrapper 0 Register */
#define SAM_MPDDRC_SAW1_OFFSET 0x0064 /* MPDDRC Smart Adaptation Wrapper 1 Register */ #define SAM_MPDDRC_SAW1_OFFSET 0x0064 /* MPDDRC Smart Adaptation Wrapper 1 Register */
#define SAM_MPDDRC_SAW2_OFFSET 0x0068 /* MPDDRC Smart Adaptation Wrapper 2 Register */ #define SAM_MPDDRC_SAW2_OFFSET 0x0068 /* MPDDRC Smart Adaptation Wrapper 2 Register */
#define SAM_MPDDRC_SAW3_OFFSET 0x006c /* MPDDRC Smart Adaptation Wrapper 3 Register */ #define SAM_MPDDRC_SAW3_OFFSET 0x006c /* MPDDRC Smart Adaptation Wrapper 3 Register */
/* 0x0060–0x00e0 Reserved */ /* 0x0060-0x00e0 Reserved */
#define SAM_MPDDRC_WPCR_OFFSET 0x00e4 /* MPDDRC Write Protect Control Register */ #define SAM_MPDDRC_WPCR_OFFSET 0x00e4 /* MPDDRC Write Protect Control Register */
#define SAM_MPDDRC_WPSR_OFFSET 0x00e8 /* MPDDRC Write Protect Status Register */ #define SAM_MPDDRC_WPSR_OFFSET 0x00e8 /* MPDDRC Write Protect Status Register */
@ -86,10 +88,14 @@
#define SAM_MPDDRC_DLL_SO1_OFFSET 0x010c /* MPDDRC DLL SLAVE Offset 1 Register */ #define SAM_MPDDRC_DLL_SO1_OFFSET 0x010c /* MPDDRC DLL SLAVE Offset 1 Register */
#define SAM_MPDDRC_DLL_WRO_OFFSET 0x0110 /* MPDDRC DLL CLKWR Offset Register */ #define SAM_MPDDRC_DLL_WRO_OFFSET 0x0110 /* MPDDRC DLL CLKWR Offset Register */
#define SAM_MPDDRC_DLL_ADO_OFFSET 0x0114 /* MPDDRC DLL CLKAD Offset Register */ #define SAM_MPDDRC_DLL_ADO_OFFSET 0x0114 /* MPDDRC DLL CLKAD Offset Register */
#define SAM_MPDDRC_DLL_SM_OFFSET(n) (0x0118+((n)<<2))
#define SAM_MPDDRC_DLL_SM0_OFFSET 0x0118 /* MPDDRC DLL Status MASTER0 Register */ #define SAM_MPDDRC_DLL_SM0_OFFSET 0x0118 /* MPDDRC DLL Status MASTER0 Register */
#define SAM_MPDDRC_DLL_SM1_OFFSET 0x011c /* MPDDRC DLL Status MASTER1 Register */ #define SAM_MPDDRC_DLL_SM1_OFFSET 0x011c /* MPDDRC DLL Status MASTER1 Register */
#define SAM_MPDDRC_DLL_SM2_OFFSET 0x0120 /* MPDDRC DLL Status MASTER2 Register */ #define SAM_MPDDRC_DLL_SM2_OFFSET 0x0120 /* MPDDRC DLL Status MASTER2 Register */
#define SAM_MPDDRC_DLL_SM3_OFFSET 0x0124 /* MPDDRC DLL Status MASTER3 Register */ #define SAM_MPDDRC_DLL_SM3_OFFSET 0x0124 /* MPDDRC DLL Status MASTER3 Register */
#define SAM_MPDDRC_DLL_SSL_OFFSET(n) (0x0128+((n)<<2))
#define SAM_MPDDRC_DLL_SSL0_OFFSET 0x0128 /* MPDDRC DLL Status SLAVE0 Register */ #define SAM_MPDDRC_DLL_SSL0_OFFSET 0x0128 /* MPDDRC DLL Status SLAVE0 Register */
#define SAM_MPDDRC_DLL_SSL1_OFFSET 0x012c /* MPDDRC DLL Status SLAVE1 Register */ #define SAM_MPDDRC_DLL_SSL1_OFFSET 0x012c /* MPDDRC DLL Status SLAVE1 Register */
#define SAM_MPDDRC_DLL_SSL2_OFFSET 0x0130 /* MPDDRC DLL Status SLAVE2 Register */ #define SAM_MPDDRC_DLL_SSL2_OFFSET 0x0130 /* MPDDRC DLL Status SLAVE2 Register */
@ -98,14 +104,17 @@
#define SAM_MPDDRC_DLL_SSL5_OFFSET 0x013c /* MPDDRC DLL Status SLAVE5 Register */ #define SAM_MPDDRC_DLL_SSL5_OFFSET 0x013c /* MPDDRC DLL Status SLAVE5 Register */
#define SAM_MPDDRC_DLL_SSL6_OFFSET 0x0140 /* MPDDRC DLL Status SLAVE6 Register */ #define SAM_MPDDRC_DLL_SSL6_OFFSET 0x0140 /* MPDDRC DLL Status SLAVE6 Register */
#define SAM_MPDDRC_DLL_SSL7_OFFSET 0x0144 /* MPDDRC DLL Status SLAVE7 Register */ #define SAM_MPDDRC_DLL_SSL7_OFFSET 0x0144 /* MPDDRC DLL Status SLAVE7 Register */
#define SAM_MPDDRC_DLL_SWR_OFFSET(n) (0x0148+((n)<<2))
#define SAM_MPDDRC_DLL_SWR0_OFFSET 0x0148 /* MPDDRC DLL Status CLKWR0 Register */ #define SAM_MPDDRC_DLL_SWR0_OFFSET 0x0148 /* MPDDRC DLL Status CLKWR0 Register */
#define SAM_MPDDRC_DLL_SWR1_OFFSET 0x014c /* MPDDRC DLL Status CLKWR1 Register */ #define SAM_MPDDRC_DLL_SWR1_OFFSET 0x014c /* MPDDRC DLL Status CLKWR1 Register */
#define SAM_MPDDRC_DLL_SWR2_OFFSET 0x0150 /* MPDDRC DLL StatusCLKWR2 Register */ #define SAM_MPDDRC_DLL_SWR2_OFFSET 0x0150 /* MPDDRC DLL StatusCLKWR2 Register */
#define SAM_MPDDRC_DLL_SWR3_OFFSET 0x0154 /* MPDDRC DLL Status CLKWR3 Register */ #define SAM_MPDDRC_DLL_SWR3_OFFSET 0x0154 /* MPDDRC DLL Status CLKWR3 Register */
#define SAM_MPDDRC_DLL_SAD_OFFSET 0x0158 /* MPDDRC DLL Status CLKAD Register */
/* 0x015c–0x01fxc Reserved */
/* MPDDRC Register Addresses ********************************************************/ #define SAM_MPDDRC_DLL_SAD_OFFSET 0x0158 /* MPDDRC DLL Status CLKAD Register */
/* 0x015c-0x01fxc Reserved */
/* MPDDRC Register Addresses ****************************************************************/
#define SAM_MPDDRC_MR (SAM_MPDDRC_VBASE+SAM_MPDDRC_MR_OFFSET) #define SAM_MPDDRC_MR (SAM_MPDDRC_VBASE+SAM_MPDDRC_MR_OFFSET)
#define SAM_MPDDRC_RTR (SAM_MPDDRC_VBASE+SAM_MPDDRC_RTR_OFFSET) #define SAM_MPDDRC_RTR (SAM_MPDDRC_VBASE+SAM_MPDDRC_RTR_OFFSET)
@ -129,6 +138,8 @@
#define SAM_MPDDRC_BDW_PORT_0123 (SAM_MPDDRC_VBASE+SAM_MPDDRC_BDW_PORT_0123_OFFSET) #define SAM_MPDDRC_BDW_PORT_0123 (SAM_MPDDRC_VBASE+SAM_MPDDRC_BDW_PORT_0123_OFFSET)
#define SAM_MPDDRC_BDW_PORT_4567 (SAM_MPDDRC_VBASE+SAM_MPDDRC_BDW_PORT_4567_OFFSET) #define SAM_MPDDRC_BDW_PORT_4567 (SAM_MPDDRC_VBASE+SAM_MPDDRC_BDW_PORT_4567_OFFSET)
#define SAM_MPDDRC_RD_DATA_PATH (SAM_MPDDRC_VBASE+SAM_MPDDRC_RD_DATA_PATH_OFFSET) #define SAM_MPDDRC_RD_DATA_PATH (SAM_MPDDRC_VBASE+SAM_MPDDRC_RD_DATA_PATH_OFFSET)
#define SAM_MPPDRC_SAW(n) (SAM_MPDDRC_VBASE+SAM_MPPDRC_SAW_OFFSET(n)
#define SAM_MPDDRC_SAW0 (SAM_MPDDRC_VBASE+SAM_MPDDRC_SAW0_OFFSET) #define SAM_MPDDRC_SAW0 (SAM_MPDDRC_VBASE+SAM_MPDDRC_SAW0_OFFSET)
#define SAM_MPDDRC_SAW1 (SAM_MPDDRC_VBASE+SAM_MPDDRC_SAW1_OFFSET) #define SAM_MPDDRC_SAW1 (SAM_MPDDRC_VBASE+SAM_MPDDRC_SAW1_OFFSET)
#define SAM_MPDDRC_SAW2 (SAM_MPDDRC_VBASE+SAM_MPDDRC_SAW2_OFFSET) #define SAM_MPDDRC_SAW2 (SAM_MPDDRC_VBASE+SAM_MPDDRC_SAW2_OFFSET)
@ -143,10 +154,14 @@
#define SAM_MPDDRC_DLL_SO1 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SO1_OFFSET) #define SAM_MPDDRC_DLL_SO1 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SO1_OFFSET)
#define SAM_MPDDRC_DLL_WRO (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_WRO_OFFSET) #define SAM_MPDDRC_DLL_WRO (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_WRO_OFFSET)
#define SAM_MPDDRC_DLL_ADO (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_ADO_OFFSET) #define SAM_MPDDRC_DLL_ADO (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_ADO_OFFSET)
#define SAM_MPDDRC_DLL_SM(n) (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SM_OFFSET(n))
#define SAM_MPDDRC_DLL_SM0 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SM0_OFFSET) #define SAM_MPDDRC_DLL_SM0 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SM0_OFFSET)
#define SAM_MPDDRC_DLL_SM1 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SM1_OFFSET) #define SAM_MPDDRC_DLL_SM1 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SM1_OFFSET)
#define SAM_MPDDRC_DLL_SM2 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SM2_OFFSET) #define SAM_MPDDRC_DLL_SM2 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SM2_OFFSET)
#define SAM_MPDDRC_DLL_SM3 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SM3_OFFSET) #define SAM_MPDDRC_DLL_SM3 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SM3_OFFSET)
#define SAM_MPDDRC_DLL_SSL(n) (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SSL_OFFSET(n))
#define SAM_MPDDRC_DLL_SSL0 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SSL0_OFFSET) #define SAM_MPDDRC_DLL_SSL0 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SSL0_OFFSET)
#define SAM_MPDDRC_DLL_SSL1 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SSL1_OFFSET) #define SAM_MPDDRC_DLL_SSL1 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SSL1_OFFSET)
#define SAM_MPDDRC_DLL_SSL2 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SSL2_OFFSET) #define SAM_MPDDRC_DLL_SSL2 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SSL2_OFFSET)
@ -155,13 +170,16 @@
#define SAM_MPDDRC_DLL_SSL5 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SSL5_OFFSET) #define SAM_MPDDRC_DLL_SSL5 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SSL5_OFFSET)
#define SAM_MPDDRC_DLL_SSL6 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SSL6_OFFSET) #define SAM_MPDDRC_DLL_SSL6 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SSL6_OFFSET)
#define SAM_MPDDRC_DLL_SSL7 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SSL7_OFFSET) #define SAM_MPDDRC_DLL_SSL7 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SSL7_OFFSET)
#define SAM_MPDDRC_DLL_SWR(n) (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SWR_OFFSET(n))
#define SAM_MPDDRC_DLL_SWR0 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SWR0_OFFSET) #define SAM_MPDDRC_DLL_SWR0 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SWR0_OFFSET)
#define SAM_MPDDRC_DLL_SWR1 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SWR1_OFFSET) #define SAM_MPDDRC_DLL_SWR1 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SWR1_OFFSET)
#define SAM_MPDDRC_DLL_SWR2 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SWR2_OFFSET) #define SAM_MPDDRC_DLL_SWR2 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SWR2_OFFSET)
#define SAM_MPDDRC_DLL_SWR3 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SWR3_OFFSET) #define SAM_MPDDRC_DLL_SWR3 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SWR3_OFFSET)
#define SAM_MPDDRC_DLL_SAD (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SAD_OFFSET) #define SAM_MPDDRC_DLL_SAD (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SAD_OFFSET)
/* MPDDRC Register Bit Definitions **************************************************/ /* MPDDRC Register Bit Definitions **********************************************************/
/* MPDDRC Mode Register */ /* MPDDRC Mode Register */
@ -226,6 +244,7 @@
# define MPDDRC_CR_OCD_DEFAULT (7 << MPDDRC_CR_OCD_SHIFT) /* OCD calibration default */ # define MPDDRC_CR_OCD_DEFAULT (7 << MPDDRC_CR_OCD_SHIFT) /* OCD calibration default */
#define MPDDRC_CR_DQMS (1 << 16) /* Bit 16: Mask Data is Shared */ #define MPDDRC_CR_DQMS (1 << 16) /* Bit 16: Mask Data is Shared */
#define MPDDRC_CR_ENRDM (1 << 17) /* Bit 17: Enable Read Measure */ #define MPDDRC_CR_ENRDM (1 << 17) /* Bit 17: Enable Read Measure */
#define MPDDRC_CR_LC_LPDDR1 (1 << 19) /* Bit 19: Low-cost Low-power DDR1 */
#define MPDDRC_CR_NB (1 << 20) /* Bit 20: Number of Banks */ #define MPDDRC_CR_NB (1 << 20) /* Bit 20: Number of Banks */
# define MPDDRC_CR_4BANKS (0) /* 4 banks */ # define MPDDRC_CR_4BANKS (0) /* 4 banks */
# define MPDDRC_CR_8BANKS MPDDRC_CR_NB /* 8 banks */ # define MPDDRC_CR_8BANKS MPDDRC_CR_NB /* 8 banks */
@ -328,9 +347,10 @@
#define MPDDRC_MD_SHIFT (0) /* Bits 0-2: Memory Device */ #define MPDDRC_MD_SHIFT (0) /* Bits 0-2: Memory Device */
#define MPDDRC_MD_MASK (7 << MPDDRC_MD_SHIFT) #define MPDDRC_MD_MASK (7 << MPDDRC_MD_SHIFT)
# define MPDDRC_MD_LPDDR_SDRAM (2 << MPDDRC_MD_SHIFT) /* Low-power DDR1-SDRAM */ # define MPDDRC_MD_DDR_SDRAM (2 << MPDDRC_MD_SHIFT) /* DDR1-SDRAM */
# define MPDDRC_MD_LPDDR_SDRAM (3 << MPDDRC_MD_SHIFT) /* Low-power DDR1-SDRAM */
# define MPDDRC_MD_DDR2_SDRAM (6 << MPDDRC_MD_SHIFT) /* DDR2-SDRAM */ # define MPDDRC_MD_DDR2_SDRAM (6 << MPDDRC_MD_SHIFT) /* DDR2-SDRAM */
# define MPDDRC_MD_LPDDR2_SDRAM (7 << MPDDRC_MD_SHIFT) /* Low-Power DDR2-SDRAM */ # define MPDDRC_MD_LPDDR2_SDRAM (7 << MPDDRC_MD_SHIFT) /* Low-power DDR2-SDRAM */
#define MPDDRC_MD_DBW (1 << 4) /* Bit 4: Data Bus Width */ #define MPDDRC_MD_DBW (1 << 4) /* Bit 4: Data Bus Width */
# define MPDDRC_MD_DBW32 (0) /* Data bus width is 32 bits */ # define MPDDRC_MD_DBW32 (0) /* Data bus width is 32 bits */
# define MPDDRC_MD_DBW16 MPDDRC_MD_DBW /* Data bus width is 16 bits */ # define MPDDRC_MD_DBW16 MPDDRC_MD_DBW /* Data bus width is 16 bits */
@ -341,14 +361,11 @@
#define MPDDRC_LPDDR2_LPR_BK_MASK_PASR_MASK (0xff << MPDDRC_LPDDR2_LPR_BK_MASK_PASR_SHIFT) #define MPDDRC_LPDDR2_LPR_BK_MASK_PASR_MASK (0xff << MPDDRC_LPDDR2_LPR_BK_MASK_PASR_SHIFT)
# define MPDDRC_LPDDR2_LPR_BK_MASK_PASR(n) ((n) << MPDDRC_LPDDR2_LPR_BK_MASK_PASR_SHIFT) # define MPDDRC_LPDDR2_LPR_BK_MASK_PASR(n) ((n) << MPDDRC_LPDDR2_LPR_BK_MASK_PASR_SHIFT)
#define MPDDRC_LPDDR2_LPR_SEG_MASK_SHIFT (8) /* Bits 8-23: Segment Mask*/ #define MPDDRC_LPDDR2_LPR_SEG_MASK_SHIFT (8) /* Bits 8-23: Segment Mask*/
#define MPDDRC_LPDDR2_LPR_SEG_MASK_MASK (0xff << MPDDRC_LPDDR2_LPR_SEG_MASK_SHIFT) #define MPDDRC_LPDDR2_LPR_SEG_MASK_MASK (0xffff << MPDDRC_LPDDR2_LPR_SEG_MASK_SHIFT)
# define MPDDRC_LPDDR2_LPR_SEG_MASK(n) ((n) << MPDDRC_LPDDR2_LPR_SEG_MASK_SHIFT) # define MPDDRC_LPDDR2_LPR_SEG_MASK(n) ((n) << MPDDRC_LPDDR2_LPR_SEG_MASK_SHIFT)
#define MPDDRC_LPDDR2_LPR_DS_SHIFT (24) /* Bits 24-27: Drive strength */ #define MPDDRC_LPDDR2_LPR_DS_SHIFT (24) /* Bits 24-27: Drive strength */
#define MPDDRC_LPDDR2_LPR_DS_MASK (15 << MPDDRC_LPDDR2_LPR_DS_SHIFT) #define MPDDRC_LPDDR2_LPR_DS_MASK (15 << MPDDRC_LPDDR2_LPR_DS_SHIFT)
# define MPDDRC_LPDDR2_LPR_DS(n) ((n) << MPDDRC_LPDDR2_LPR_DS_SHIFT) # define MPDDRC_LPDDR2_LPR_DS(n) ((n) << MPDDRC_LPDDR2_LPR_DS_SHIFT)
#define MPDDRC_LPDDR2_LPR_SR_SHIFT (28) /* Bits 28-31: Slew Rate (REVISIT) */
#define MPDDRC_LPDDR2_LPR_SR_MASK (15 << MPDDRC_LPDDR2_LPR_SR_SHIFT)
# define MPDDRC_LPDDR2_LPR_SR(n) ((n) << MPDDRC_LPDDR2_LPR_SR_SHIFT)
/* MPDDRC LPDDR2 Calibration and MR4 Register */ /* MPDDRC LPDDR2 Calibration and MR4 Register */
@ -375,6 +392,7 @@
# define MPDDRC_IO_CALIBR_RZQ60_50 (4 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2:RZQ = 60 Ohm DDR2/LPDDR1: RZQ = 50 Ohm */ # define MPDDRC_IO_CALIBR_RZQ60_50 (4 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2:RZQ = 60 Ohm DDR2/LPDDR1: RZQ = 50 Ohm */
# define MPDDRC_IO_CALIBR_RZQ80_67 (6 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2 RZQ = 80 Ohm DDR2/LPDDR1: RZQ = 66.7 Ohm */ # define MPDDRC_IO_CALIBR_RZQ80_67 (6 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2 RZQ = 80 Ohm DDR2/LPDDR1: RZQ = 66.7 Ohm */
# define MPDDRC_IO_CALIBR_RZQ120_100 (7 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2:RZQ = 120 Oh m DDR2/LPDDR1: RZQ = 100 Ohm */ # define MPDDRC_IO_CALIBR_RZQ120_100 (7 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2:RZQ = 120 Oh m DDR2/LPDDR1: RZQ = 100 Ohm */
#define MPDDRC_IO_CALIBR_EN_CALIB (1 << 4) /* Bit 4: Enable of the Calibration */
#define MPDDRC_IO_CALIBR_TZQIO_SHIFT (8) /* Bits 8-10: IO Calibration */ #define MPDDRC_IO_CALIBR_TZQIO_SHIFT (8) /* Bits 8-10: IO Calibration */
#define MPDDRC_IO_CALIBR_TZQIO_MASK (7 << MPDDRC_IO_CALIBR_TZQIO_SHIFT) #define MPDDRC_IO_CALIBR_TZQIO_MASK (7 << MPDDRC_IO_CALIBR_TZQIO_SHIFT)
# define MPDDRC_IO_CALIBR_TZQIO(n) ((n) << MPDDRC_IO_CALIBR_TZQIO_SHIFT) # define MPDDRC_IO_CALIBR_TZQIO(n) ((n) << MPDDRC_IO_CALIBR_TZQIO_SHIFT)
@ -393,27 +411,162 @@
/* MPDDRC OCMS KEY2 Register (32-bit key value) */ /* MPDDRC OCMS KEY2 Register (32-bit key value) */
/* MPDDRC Configuration Arbiter Register */ /* MPDDRC Configuration Arbiter Register */
#define MPDDRC_CONF_ARBITER_
#define MPDDRC_CONF_ARBITER_ARB_SHIFT (0) /* Bits 0-1: Type of Arbitration */
#define MPDDRC_CONF_ARBITER_ARB_MASK (3 << MPDDRC_CONF_ARBITER_ARB_SHIFT)
# define MPDDRC_CONF_ARBITER_ARB_ROUND (0 << MPDDRC_CONF_ARBITER_ARB_SHIFT) /* Round Robin */
# define MPDDRC_CONF_ARBITER_ARB_NB_REQUEST (1 << MPDDRC_CONF_ARBITER_ARB_SHIFT) /* Request Policy */
# define MPDDRC_CONF_ARBITER_ARB_BANDWIDTH (2 << MPDDRC_CONF_ARBITER_ARB_SHIFT) /* Bandwidth Policy */
#define MPDDRC_CONF_ARBITER_BDW_BURST (1 << 2) /* Bit 2: Bandwidth is Reached or Bandwidth and Current Burst Access is Ended */
#define MPDDRC_CONF_ARBITER_BDW_MAX_CUR (1 << 3) /* Bit 3: Bandwidth Max or Current */
#define MPDDRC_CONF_ARBITER_RQ_WD_P(n) (1 << ((n)+8) /* Bits 8-15: Request or Word from Port n */
# define MPDDRC_CONF_ARBITER_RQ_WD_P0 (1 << 8) /* Bit 8: Request or Word from Port 0 */
# define MPDDRC_CONF_ARBITER_RQ_WD_P1 (1 << 9) /* Bit 9: Request or Word from Port 1 */
# define MPDDRC_CONF_ARBITER_RQ_WD_P2 (1 << 10) /* Bit 10: Request or Word from Port 2 */
# define MPDDRC_CONF_ARBITER_RQ_WD_P3 (1 << 11) /* Bit 11: Request or Word from Port 3 */
# define MPDDRC_CONF_ARBITER_RQ_WD_P4 (1 << 12) /* Bit 12: Request or Word from Port 4 */
# define MPDDRC_CONF_ARBITER_RQ_WD_P5 (1 << 13) /* Bit 13: Request or Word from Port 5 */
# define MPDDRC_CONF_ARBITER_RQ_WD_P6 (1 << 14) /* Bit 14: Request or Word from Port 6 */
# define MPDDRC_CONF_ARBITER_RQ_WD_P7 (1 << 15) /* Bit 15: Request or Word from Port 7 */
#define MPDDRC_CONF_ARBITER_MA_PR_P(n) (1 << ((n)+16)) /* Bits 16-23: Master or Software Provide Information */
# define MPDDRC_CONF_ARBITER_MA_PR_P0 (1 << 16) /* Bit 16: Master or Software Provide Information */
# define MPDDRC_CONF_ARBITER_MA_PR_P1 (1 << 17) /* Bit 17: Master or Software Provide Information */
# define MPDDRC_CONF_ARBITER_MA_PR_P2 (1 << 18) /* Bit 18: Master or Software Provide Information */
# define MPDDRC_CONF_ARBITER_MA_PR_P3 (1 << 19) /* Bit 19: Master or Software Provide Information */
# define MPDDRC_CONF_ARBITER_MA_PR_P4 (1 << 20) /* Bit 20: Master or Software Provide Information */
# define MPDDRC_CONF_ARBITER_MA_PR_P5 (1 << 21) /* Bit 21: Master or Software Provide Information */
# define MPDDRC_CONF_ARBITER_MA_PR_P6 (1 << 22) /* Bit 22: Master or Software Provide Information */
# define MPDDRC_CONF_ARBITER_MA_PR_P7 (1 << 23) /* Bit 23: Master or Software Provide Information */
/* MPDDRC Time-out Port 0/1/2/3 Register */ /* MPDDRC Time-out Port 0/1/2/3 Register */
#define MPDDRC_TIMEOUT_
#define MPDDRC_TIMEOUT_TIMEOUT_P_SHIFT(n) ((n)<<4) /* Time-out for Port n, n=0..7 */
#define MPDDRC_TIMEOUT_TIMEOUT_P_MASK(n) (15 << MPDDRC_TIMEOUT_TIMEOUT_P_SHIFT(n))
# define MPDDRC_TIMEOUT_TIMEOUT_P(n,v) ((uint32_t)(v) << MPDDRC_TIMEOUT_TIMEOUT_P_SHIFT(n))
# define MPDDRC_TIMEOUT_TIMEOUT_P0_SHIFT (0) /* Bits 4-7: Time-out for Port 0 */
# define MPDDRC_TIMEOUT_TIMEOUT_P0_MASK (15 << MPDDRC_TIMEOUT_TIMEOUT_P0_SHIFT)
# define MPDDRC_TIMEOUT_TIMEOUT_P0(n) ((uint32_t)(n) << MPDDRC_TIMEOUT_TIMEOUT_P0_SHIFT)
# define MPDDRC_TIMEOUT_TIMEOUT_P1_SHIFT (4) /* Bits 0-3: Time-out for Port 1 */
# define MPDDRC_TIMEOUT_TIMEOUT_P1_MASK (15 << MPDDRC_TIMEOUT_TIMEOUT_P1_SHIFT)
# define MPDDRC_TIMEOUT_TIMEOUT_P1(n) ((uint32_t)(n) << MPDDRC_TIMEOUT_TIMEOUT_P1_SHIFT)
# define MPDDRC_TIMEOUT_TIMEOUT_P2_SHIFT (8) /* Bits 8-7: Time-out for Port 2 */
# define MPDDRC_TIMEOUT_TIMEOUT_P2_MASK (15 << MPDDRC_TIMEOUT_TIMEOUT_P2_SHIFT)
# define MPDDRC_TIMEOUT_TIMEOUT_P2(n) ((uint32_t)(n) << MPDDRC_TIMEOUT_TIMEOUT_P2_SHIFT)
# define MPDDRC_TIMEOUT_TIMEOUT_P3_SHIFT (12) /* Bits 12-15: Time-out for Port 3 */
# define MPDDRC_TIMEOUT_TIMEOUT_P3_MASK (15 << MPDDRC_TIMEOUT_TIMEOUT_P3_SHIFT)
# define MPDDRC_TIMEOUT_TIMEOUT_P3(n) ((uint32_t)(n) << MPDDRC_TIMEOUT_TIMEOUT_P3_SHIFT)
# define MPDDRC_TIMEOUT_TIMEOUT_P4_SHIFT (16) /* Bits 16-19: Time-out for Port 4 */
# define MPDDRC_TIMEOUT_TIMEOUT_P4_MASK (15 << MPDDRC_TIMEOUT_TIMEOUT_P4_SHIFT)
# define MPDDRC_TIMEOUT_TIMEOUT_P4(n) ((uint32_t)(n) << MPDDRC_TIMEOUT_TIMEOUT_P4_SHIFT)
# define MPDDRC_TIMEOUT_TIMEOUT_P5_SHIFT (20) /* Bits 20-23: Time-out for Port 5 */
# define MPDDRC_TIMEOUT_TIMEOUT_P5_MASK (15 << MPDDRC_TIMEOUT_TIMEOUT_P5_SHIFT)
# d efine MPDDRC_TIMEOUT_TIMEOUT_P5(n) ((uint32_t)(n) << MPDDRC_TIMEOUT_TIMEOUT_P5_SHIFT)
# define MPDDRC_TIMEOUT_TIMEOUT_P6_SHIFT (24) /* Bits 24-27: Time-out for Port 6 */
# define MPDDRC_TIMEOUT_TIMEOUT_P6_MASK (15 << MPDDRC_TIMEOUT_TIMEOUT_P6_SHIFT)
# define MPDDRC_TIMEOUT_TIMEOUT_P6(n) ((uint32_t)(n) << MPDDRC_TIMEOUT_TIMEOUT_P6_SHIFT)
# define MPDDRC_TIMEOUT_TIMEOUT_P7_SHIFT (28) /* Bits 28-31: Time-out for Port 7 */
# define MPDDRC_TIMEOUT_TIMEOUT_P7_MASK (15 << MPDDRC_TIMEOUT_TIMEOUT_P7_SHIFT)
# define MPDDRC_TIMEOUT_TIMEOUT_P7(n) ((uint32_t)(n) << MPDDRC_TIMEOUT_TIMEOUT_P7_SHIFT)
/* MPDDRC Request Port 0/1/2/3 Register */ /* MPDDRC Request Port 0/1/2/3 Register */
#define MPDDRC_REQ_PORT_0123_
#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P_SHIFT(n) ((n)<<8) /* Number of Requests/Words/Allocation from Port n, n=0..3 */
#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P_MASK(n) (0xff << PDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P_SHIFT(n))
# define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P(n,v) ((uint32_t)(v) << PDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P_SHIFT(n))
# define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_SHIFT (0) /* Bits 0-7: Number of Requests/Words/Allocation from Port 0 */
# define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_MASK (0xff << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_SHIFT)
# define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0(n) ((uint32_t)(n) << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_SHIFT)
# define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1_SHIFT (8) /* Bits 8-15: Number of Requests/Words/Allocation from Port 1 */
# define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1_MASK (0xff << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1_SHIFT)
# define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1(n) ((uint32_t)(n) << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1_SHIFT)
# define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2_SHIFT (16) /* Bits 16-23: Number of Requests/Words/Allocation from Port 2 */
# define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2_MASK (0xff << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2_SHIFT)
# define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2(n) ((uint32_t)(n) << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2_SHIFT)
# define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3_SHIFT (24) /* Bits 24-31: Number of Requests/Words/Allocation from Port 3 */
# define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3_MASK (0xff << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3_SHIFT)
# define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3(n) ((uint32_t)(n) << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3_SHIFT)
/* MPDDRC Request Port 4/5/6/7 Register */ /* MPDDRC Request Port 4/5/6/7 Register */
#define MPDDRC_REQ_PORT_4567_
#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P_SHIFT(n) ((n)<<8) /* Number of Requests/Words/Allocation from port n, n=4..7 */
#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P_MASK(n) (0xff << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P_SHIFT(n))
# define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P(n,v) ((uint32_t)(v) << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P_SHIFT(n))
# define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_SHIFT (0) /* Bits 0-7: Number of Requests/Words/Allocation from port 4 */
# define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_MASK (0xff << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_SHIFT)
# define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4(n) ((uint32_t)(n) << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_SHIFT)
# define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5_SHIFT (8) /* Bits 8-15: Number of Requests/Words/Allocation from port 5 */
# define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5_MASK (0xff << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5_SHIFT)
# define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5(n) ((uint32_t)(n) << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5_SHIFT)
# define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6_SHIFT (16) /* Bits 16-23: Number of Requests/Words/Allocation from port 6 */
# define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6_MASK (0xff << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6_SHIFT)
# define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6(n) ((uint32_t)(n) << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6_SHIFT)
# define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7_SHIFT (24) /* Bits 24-31: Number of Requests/Words/Allocation from port 7 */
# define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7_MASK (0xff << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7_SHIFT)
# define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7(n) ((uint32_t)(n) << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7_SHIFT)
/* MPDDRC Bandwidth Port 0/1/2/3 Register */ /* MPDDRC Bandwidth Port 0/1/2/3 Register */
#define MPDDRC_BDW_PORT_0123_
#define MPDDRC_BDW_PORT_0123_BDW_P_SHIFT(n) ((n)<<8) /* Current/Maximum Bandwidth from Port n, n=0..3 */
#define MPDDRC_BDW_PORT_0123_BDW_P_MASK(n) (0x7f << PDDRC_BDW_PORT_0123_BDW_P_SHIFT(n))
# define MPDDRC_BDW_PORT_0123_BDW_P(n,v) ((uint32_t)(v) << PDDRC_BDW_PORT_0123_BDW_P_SHIFT(n))
# define MPDDRC_BDW_PORT_0123_BDW_P0_SHIFT (0) /* Bits 0-6: Current/Maximum Bandwidth from Port 0 */
# define MPDDRC_BDW_PORT_0123_BDW_P0_MASK (0x7f << MPDDRC_BDW_PORT_0123_BDW_P0_SHIFT)
# define MPDDRC_BDW_PORT_0123_BDW_P0(n) ((uint32_t)(n) << MPDDRC_BDW_PORT_0123_BDW_P0_SHIFT)
# define MPDDRC_BDW_PORT_0123_BDW_P1_SHIFT (8) /* Bits 8-14: Current/Maximum Bandwidth from Port 1 */
# define MPDDRC_BDW_PORT_0123_BDW_P1_MASK (0x7f << MPDDRC_BDW_PORT_0123_BDW_P1_SHIFT)
# define MPDDRC_BDW_PORT_0123_BDW_P1(n) ((uint32_t)(n) << MPDDRC_BDW_PORT_0123_BDW_P1_SHIFT)
# define MPDDRC_BDW_PORT_0123_BDW_P2_SHIFT (16) /* Bits 16-22: Current/Maximum Bandwidth from Port 2 */
# define MPDDRC_BDW_PORT_0123_BDW_P2_MASK (0x7f << MPDDRC_BDW_PORT_0123_BDW_P2_SHIFT)
# define MPDDRC_BDW_PORT_0123_BDW_P2(n) ((uint32_t)(n) << MPDDRC_BDW_PORT_0123_BDW_P2_SHIFT)
# define MPDDRC_BDW_PORT_0123_BDW_P3_SHIFT (24) /* Bits 24-30: Current/Maximum Bandwidth from Port 3 */
# define MPDDRC_BDW_PORT_0123_BDW_P3_MASK (0x7f << MPDDRC_BDW_PORT_0123_BDW_P3_SHIFT)
# define MPDDRC_BDW_PORT_0123_BDW_P3(n) ((uint32_t)(n) << MPDDRC_BDW_PORT_0123_BDW_P3_SHIFT)
/* MPDDRC Bandwidth Port 4/5/6/7 Register */ /* MPDDRC Bandwidth Port 4/5/6/7 Register */
#define MPDDRC_BDW_PORT_4567_
#define MPDDRC_BDW_PORT_4567_BDW_P_SHIFT(n) ((n)<<8) /* Current/Maximum Bandwidth from Port n, n=4..7 */
#define MPDDRC_BDW_PORT_4567_BDW_P_MASK(n) (0x7f << PDDRC_BDW_PORT_4567_BDW_P_SHIFT(n))
# define MPDDRC_BDW_PORT_4567_BDW_P(n,v) ((uint32_t)(v) << PDDRC_BDW_PORT_4567_BDW_P_SHIFT(n))
# define MPDDRC_BDW_PORT_4567_BDW_P4_SHIFT (0) /* Bits 0-6: Current/Maximum Bandwidth from Port 4 */
# define MPDDRC_BDW_PORT_4567_BDW_P4_MASK (0x7f << MPDDRC_BDW_PORT_4567_BDW_P4_SHIFT)
# define MPDDRC_BDW_PORT_4567_BDW_P4(n) ((uint32_t)(n) << MPDDRC_BDW_PORT_4567_BDW_P4_SHIFT)
# define MPDDRC_BDW_PORT_4567_BDW_P5_SHIFT (8) /* Bits 8-14: Current/Maximum Bandwidth from Port 5 */
# define MPDDRC_BDW_PORT_4567_BDW_P5_MASK (0x7f << MPDDRC_BDW_PORT_4567_BDW_P5_SHIFT)
# define MPDDRC_BDW_PORT_4567_BDW_P5(n) ((uint32_t)(n) << MPDDRC_BDW_PORT_4567_BDW_P5_SHIFT)
# define MPDDRC_BDW_PORT_4567_BDW_P6_SHIFT (16) /* Bits 16-22: Current/Maximum Bandwidth from Port 6 */
# define MPDDRC_BDW_PORT_4567_BDW_P6_MASK (0x7f << MPDDRC_BDW_PORT_4567_BDW_P6_SHIFT)
# define MPDDRC_BDW_PORT_4567_BDW_P6(n) ((uint32_t)(n) << MPDDRC_BDW_PORT_4567_BDW_P6_SHIFT)
# define MPDDRC_BDW_PORT_4567_BDW_P7_SHIFT (24) /* Bits 24-30: Current/Maximum Bandwidth from Port 7 */
# define MPDDRC_BDW_PORT_4567_BDW_P7_MASK (0x7f << MPDDRC_BDW_PORT_4567_BDW_P7_SHIFT)
# define MPDDRC_BDW_PORT_4567_BDW_P7(n) ((uint32_t)(n) << MPDDRC_BDW_PORT_4567_BDW_P7_SHIFT)
/* MPDDRC Read Datapath Register */ /* MPDDRC Read Datapath Register */
#define MPDDRC_RD_DATA_PATH_
/* MPDDRC Smart Adaptation Wrapper 0 Register */ #define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT (0) /* Bits 0-1: Shift Sampling Point of Data */
#define MPDDRC_SAW0_ #define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_MASK (3 << MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT)
/* MPDDRC Smart Adaptation Wrapper 1 Register */ # define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_NONE (0 << MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT) /* Initial sampling point */
#define MPDDRC_SAW1_ # define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_1CYCLE (1 << MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT) /* Sampling shifted by 1 cycle */
/* MPDDRC Smart Adaptation Wrapper 2 Register */ # define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_2CYCLES (2 << MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT) /* Sampling point shifted by 2 cycles */
#define MPDDRC_SAW2_ # define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_3CYCLES (3 << MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT) /* Sampling point shifted by 3 cycles */
/* MPDDRC Smart Adaptation Wrapper 3 Register */
#define MPDDRC_SAW3_ /* MPDDRC Smart Adaptation Wrapper 0-3 Register */
#define MPDDRC_SAW_FLUSH_MAX_SHIFT (0) /* Bits 0-7: Clears FIFO Content */
#define MPDDRC_SAW_FLUSH_MAX_MASK (0xff << MPDDRC_SAW_FLUSH_MAX_SHIFT)
# define MPDDRC_SAW_FLUSH_MAX(n) ((uint32_t)(n) << MPDDRC_SAW_FLUSH_MAX_SHIFT)
#define MPDDRC_SAW_INCR_THRESH_SHIFT (8) /* Bits 8-13: Incremental Threshold */
#define MPDDRC_SAW_INCR_THRESH_MASK (0x3f << MPDDRC_SAW_INCR_THRESH_SHIFT)
# define MPDDRC_SAW_INCR_THRESH_1WORD (1 << MPDDRC_SAW_INCR_THRESH_SHIFT) /* 1 word/dword max */
# define MPDDRC_SAW_INCR_THRESH_2WORDS (2 << MPDDRC_SAW_INCR_THRESH_SHIFT) /* 2 word/dword max */
# define MPDDRC_SAW_INCR_THRESH_4WORDS (4 << MPDDRC_SAW_INCR_THRESH_SHIFT) /* 4 word/dword max */
# define MPDDRC_SAW_INCR_THRESH_8WORDS (8 << MPDDRC_SAW_INCR_THRESH_SHIFT) /* 8 word/dword max */
# define MPDDRC_SAW_INCR_THRESH_16WORDS (16 << MPDDRC_SAW_INCR_THRESH_SHIFT) /* 16 word/dword max */
# define MPDDRC_SAW_INCR_THRESH_32WORDS (21 << MPDDRC_SAW_INCR_THRESH_SHIFT) /* 32 word/dword max */
#define MPDDRC_SAW_PFCH_THRESH_SHIFT (16) /* Bits 16-21: Prefetch Threshold */
#define MPDDRC_SAW_PFCH_THRESH_MASK (0x3f << MPDDRC_SAW_PFCH_THRESH_SHIFT)
# define MPDDRC_SAW_PFCH_THRESH_2WORDS (2 << MPDDRC_SAW_PFCH_THRESH_SHIFT) /* 2 word/dword max */
# define MPDDRC_SAW_PFCH_THRESH_4WORDS (4 << MPDDRC_SAW_PFCH_THRESH_SHIFT) /* 4 word/dword max */
# define MPDDRC_SAW_PFCH_THRESH_8WORDS (8 << MPDDRC_SAW_PFCH_THRESH_SHIFT) /* 8 word/dword max */
/* MPDDRC Write Protect Control Register */ /* MPDDRC Write Protect Control Register */
@ -429,50 +582,109 @@
#define MPDDRC_WPSR_WPVSRC_MASK (0xffff << MPDDRC_WPSR_WPVSRC_SHIFT) #define MPDDRC_WPSR_WPVSRC_MASK (0xffff << MPDDRC_WPSR_WPVSRC_SHIFT)
/* MPDDRC DLL Offset Selection Register */ /* MPDDRC DLL Offset Selection Register */
#define MPDDRC_DLL_OS_
#define MPDDRC_DLL_OS_SELOFF (1 << 0) /* Bit 0: Offset Selection */
/* MPDDRC DLL MASTER Offset Register */ /* MPDDRC DLL MASTER Offset Register */
#define MPDDRC_DLL_MO_
#define MPDDRC_DLL_MO_M0OFF_SHIFT (0) /* Bits 0-7: Master 0 Delay Line Offset */
#define MPDDRC_DLL_MO_M0OFF_MASK (0xff < MPDDRC_DLL_MO_M0OFF_SHIFT)
# define MPDDRC_DLL_MO_M0OFF(n) ((uint32_t)(n) < MPDDRC_DLL_MO_M0OFF_SHIFT)
/* MPDDRC DLL SLAVE Offset 0 Register */ /* MPDDRC DLL SLAVE Offset 0 Register */
#define MPDDRC_DLL_SO0_
#define MPDDRC_DLL_SO0_SOFF_SHIFT(n) (0) /* SLAVEn Delay Line Offset, n=0..3 */
#define MPDDRC_DLL_SO0_SOFF_MASK(n) (0xff < MPDDRC_DLL_SO0_SOFF_SHIFT(n))
# define MPDDRC_DLL_SO0_SOFF(n,v) ((uint32_t)(v) < MPDDRC_DLL_SO0_SOFF_SHIFT(n))
# define MPDDRC_DLL_SO0_S0OFF_SHIFT (0) /* Bits 0-7: SLAVE0 Delay Line Offset */
# define MPDDRC_DLL_SO0_S0OFF_MASK (0xff < MPDDRC_DLL_SO0_S0OFF_SHIFT)
# define MPDDRC_DLL_SO0_S0OFF(n) ((uint32_t)(n) < MPDDRC_DLL_SO0_S0OFF_SHIFT)
# define MPDDRC_DLL_SO0_S1OFF_SHIFT (8) /* Bits 8-15: SLAVE1 Delay Line Offset */
# define MPDDRC_DLL_SO0_S1OFF_MASK (0xff < MPDDRC_DLL_SO0_S1OFF_SHIFT)
# define MPDDRC_DLL_SO0_S1OFF(n) ((uint32_t)(n) < MPDDRC_DLL_SO0_S1OFF_SHIFT)
# define MPDDRC_DLL_SO0_S2OFF_SHIFT (16) /* Bits 16-23: SLAVE2 Delay Line Offset */
# define MPDDRC_DLL_SO0_S2OFF_MASK (0xff < MPDDRC_DLL_SO0_S2OFF_SHIFT)
# define MPDDRC_DLL_SO0_S2OFF(n) ((uint32_t)(n) < MPDDRC_DLL_SO0_S2OFF_SHIFT)
# define MPDDRC_DLL_SO0_S3OFF_SHIFT (24) /* Bits 24-31: SLAVE3 Delay Line Offset */
# define MPDDRC_DLL_SO0_S3OFF_MASK (0xff < MPDDRC_DLL_SO0_S3OFF_SHIFT)
# define MPDDRC_DLL_SO0_S3OFF(n) ((uint32_t)(n) < MPDDRC_DLL_SO0_S3OFF_SHIFT)
/* MPDDRC DLL SLAVE Offset 1 Register */ /* MPDDRC DLL SLAVE Offset 1 Register */
#define MPDDRC_DLL_SO1_
#define MPDDRC_DLL_SO1_SOFF_SHIFT(n) (0) /* SLAVEn Delay Line Offset, n=4..7 */
#define MPDDRC_DLL_SO1_SOFF_MASK(n) (0xff < MPDDRC_DLL_SO1_SOFF_SHIFT(n))
# define MPDDRC_DLL_SO1_SOFF(n,v) ((uint32_t)(v) < MPDDRC_DLL_SO1_SOFF_SHIFT(n))
# define MPDDRC_DLL_SO1_S4OFF_SHIFT (0) /* Bits 0-7: SLAVE4 Delay Line Offset */
# define MPDDRC_DLL_SO1_S4OFF_MASK (0xff < MPDDRC_DLL_SO1_S4OFF_SHIFT)
# define MPDDRC_DLL_SO1_S4OFF(n) ((uint32_t)(n) < MPDDRC_DLL_SO1_S4OFF_SHIFT)
# define MPDDRC_DLL_SO1_S5OFF_SHIFT (8) /* Bits 8-15: SLAVE5 Delay Line Offset */
# define MPDDRC_DLL_SO1_S5OFF_MASK (0xff < MPDDRC_DLL_SO1_S5OFF_SHIFT)
# define MPDDRC_DLL_SO1_S5OFF(n) ((uint32_t)(n) < MPDDRC_DLL_SO1_S5OFF_SHIFT)
# define MPDDRC_DLL_SO1_S6OFF_SHIFT (16) /* Bits 16-23: SLAVE6 Delay Line Offset */
# define MPDDRC_DLL_SO1_S6OFF_MASK (0xff < MPDDRC_DLL_SO1_S6OFF_SHIFT)
# define MPDDRC_DLL_SO1_S6OFF(n) ((uint32_t)(n) < MPDDRC_DLL_SO1_S6OFF_SHIFT)
# define MPDDRC_DLL_SO1_S7OFF_SHIFT (24) /* Bits 24-31: SLAVE7 Delay Line Offset */
# define MPDDRC_DLL_SO1_S7OFF_MASK (0xff < MPDDRC_DLL_SO1_S7OFF_SHIFT)
# define MPDDRC_DLL_SO1_S7OFF(n) ((uint32_t)(n) < MPDDRC_DLL_SO1_S7OFF_SHIFT)
/* MPDDRC DLL CLKWR Offset Register */ /* MPDDRC DLL CLKWR Offset Register */
#define MPDDRC_DLL_WRO_
#define MPDDRC_DLL_WRO_WROFF_SHIFT(n) (0) /* CLKWRn Delay Line Offset, n=0..3 */
#define MPDDRC_DLL_WRO_WROFF_MASK(n) (0xff < MPDDRC_DLL_WRO_WROFF_SHIFT(n))
# define MPDDRC_DLL_WRO_WROFF(n,v) ((uint32_t)(n) < MPDDRC_DLL_WRO_WROFF_SHIFT(n))
# define MPDDRC_DLL_WRO_WR0OFF_SHIFT (0) /* Bits 0-7: CLKWR0 Delay Line Offset */
# define MPDDRC_DLL_WRO_WR0OFF_MASK (0xff < MPDDRC_DLL_WRO_WR0OFF_SHIFT)
# define MPDDRC_DLL_WRO_WR0OFF(n) ((uint32_t)(n) < MPDDRC_DLL_WRO_WR0OFF_SHIFT)
# define MPDDRC_DLL_WRO_WR1OFF_SHIFT (8) /* Bits 8-15: CLKWR1 Delay Line Offset */
# define MPDDRC_DLL_WRO_WR1OFF_MASK (0xff < MPDDRC_DLL_WRO_WR1OFF_SHIFT)
# define MPDDRC_DLL_WRO_WR1OFF(n) ((uint32_t)(n) < MPDDRC_DLL_WRO_WR1OFF_SHIFT)
# define MPDDRC_DLL_WRO_WR2OFF_SHIFT (16) /* Bits 16-23: CLKWR2 Delay Line Offset */
# define MPDDRC_DLL_WRO_WR2OFF_MASK (0xff < MPDDRC_DLL_WRO_WR2OFF_SHIFT)
# define MPDDRC_DLL_WRO_WR2OFF(n) ((uint32_t)(n) < MPDDRC_DLL_WRO_WR2OFF_SHIFT)
# define MPDDRC_DLL_WRO_WR3OFF_SHIFT (24) /* Bits 24-31: CLKWR3 Delay Line Offset */
# define MPDDRC_DLL_WRO_WR3OFF_MASK (0xff < MPDDRC_DLL_WRO_WR3OFF_SHIFT)
# define MPDDRC_DLL_WRO_WR3OFF(n) ((uint32_t)(n) < MPDDRC_DLL_WRO_WR3OFF_SHIFT)
/* MPDDRC DLL CLKAD Offset Register */ /* MPDDRC DLL CLKAD Offset Register */
#define MPDDRC_DLL_ADO_
/* MPDDRC DLL Status MASTER0 Register */ #define MPDDRC_DLL_ADO_ADOFF_SHIFT (0) /* Bits 0-7: CLKAD Delay Line Offset */
#define MPDDRC_DLL_SM0_ #define MPDDRC_DLL_ADO_ADOFF_MASK (0xff < MPDDRC_DLL_ADO_ADOFF_SHIFT)
/* MPDDRC DLL Status MASTER1 Register */ # define MPDDRC_DLL_ADO_ADOFF(n) ((uint32_t)(n) < MPDDRC_DLL_ADO_ADOFF_SHIFT)
#define MPDDRC_DLL_SM1_
/* MPDDRC DLL Status MASTER2 Register */ /* MPDDRC DLL Status MASTER 0..3 Register */
#define MPDDRC_DLL_SM2_
/* MPDDRC DLL Status MASTER3 Register */ #define MPDDRC_DLL_SM_MDINC (1 << 0) /* Bit 0: MASTER Delay Increment */
#define MPDDRC_DLL_SM3_ #define MPDDRC_DLL_SM_MDDEC (1 << 1) /* Bit 1: MASTER Delay Decrement */
/* MPDDRC DLL Status SLAVE0 Register */ #define MPDDRC_DLL_SM_MDOVF (1 << 2) /* Bit 2: MASTER Delay Overflow Flag */
#define MPDDRC_DLL_SSL0_ #define MPDDRC_DLL_SM_MDLVAL_SHIFT (8) /* Bits 8-15: MASTER Delay Lock Value */
/* MPDDRC DLL Status SLAVE1 Register */ #define MPDDRC_DLL_SM_MDLVAL_MASK (0xff < MPDDRC_DLL_SM_MDLVAL_SHIFT)
#define MPDDRC_DLL_SSL1_ # define MPDDRC_DLL_SM_MDLVAL(n) ((uint32_t)(n) < MPDDRC_DLL_SM_MDLVAL_SHIFT)
/* MPDDRC DLL Status SLAVE2 Register */ #define MPDDRC_DLL_SM_MDCNT_SHIFT (20) /* Bits 20-27: MASTER Delay Counter Value */
#define MPDDRC_DLL_SSL2_ #define MPDDRC_DLL_SM_MDCNT_MASK (0xff < MPDDRC_DLL_SM_MDCNT_SHIFT)
/* MPDDRC DLL Status SLAVE3 Register */ # define MPDDRC_DLL_SM_MDCNT(n) ((uint32_t)(n) < MPDDRC_DLL_SM_MDCNT_SHIFT)
#define MPDDRC_DLL_SSL3_
/* MPDDRC DLL Status SLAVE4 Register */ /* MPDDRC DLL Status SLAVE 0..7 Register */
#define MPDDRC_DLL_SSL4_
/* MPDDRC DLL Status SLAVE5 Register */ #define MPDDRC_DLL_SSL_SDCOVF (1 << 0) /* Bit 0: SLAVE Delay Correction Overflow Flag */
#define MPDDRC_DLL_SSL5_ #define MPDDRC_DLL_SSL_SDCUDF (1 << 1) /* Bit 1: SLAVE Delay Correction Underflow Flag */
/* MPDDRC DLL Status SLAVE6 Register */ #define MPDDRC_DLL_SSL_SDERF (1 << 2) /* Bit 2: SLAVE Delay Correction Error Flag */
#define MPDDRC_DLL_SSL6_ #define MPDDRC_DLL_SSL_SDCNT_SHIFT (8) /* Bits 8-15: SLAVE Delay Counter Value */
/* MPDDRC DLL Status SLAVE7 Register */ #define MPDDRC_DLL_SSL_SDCNT_MASK (0xff < MPDDRC_DLL_SSL_SDCNT_SHIFT)
#define MPDDRC_DLL_SSL7_ # define MPDDRC_DLL_SSL_SDCNT(n) ((uint32_t)(n) < MPDDRC_DLL_SSL_SDCNT_SHIFT)
/* MPDDRC DLL Status CLKWR0 Register */ #define MPDDRC_DLL_SSL_SDCVAL_SHIFT (20) /* Bits 20-27: SLAVE Delay Correction Value */
#define MPDDRC_DLL_SWR0_ #define MPDDRC_DLL_SSL_SDCVAL_MASK (0xff < MPDDRC_DLL_SSL_SDCVAL_SHIFT)
/* MPDDRC DLL Status CLKWR1 Register */ # define MPDDRC_DLL_SSL_SDCVAL(n) ((uint32_t)(n) < MPDDRC_DLL_SSL_SDCVAL_SHIFT)
#define MPDDRC_DLL_SWR1_
/* MPDDRC DLL StatusCLKWR2 Register */ /* MPDDRC DLL Status CLKWR 0..3 Register */
#define MPDDRC_DLL_SWR2_
/* MPDDRC DLL Status CLKWR3 Register */ #define MPDDRC_DLL_SWR_WRDCNT_SHIFT (0) /* Bits 0-7: CLKWRx Delay Counter Value */
#define MPDDRC_DLL_SWR3_ #define MPDDRC_DLL_SWR_WRDCNT_MASK (0xff < MPDDRC_DLL_SWR_WRDCNT_SHIFT)
# define MPDDRC_DLL_SWR_WRDCNT(n) ((uint32_t)(n) < MPDDRC_DLL_SWR_WRDCNT_SHIFT)
/* MPDDRC DLL Status CLKAD Register */ /* MPDDRC DLL Status CLKAD Register */
#define MPDDRC_DLL_SAD_
#define MPDDRC_DLL_SAD_ADDCNT_SHIFT (0) /* Bits 0-7: CLKAD Delay Counter Value */
#define MPDDRC_DLL_SAD_ADDCNT_MASK (0xff < MPDDRC_DLL_SAD_ADDCNT_SHIFT)
# define MPDDRC_DLL_SAD_ADDCNT(n) ((uint32_t)(n) < MPDDRC_DLL_SAD_ADDCNT_SHIFT)
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAMA5D4X_MPDDRC_H */ #endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAMA5D4X_MPDDRC_H */