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STM32 fixes for F4 32-bit timers

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4300 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-01-13 02:49:10 +00:00
parent cd567f546a
commit f158e56fca
6 changed files with 615 additions and 409 deletions
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7
ChangeLog
View File

@ -2312,7 +2312,7 @@
* configs/olimex-lpc1766stk/src/up_leds.c: Add new interfaces so that is * configs/olimex-lpc1766stk/src/up_leds.c: Add new interfaces so that is
CONFIG_ARCH_LEDS are not set, the LEDs may be controlled from application CONFIG_ARCH_LEDS are not set, the LEDs may be controlled from application
logic. logic.
* configs/olimex-lpc1766stk/src/up_buttons.c: Add support form the buttons * configs/olimex-lpc1766stk/src/up_buttons.c: Add support for the buttons
on the Olimex LPC1766-STK board. on the Olimex LPC1766-STK board.
* Makefile: Added 'apps_clean' and 'apps_distclean' target to simplify * Makefile: Added 'apps_clean' and 'apps_distclean' target to simplify
managing the state of the application directory while in the NuttX directory managing the state of the application directory while in the NuttX directory
@ -2361,4 +2361,7 @@
(Contributed by Mike Smith). (Contributed by Mike Smith).
* fs/fat/fs_fat32util.c: On a failure to recognize a FAT file system, the * fs/fat/fs_fat32util.c: On a failure to recognize a FAT file system, the
mount logic should return -EINVAL, not -ENODEV. mount logic should return -EINVAL, not -ENODEV.
* arch/arm/src/stm32/stm32_tim.c: Support for STM32 F4 32-bit timers
(Contributed by Mikhail Bychek)
* lib/stdio/lib_vsprintf.c: Add support for fixed-size fields with floating
point numbers (Contributed by Mikhail Bychek)

429
arch/arm/src/stm32/stm32_tim.c
View File

@ -6,7 +6,7 @@
* *
* With modifications and updates by: * With modifications and updates by:
* *
* Copyright (C) 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -139,60 +139,81 @@
* Private Types * Private Types
************************************************************************************/ ************************************************************************************/
/** TIM Device Structure /* TIM Device Structure */
*/
struct stm32_tim_priv_s { struct stm32_tim_priv_s
{
struct stm32_tim_ops_s *ops; struct stm32_tim_ops_s *ops;
stm32_tim_mode_t mode; stm32_tim_mode_t mode;
uint32_t base; /** TIMn base address */ uint32_t base; /* TIMn base address */
}; };
/************************************************************************************ /************************************************************************************
* Private Functions * Private Functions
************************************************************************************/ ************************************************************************************/
/** Get register value by offset */ /* Get a 16-bit register value by offset */
static inline uint16_t stm32_tim_getreg(FAR struct stm32_tim_dev_s *dev, uint8_t offset)
static inline uint16_t stm32_getreg16(FAR struct stm32_tim_dev_s *dev, uint8_t offset)
{ {
return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset);
} }
/** Put register value by offset */ /* Put a 16-bit register value by offset */
static inline void stm32_tim_putreg(FAR struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value)
static inline void stm32_putreg16(FAR struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value)
{ {
//printf("putreg(%8x)=%4x\n", ((struct stm32_tim_priv_s *)dev)->base + offset, value );
putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset);
} }
/** Modify register value by offset */ /* Modify a 16-bit register value by offset */
static inline void stm32_tim_modifyreg(FAR struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits)
static inline void stm32_modifyreg16(FAR struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits)
{ {
modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits);
} }
/* Get a 32-bit register value by offset. This applies only for the STM32 F4
* 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5.
*/
static inline uint32_t stm32_getreg32(FAR struct stm32_tim_dev_s *dev, uint8_t offset)
{
return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset);
}
/* Put a 32-bit register value by offset. This applies only for the STM32 F4
* 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5.
*/
static inline void stm32_putreg32(FAR struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value)
{
putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset);
}
static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev) static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev)
{ {
uint16_t val = stm32_tim_getreg(dev, STM32_BTIM_EGR_OFFSET); uint16_t val = stm32_getreg16(dev, STM32_BTIM_EGR_OFFSET);
val |= ATIM_EGR_UG; val |= ATIM_EGR_UG;
stm32_tim_putreg(dev, STM32_BTIM_EGR_OFFSET, val); stm32_putreg16(dev, STM32_BTIM_EGR_OFFSET, val);
} }
static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev) static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev)
{ {
uint16_t val = stm32_tim_getreg(dev, STM32_BTIM_CR1_OFFSET); uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET);
val |= ATIM_CR1_CEN; val |= ATIM_CR1_CEN;
stm32_tim_reload_counter(dev); stm32_tim_reload_counter(dev);
stm32_tim_putreg(dev, STM32_BTIM_CR1_OFFSET, val); stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
} }
static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev) static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev)
{ {
uint16_t val = stm32_tim_getreg(dev, STM32_BTIM_CR1_OFFSET); uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET);
val &= ~ATIM_CR1_CEN; val &= ~ATIM_CR1_CEN;
stm32_tim_putreg(dev, STM32_BTIM_CR1_OFFSET, val); stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
} }
/** Reset timer into system default state, but do not affect output/input pins */ /* Reset timer into system default state, but do not affect output/input pins */
static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev) static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev)
{ {
((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED;
@ -201,12 +222,14 @@ static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev)
static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode)
{ {
/** \todo Added support for input capture and bipolar dual outputs for TIM8 */ /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */
if (mode & STM32_TIM_CH_MODE_MASK) { if (mode & STM32_TIM_CH_MODE_MASK)
{
stm32_configgpio(cfg); stm32_configgpio(cfg);
} }
else { else
{
stm32_unconfiggpio(cfg); stm32_unconfiggpio(cfg);
} }
} }
@ -222,7 +245,9 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
ASSERT(dev); ASSERT(dev);
/* Disable Timer? */ /* Disable Timer? */
if (freq == 0) {
if (freq == 0)
{
stm32_tim_disable(dev); stm32_tim_disable(dev);
return 0; return 0;
} }
@ -230,27 +255,39 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
#if STM32_NATIM > 0 #if STM32_NATIM > 0
if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE)
{
prescaler = STM32_TIM18_FREQUENCY / freq; prescaler = STM32_TIM18_FREQUENCY / freq;
}
else else
#endif #endif
{
prescaler = STM32_TIM27_FREQUENCY / freq; prescaler = STM32_TIM27_FREQUENCY / freq;
}
/* we need to decrement value for '1', but only, if we are allowed to /* We need to decrement value for '1', but only, if we are allowed to
* not to cause underflow. Check for overflow. * not to cause underflow. Check for overflow.
*/ */
if (prescaler > 0) prescaler--;
if (prescaler > 0xFFFF) prescaler = 0xFFFF;
stm32_tim_putreg(dev, STM32_BTIM_PSC_OFFSET, prescaler); if (prescaler > 0)
{
prescaler--;
}
if (prescaler > 0xffff)
{
prescaler = 0xffff;
}
stm32_putreg16(dev, STM32_BTIM_PSC_OFFSET, prescaler);
stm32_tim_enable(dev); stm32_tim_enable(dev);
return prescaler; return prescaler;
} }
static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, uint16_t period) static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, uint32_t period)
{ {
ASSERT(dev); ASSERT(dev);
stm32_tim_putreg(dev, STM32_BTIM_ARR_OFFSET, period); stm32_putreg32(dev, STM32_BTIM_ARR_OFFSET, period);
} }
static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, int (*handler)(int irq, void *context), int source) static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, int (*handler)(int irq, void *context), int source)
@ -260,44 +297,63 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, int (*handler)(int
ASSERT(dev); ASSERT(dev);
ASSERT(source==0); ASSERT(source==0);
switch( ((struct stm32_tim_priv_s *)dev)->base ) { switch (((struct stm32_tim_priv_s *)dev)->base)
{
#if CONFIG_STM32_TIM2 #if CONFIG_STM32_TIM2
case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; case STM32_TIM2_BASE:
vectorno = STM32_IRQ_TIM2;
break;
#endif #endif
#if CONFIG_STM32_TIM3 #if CONFIG_STM32_TIM3
case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; case STM32_TIM3_BASE:
vectorno = STM32_IRQ_TIM3;
break;
#endif #endif
#if CONFIG_STM32_TIM4 #if CONFIG_STM32_TIM4
case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; case STM32_TIM4_BASE:
vectorno = STM32_IRQ_TIM4;
break;
#endif #endif
#if CONFIG_STM32_TIM5 #if CONFIG_STM32_TIM5
case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; case STM32_TIM5_BASE:
vectorno = STM32_IRQ_TIM5;
break;
#endif #endif
#if STM32_NBTIM > 0 #if STM32_NBTIM > 0
#if CONFIG_STM32_TIM6 #if CONFIG_STM32_TIM6
case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; case STM32_TIM6_BASE:
vectorno = STM32_IRQ_TIM6;
break;
#endif #endif
#endif #endif
#if STM32_NBTIM > 1 #if STM32_NBTIM > 1
#if CONFIG_STM32_TIM7 #if CONFIG_STM32_TIM7
case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; case STM32_TIM7_BASE:
vectorno = STM32_IRQ_TIM7;
break;
#endif #endif
#endif #endif
#if STM32_NATIM > 0 #if STM32_NATIM > 0
/** \todo add support for multiple sources and callbacks */ /* TODO: add support for multiple sources and callbacks */
#if CONFIG_STM32_TIM1 #if CONFIG_STM32_TIM1
case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; case STM32_TIM1_BASE:
vectorno = STM32_IRQ_TIM1UP;
break;
#endif #endif
#if CONFIG_STM32_TIM8 #if CONFIG_STM32_TIM8
case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break; case STM32_TIM8_BASE:
vectorno = STM32_IRQ_TIM8UP;
break;
#endif #endif
#endif #endif
default: return ERROR; default:
return ERROR;
} }
/* Disable interrupt when callback is removed */ /* Disable interrupt when callback is removed */
if (!handler) { if (!handler)
{
up_disable_irq(vectorno); up_disable_irq(vectorno);
irq_detach(vectorno); irq_detach(vectorno);
return OK; return OK;
@ -314,18 +370,18 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, int (*handler)(int
static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source) static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source)
{ {
ASSERT(dev); ASSERT(dev);
stm32_tim_modifyreg(dev, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE); stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE);
} }
static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source) static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source)
{ {
ASSERT(dev); ASSERT(dev);
stm32_tim_modifyreg(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0); stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0);
} }
static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source) static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source)
{ {
stm32_tim_putreg(dev, STM32_BTIM_SR_OFFSET, ~ATIM_SR_UIF); stm32_putreg16(dev, STM32_BTIM_SR_OFFSET, ~ATIM_SR_UIF);
} }
/************************************************************************************ /************************************************************************************
@ -349,13 +405,16 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
|| ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE
#endif #endif
#if STM32_NBTIM > 0 #if STM32_NBTIM > 0
) return ERROR; )
{
return ERROR;
}
#endif #endif
/* Decode operational modes */ /* Decode operational modes */
switch(mode & STM32_TIM_MODE_MASK) { switch (mode & STM32_TIM_MODE_MASK)
{
case STM32_TIM_MODE_DISABLED: case STM32_TIM_MODE_DISABLED:
val = 0; val = 0;
break; break;
@ -379,14 +438,15 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
} }
stm32_tim_reload_counter(dev); stm32_tim_reload_counter(dev);
stm32_tim_putreg(dev, STM32_BTIM_CR1_OFFSET, val); stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
#if STM32_NATIM > 0 #if STM32_NATIM > 0
/* Advanced registers require Main Output Enable */ /* Advanced registers require Main Output Enable */
if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE)
stm32_tim_modifyreg(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); {
stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE);
} }
#endif #endif
@ -396,7 +456,7 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel, stm32_tim_channel_t mode) static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel, stm32_tim_channel_t mode)
{ {
uint16_t ccmr_val = 0; uint16_t ccmr_val = 0;
uint16_t ccer_val = stm32_tim_getreg(dev, STM32_GTIM_CCER_OFFSET); uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET);
uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET;
ASSERT(dev); ASSERT(dev);
@ -420,13 +480,16 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
|| ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE
#endif #endif
#if STM32_NBTIM > 0 #if STM32_NBTIM > 0
) return ERROR; )
{
return ERROR;
}
#endif #endif
/* Decode configuration */ /* Decode configuration */
switch(mode & STM32_TIM_CH_MODE_MASK) { switch (mode & STM32_TIM_CH_MODE_MASK)
{
case STM32_TIM_CH_DISABLED: case STM32_TIM_CH_DISABLED:
break; break;
@ -442,71 +505,110 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
/* Set polarity */ /* Set polarity */
if (mode & STM32_TIM_CH_POLARITY_NEG) if (mode & STM32_TIM_CH_POLARITY_NEG)
{
ccer_val |= ATIM_CCER_CC1P << (channel << 2); ccer_val |= ATIM_CCER_CC1P << (channel << 2);
}
/* define its position (shift) and get register offset */ /* Define its position (shift) and get register offset */
if (channel & 1) ccmr_val <<= 8; if (channel & 1)
if (channel > 1) ccmr_offset = STM32_GTIM_CCMR2_OFFSET; {
ccmr_val <<= 8;
}
stm32_tim_putreg(dev, ccmr_offset, ccmr_val); if (channel > 1)
stm32_tim_putreg(dev, STM32_GTIM_CCER_OFFSET, ccer_val); {
ccmr_offset = STM32_GTIM_CCMR2_OFFSET;
}
stm32_putreg16(dev, ccmr_offset, ccmr_val);
stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val);
/* set GPIO */ /* set GPIO */
switch( ((struct stm32_tim_priv_s *)dev)->base ) { switch (((struct stm32_tim_priv_s *)dev)->base)
{
#if CONFIG_STM32_TIM2 #if CONFIG_STM32_TIM2
case STM32_TIM2_BASE: case STM32_TIM2_BASE:
switch(channel) { switch (channel)
{
#if defined(GPIO_TIM2_CH1OUT) #if defined(GPIO_TIM2_CH1OUT)
case 0: stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; case 0:
stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode);
break;
#endif #endif
#if defined(GPIO_TIM2_CH2OUT) #if defined(GPIO_TIM2_CH2OUT)
case 1: stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; case 1:
stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode);
break;
#endif #endif
#if defined(GPIO_TIM2_CH3OUT) #if defined(GPIO_TIM2_CH3OUT)
case 2: stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; case 2:
stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode);
break;
#endif #endif
#if defined(GPIO_TIM2_CH4OUT) #if defined(GPIO_TIM2_CH4OUT)
case 3: stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; case 3:
stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode);
break;
#endif #endif
default: return ERROR; default:
return ERROR;
} }
break; break;
#endif #endif
#if CONFIG_STM32_TIM3 #if CONFIG_STM32_TIM3
case STM32_TIM3_BASE: case STM32_TIM3_BASE:
switch(channel) { switch (channel)
{
#if defined(GPIO_TIM3_CH1OUT) #if defined(GPIO_TIM3_CH1OUT)
case 0: stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break; case 0:
stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode);
break;
#endif #endif
#if defined(GPIO_TIM3_CH2OUT) #if defined(GPIO_TIM3_CH2OUT)
case 1: stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break; case 1:
stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode);
break;
#endif #endif
#if defined(GPIO_TIM3_CH3OUT) #if defined(GPIO_TIM3_CH3OUT)
case 2: stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break; case 2:
stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode);
break;
#endif #endif
#if defined(GPIO_TIM3_CH4OUT) #if defined(GPIO_TIM3_CH4OUT)
case 3: stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break; case 3:
stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode);
break;
#endif #endif
default: return ERROR; default:
return ERROR;
} }
break; break;
#endif #endif
#if CONFIG_STM32_TIM4 #if CONFIG_STM32_TIM4
case STM32_TIM4_BASE: case STM32_TIM4_BASE:
switch(channel) { switch (channel)
{
#if defined(GPIO_TIM4_CH1OUT) #if defined(GPIO_TIM4_CH1OUT)
case 0: stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break; case 0:
stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode);
break;
#endif #endif
#if defined(GPIO_TIM4_CH2OUT) #if defined(GPIO_TIM4_CH2OUT)
case 1: stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break; case 1:
stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode);
break;
#endif #endif
#if defined(GPIO_TIM4_CH3OUT) #if defined(GPIO_TIM4_CH3OUT)
case 2: stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break; case 2:
stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode);
break;
#endif #endif
#if defined(GPIO_TIM4_CH4OUT) #if defined(GPIO_TIM4_CH4OUT)
case 3: stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break; case 3:
stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode);
break;
#endif #endif
default: return ERROR; default: return ERROR;
} }
@ -514,18 +616,27 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
#endif #endif
#if CONFIG_STM32_TIM5 #if CONFIG_STM32_TIM5
case STM32_TIM5_BASE: case STM32_TIM5_BASE:
switch(channel) { switch (channel)
{
#if defined(GPIO_TIM5_CH1OUT) #if defined(GPIO_TIM5_CH1OUT)
case 0: stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break; case 0:
stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode);
break;
#endif #endif
#if defined(GPIO_TIM5_CH2OUT) #if defined(GPIO_TIM5_CH2OUT)
case 1: stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break; case 1:
stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode);
break;
#endif #endif
#if defined(GPIO_TIM5_CH3OUT) #if defined(GPIO_TIM5_CH3OUT)
case 2: stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break; case 2:
stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode);
break;
#endif #endif
#if defined(GPIO_TIM5_CH4OUT) #if defined(GPIO_TIM5_CH4OUT)
case 3: stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break; case 3:
stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode);
break;
#endif #endif
default: return ERROR; default: return ERROR;
} }
@ -535,18 +646,23 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
#if STM32_NATIM > 0 #if STM32_NATIM > 0
#if CONFIG_STM32_TIM1 #if CONFIG_STM32_TIM1
case STM32_TIM1_BASE: case STM32_TIM1_BASE:
switch(channel) { switch (channel)
{
#if defined(GPIO_TIM1_CH1OUT) #if defined(GPIO_TIM1_CH1OUT)
case 0: stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; case 0:
stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
#endif #endif
#if defined(GPIO_TIM1_CH2OUT) #if defined(GPIO_TIM1_CH2OUT)
case 1: stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; case 1:
stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
#endif #endif
#if defined(GPIO_TIM1_CH3OUT) #if defined(GPIO_TIM1_CH3OUT)
case 2: stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; case 2:
stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
#endif #endif
#if defined(GPIO_TIM1_CH4OUT) #if defined(GPIO_TIM1_CH4OUT)
case 3: stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; case 3:
stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
#endif #endif
default: return ERROR; default: return ERROR;
} }
@ -554,40 +670,57 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
#endif #endif
#if CONFIG_STM32_TIM8 #if CONFIG_STM32_TIM8
case STM32_TIM8_BASE: case STM32_TIM8_BASE:
switch(channel) { switch (channel)
{
#if defined(GPIO_TIM8_CH1OUT) #if defined(GPIO_TIM8_CH1OUT)
case 0: stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; case 0:
stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
#endif #endif
#if defined(GPIO_TIM8_CH2OUT) #if defined(GPIO_TIM8_CH2OUT)
case 1: stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; case 1:
stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break;
#endif #endif
#if defined(GPIO_TIM8_CH3OUT) #if defined(GPIO_TIM8_CH3OUT)
case 2: stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; case 2:
stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break;
#endif #endif
#if defined(GPIO_TIM8_CH4OUT) #if defined(GPIO_TIM8_CH4OUT)
case 3: stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; case 3:
stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
#endif #endif
default: return ERROR; default:
return ERROR;
} }
break; break;
#endif #endif
#endif #endif
default: return ERROR; default:
return ERROR;
} }
return OK; return OK;
} }
static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint16_t compare) static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare)
{ {
ASSERT(dev); ASSERT(dev);
switch(channel) { switch (channel)
case 1: stm32_tim_putreg(dev, STM32_GTIM_CCR1_OFFSET, compare); break; {
case 2: stm32_tim_putreg(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 1:
case 3: stm32_tim_putreg(dev, STM32_GTIM_CCR3_OFFSET, compare); break; stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare);
case 4: stm32_tim_putreg(dev, STM32_GTIM_CCR4_OFFSET, compare); break; break;
default: return ERROR; case 2:
stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare);
break;
case 3:
stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare);
break;
case 4:
stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare);
break;
default:
return ERROR;
} }
return OK; return OK;
} }
@ -596,11 +729,16 @@ static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel
{ {
ASSERT(dev); ASSERT(dev);
switch(channel) { switch (channel)
case 1: return stm32_tim_getreg(dev, STM32_GTIM_CCR1_OFFSET); {
case 2: return stm32_tim_getreg(dev, STM32_GTIM_CCR2_OFFSET); case 1:
case 3: return stm32_tim_getreg(dev, STM32_GTIM_CCR3_OFFSET); return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET);
case 4: return stm32_tim_getreg(dev, STM32_GTIM_CCR4_OFFSET); case 2:
return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET);
case 3:
return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET);
case 4:
return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET);
} }
return ERROR; return ERROR;
} }
@ -609,14 +747,14 @@ static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel
* Advanced Functions * Advanced Functions
************************************************************************************/ ************************************************************************************/
/** \todo Advanced functions for the STM32_ATIM */ /* TODO: Advanced functions for the STM32_ATIM */
/************************************************************************************ /************************************************************************************
* Device Structures, Instantiation * Device Structures, Instantiation
************************************************************************************/ ************************************************************************************/
struct stm32_tim_ops_s stm32_tim_ops = { struct stm32_tim_ops_s stm32_tim_ops =
{
.setmode = &stm32_tim_setmode, .setmode = &stm32_tim_setmode,
.setclock = &stm32_tim_setclock, .setclock = &stm32_tim_setclock,
.setperiod = &stm32_tim_setperiod, .setperiod = &stm32_tim_setperiod,
@ -630,7 +768,8 @@ struct stm32_tim_ops_s stm32_tim_ops = {
}; };
#if CONFIG_STM32_TIM2 #if CONFIG_STM32_TIM2
struct stm32_tim_priv_s stm32_tim2_priv = { struct stm32_tim_priv_s stm32_tim2_priv =
{
.ops = &stm32_tim_ops, .ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED, .mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM2_BASE, .base = STM32_TIM2_BASE,
@ -638,7 +777,8 @@ struct stm32_tim_priv_s stm32_tim2_priv = {
#endif #endif
#if CONFIG_STM32_TIM3 #if CONFIG_STM32_TIM3
struct stm32_tim_priv_s stm32_tim3_priv = { struct stm32_tim_priv_s stm32_tim3_priv =
{
.ops = &stm32_tim_ops, .ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED, .mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM3_BASE, .base = STM32_TIM3_BASE,
@ -646,7 +786,8 @@ struct stm32_tim_priv_s stm32_tim3_priv = {
#endif #endif
#if CONFIG_STM32_TIM4 #if CONFIG_STM32_TIM4
struct stm32_tim_priv_s stm32_tim4_priv = { struct stm32_tim_priv_s stm32_tim4_priv =
{
.ops = &stm32_tim_ops, .ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED, .mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM4_BASE, .base = STM32_TIM4_BASE,
@ -654,7 +795,8 @@ struct stm32_tim_priv_s stm32_tim4_priv = {
#endif #endif
#if CONFIG_STM32_TIM5 #if CONFIG_STM32_TIM5
struct stm32_tim_priv_s stm32_tim5_priv = { struct stm32_tim_priv_s stm32_tim5_priv =
{
.ops = &stm32_tim_ops, .ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED, .mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM5_BASE, .base = STM32_TIM5_BASE,
@ -663,7 +805,8 @@ struct stm32_tim_priv_s stm32_tim5_priv = {
#if STM32_NBTIM > 0 #if STM32_NBTIM > 0
#if CONFIG_STM32_TIM6 #if CONFIG_STM32_TIM6
struct stm32_tim_priv_s stm32_tim6_priv = { struct stm32_tim_priv_s stm32_tim6_priv =
{
.ops = &stm32_tim_ops, .ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED, .mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM6_BASE, .base = STM32_TIM6_BASE,
@ -673,7 +816,8 @@ struct stm32_tim_priv_s stm32_tim6_priv = {
#if STM32_NBTIM > 1 #if STM32_NBTIM > 1
#if CONFIG_STM32_TIM7 #if CONFIG_STM32_TIM7
struct stm32_tim_priv_s stm32_tim7_priv = { struct stm32_tim_priv_s stm32_tim7_priv =
{
.ops = &stm32_tim_ops, .ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED, .mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM7_BASE, .base = STM32_TIM7_BASE,
@ -684,7 +828,8 @@ struct stm32_tim_priv_s stm32_tim7_priv = {
#if STM32_NATIM > 0 #if STM32_NATIM > 0
#if CONFIG_STM32_TIM1 #if CONFIG_STM32_TIM1
struct stm32_tim_priv_s stm32_tim1_priv = { struct stm32_tim_priv_s stm32_tim1_priv =
{
.ops = &stm32_tim_ops, .ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED, .mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM1_BASE, .base = STM32_TIM1_BASE,
@ -692,7 +837,8 @@ struct stm32_tim_priv_s stm32_tim1_priv = {
#endif #endif
#if CONFIG_STM32_TIM8 #if CONFIG_STM32_TIM8
struct stm32_tim_priv_s stm32_tim8_priv = { struct stm32_tim_priv_s stm32_tim8_priv =
{
.ops = &stm32_tim_ops, .ops = &stm32_tim_ops,
.mode = STM32_TIM_MODE_UNUSED, .mode = STM32_TIM_MODE_UNUSED,
.base = STM32_TIM8_BASE, .base = STM32_TIM8_BASE,
@ -701,7 +847,6 @@ struct stm32_tim_priv_s stm32_tim8_priv = {
#endif #endif
/************************************************************************************ /************************************************************************************
* Public Function - Initialization * Public Function - Initialization
************************************************************************************/ ************************************************************************************/
@ -712,7 +857,8 @@ FAR struct stm32_tim_dev_s * stm32_tim_init(int timer)
/* Get structure and enable power */ /* Get structure and enable power */
switch(timer) { switch (timer)
{
#if CONFIG_STM32_TIM2 #if CONFIG_STM32_TIM2
case 2: case 2:
dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv;
@ -769,60 +915,81 @@ FAR struct stm32_tim_dev_s * stm32_tim_init(int timer)
break; break;
#endif #endif
#endif #endif
default: return NULL; default:
return NULL;
} }
/* Is device already allocated */ /* Is device already allocated */
if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED)
{
return NULL; return NULL;
}
stm32_tim_reset(dev); stm32_tim_reset(dev);
return dev; return dev;
} }
/* TODO: Detach interrupts, and close down all TIM Channels */
/** \todo Detach interrupts, and close down all TIM Channels */
int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev) int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
{ {
ASSERT(dev); ASSERT(dev);
/* Disable power */ /* Disable power */
switch( ((struct stm32_tim_priv_s *)dev)->base ) { switch (((struct stm32_tim_priv_s *)dev)->base)
{
#if CONFIG_STM32_TIM2 #if CONFIG_STM32_TIM2
case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); break; case STM32_TIM2_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0);
break;
#endif #endif
#if CONFIG_STM32_TIM3 #if CONFIG_STM32_TIM3
case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); break; case STM32_TIM3_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0);
break;
#endif #endif
#if CONFIG_STM32_TIM4 #if CONFIG_STM32_TIM4
case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); break; case STM32_TIM4_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0);
break;
#endif #endif
#if CONFIG_STM32_TIM5 #if CONFIG_STM32_TIM5
case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); break; case STM32_TIM5_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0);
break;
#endif #endif
#if STM32_NBTIM > 0 #if STM32_NBTIM > 0
#if CONFIG_STM32_TIM6 #if CONFIG_STM32_TIM6
case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); break; case STM32_TIM6_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0);
break;
#endif #endif
#endif #endif
#if STM32_NBTIM > 1 #if STM32_NBTIM > 1
#if CONFIG_STM32_TIM7 #if CONFIG_STM32_TIM7
case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); break; case STM32_TIM7_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0);
break;
#endif #endif
#endif #endif
#if STM32_NATIM > 0 #if STM32_NATIM > 0
#if CONFIG_STM32_TIM1 #if CONFIG_STM32_TIM1
case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; case STM32_TIM1_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
break;
#endif #endif
#if CONFIG_STM32_TIM8 #if CONFIG_STM32_TIM8
case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; case STM32_TIM8_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
break;
#endif #endif
#endif #endif
default: return ERROR; default:
return ERROR;
} }
/* Mark it as free */ /* Mark it as free */

6
arch/arm/src/stm32/stm32_tim.h
View File

@ -6,7 +6,7 @@
* *
* With modifications and updates by: * With modifications and updates by:
* *
* Copyright (C) 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -156,12 +156,12 @@ struct stm32_tim_ops_s
int (*setmode)(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); int (*setmode)(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode);
int (*setclock)(FAR struct stm32_tim_dev_s *dev, uint32_t freq); int (*setclock)(FAR struct stm32_tim_dev_s *dev, uint32_t freq);
void (*setperiod)(FAR struct stm32_tim_dev_s *dev, uint16_t period); void (*setperiod)(FAR struct stm32_tim_dev_s *dev, uint32_t period);
/* General and Advanced Timers Adds */ /* General and Advanced Timers Adds */
int (*setchannel)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, stm32_tim_channel_t mode); int (*setchannel)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, stm32_tim_channel_t mode);
int (*setcompare)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint16_t compare); int (*setcompare)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare);
int (*getcapture)(FAR struct stm32_tim_dev_s *dev, uint8_t channel); int (*getcapture)(FAR struct stm32_tim_dev_s *dev, uint8_t channel);
int (*setisr)(FAR struct stm32_tim_dev_s *dev, int (*handler)(int irq, void *context), int source); int (*setisr)(FAR struct stm32_tim_dev_s *dev, int (*handler)(int irq, void *context), int source);

4
drivers/input/tsc2007.c
View File

@ -257,13 +257,13 @@ static void tsc2007_notify(FAR struct tsc2007_dev_s *priv)
if (priv->nwaiters > 0) if (priv->nwaiters > 0)
{ {
/* After posting this semaphore, we need to exit because the TSC2007 /* After posting this semaphore, we need to exit because the TSC2007
* is no longer avaialable. * is no longer available.
*/ */
sem_post(&priv->waitsem); sem_post(&priv->waitsem);
} }
/* If there are threads waiting on poll() for TSC2007 data to become availabe, /* If there are threads waiting on poll() for TSC2007 data to become available,
* then wake them up now. NOTE: we wake up all waiting threads because we * then wake them up now. NOTE: we wake up all waiting threads because we
* do not know that they are going to do. If they all try to read the data, * do not know that they are going to do. If they all try to read the data,
* then some make end up blocking after all. * then some make end up blocking after all.

8
include/stdlib.h
View File

@ -144,12 +144,12 @@ EXTERN unsigned long long strtoull(const char *, char **, int);
#endif #endif
EXTERN double_t strtod(const char *, char **); EXTERN double_t strtod(const char *, char **);
#define atoi(nptr) strtol((nptr), NULL, 10); #define atoi(nptr) strtol((nptr), NULL, 10)
#define atol(nptr) strtol((nptr), NULL, 10); #define atol(nptr) strtol((nptr), NULL, 10)
#ifdef CONFIG_HAVE_LONG_LONG #ifdef CONFIG_HAVE_LONG_LONG
#define atoll(nptr) strtoll((nptr), NULL, 10); #define atoll(nptr) strtoll((nptr), NULL, 10)
#endif #endif
#define atof(nptr) strtod((nptr), NULL); #define atof(nptr) strtod((nptr), NULL)
/* Memory Management */ /* Memory Management */

36
lib/stdio/lib_libvsprintf.c
View File

@ -529,6 +529,21 @@ static int getusize(uint8_t fmt, uint8_t flags, unsigned int n)
utoascii(&nulloutstream, fmt, flags, n); utoascii(&nulloutstream, fmt, flags, n);
return nulloutstream.nput; return nulloutstream.nput;
} }
/****************************************************************************
* Name: getdblsize
****************************************************************************/
#ifdef CONFIG_LIBC_FLOATINGPOINT
static int getdblsize(uint8_t fmt, int trunc, uint8_t flags, double n)
{
struct lib_outstream_s nulloutstream;
lib_nulloutstream(&nulloutstream);
lib_dtoa(&nulloutstream, fmt, trunc, flags, n);
return nulloutstream.nput;
}
#endif
#endif /* CONFIG_NOPRINTF_FIELDWIDTH */ #endif /* CONFIG_NOPRINTF_FIELDWIDTH */
#ifdef CONFIG_LONG_IS_NOT_INT #ifdef CONFIG_LONG_IS_NOT_INT
@ -1535,9 +1550,30 @@ int lib_vsprintf(FAR struct lib_outstream_s *obj, FAR const char *src, va_list a
else if (strchr("eEfgG", FMT_CHAR)) else if (strchr("eEfgG", FMT_CHAR))
{ {
double dblval = va_arg(ap, double); double dblval = va_arg(ap, double);
#ifndef CONFIG_NOPRINTF_FIELDWIDTH
int dblsize;
/* Get the width of the output */
dblsize = getdblsize(FMT_CHAR, trunc, flags, dblval);
/* Perform left field justification actions */
prejustify(obj, fmt, flags, width, dblsize);
#endif
/* Output the number */
lib_dtoa(obj, FMT_CHAR, trunc, flags, dblval); lib_dtoa(obj, FMT_CHAR, trunc, flags, dblval);
#ifndef CONFIG_NOPRINTF_FIELDWIDTH
/* Perform right field justification actions */
postjustify(obj, fmt, flags, width, dblsize);
} }
#endif #endif
#endif /* CONFIG_LIBC_FLOATINGPOINT */
} }
return obj->nput; return obj->nput;