PIC32MX1/2 pin selection logic; Mirtoo LEDs, SPI2, and UART2 configuration
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4853 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
55f328c91a
commit
f17fd97fd2
@ -47,7 +47,7 @@
|
||||
****************************************************************************/
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
#if defined(PIC32MX110F016B)
|
||||
#if defined(CONFIG_ARCH_CHIP_PIC32MX110F016B)
|
||||
# define CHIP_PIC32MX1 1
|
||||
# undef CHIP_PIC32MX2
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -60,13 +60,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -81,7 +83,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX110F016C)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX110F016C)
|
||||
# define CHIP_PIC32MX1 1
|
||||
# undef CHIP_PIC32MX2
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -94,13 +96,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -115,7 +119,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX110F016D)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX110F016D)
|
||||
# define CHIP_PIC32MX1 1
|
||||
# undef CHIP_PIC32MX2
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -128,13 +132,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -149,7 +155,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX120F032B)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX120F032B)
|
||||
# define CHIP_PIC32MX1 1
|
||||
# undef CHIP_PIC32MX2
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -162,13 +168,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -183,7 +191,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX120F032C)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX120F032C)
|
||||
# define CHIP_PIC32MX1 1
|
||||
# undef CHIP_PIC32MX2
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -196,13 +204,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -217,7 +227,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX120F032D)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX120F032D)
|
||||
# define CHIP_PIC32MX1 1
|
||||
# undef CHIP_PIC32MX2
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -230,13 +240,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -251,7 +263,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX130F064B)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX130F064B)
|
||||
# define CHIP_PIC32MX1 1
|
||||
# undef CHIP_PIC32MX2
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -264,13 +276,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -285,7 +299,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX130F064C)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX130F064C)
|
||||
# define CHIP_PIC32MX1 1
|
||||
# undef CHIP_PIC32MX2
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -298,13 +312,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -319,7 +335,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX130F064D)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX130F064D)
|
||||
# define CHIP_PIC32MX1 1
|
||||
# undef CHIP_PIC32MX2
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -332,13 +348,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -353,7 +371,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX150F128B)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX150F128B)
|
||||
# define CHIP_PIC32MX1 1
|
||||
# undef CHIP_PIC32MX2
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -366,13 +384,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -387,7 +407,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX150F128C)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX150F128C)
|
||||
# define CHIP_PIC32MX1 1
|
||||
# undef CHIP_PIC32MX2
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -400,13 +420,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -421,7 +443,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX150F128D)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX150F128D)
|
||||
# define CHIP_PIC32MX1 1
|
||||
# undef CHIP_PIC32MX2
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -434,13 +456,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -455,7 +479,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX210F016B)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX210F016B)
|
||||
# undef CHIP_PIC32MX1
|
||||
# define CHIP_PIC32MX2 1
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -468,13 +492,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -489,7 +515,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX210F016C)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX210F016C)
|
||||
# undef CHIP_PIC32MX1
|
||||
# define CHIP_PIC32MX2 1
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -502,13 +528,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -523,7 +551,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX210F016D)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX210F016D)
|
||||
# undef CHIP_PIC32MX1
|
||||
# define CHIP_PIC32MX2 1
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -536,13 +564,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -557,7 +587,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX220F032B)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX220F032B)
|
||||
# undef CHIP_PIC32MX1
|
||||
# define CHIP_PIC32MX2 1
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -570,13 +600,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -591,7 +623,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX220F032C)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX220F032C)
|
||||
# undef CHIP_PIC32MX1
|
||||
# define CHIP_PIC32MX2 1
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -604,13 +636,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -625,7 +659,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX220F032D)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX220F032D)
|
||||
# undef CHIP_PIC32MX1
|
||||
# define CHIP_PIC32MX2 1
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -638,13 +672,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -659,7 +695,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX230F064B)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX230F064B)
|
||||
# undef CHIP_PIC32MX1
|
||||
# define CHIP_PIC32MX2 1
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -672,13 +708,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -693,7 +731,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX230F064C)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX230F064C)
|
||||
# undef CHIP_PIC32MX1
|
||||
# define CHIP_PIC32MX2 1
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -706,13 +744,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -727,7 +767,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX230F064D)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX230F064D)
|
||||
# undef CHIP_PIC32MX1
|
||||
# define CHIP_PIC32MX2 1
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -740,13 +780,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -761,7 +803,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX250F128B)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX250F128B)
|
||||
# undef CHIP_PIC32MX1
|
||||
# define CHIP_PIC32MX2 1
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -774,13 +816,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -795,7 +839,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX250F128C)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX250F128C)
|
||||
# undef CHIP_PIC32MX1
|
||||
# define CHIP_PIC32MX2 1
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -808,13 +852,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -829,7 +875,7 @@
|
||||
# define CHIP_PSP 0 /* No parallel slave port (?) */
|
||||
# define CHIP_NETHERNET 0 /* No Ethernet */
|
||||
# define CHIP_JTAG 1 /* Has JTAG */
|
||||
#elif defined(PIC32MX250F128D)
|
||||
#elif defined(CONFIG_ARCH_CHIP_PIC32MX250F128D)
|
||||
# undef CHIP_PIC32MX1
|
||||
# define CHIP_PIC32MX2 1
|
||||
# undef CHIP_PIC32MX3
|
||||
@ -842,13 +888,15 @@
|
||||
# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# undef CHIP_CHE /* No pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 3 /* 3 ports (A, B, C) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
|
||||
# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */
|
||||
# define CHIP_CTMU 1 /* Has CTMU */
|
||||
# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# define CHIP_VRFSEL 1 /* Comparator voltage reference selection */
|
||||
# undef CHIP_TRACE /* No trace capability */
|
||||
# define CHIP_NUARTS 2 /* 2 UARTS */
|
||||
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
|
||||
@ -876,6 +924,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -907,6 +957,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -938,6 +990,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -969,6 +1023,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1000,6 +1056,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1031,6 +1089,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1062,6 +1122,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1093,6 +1155,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1124,6 +1188,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1155,6 +1221,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1186,6 +1254,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1217,6 +1287,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1248,6 +1320,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1279,6 +1353,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1310,6 +1386,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1341,6 +1419,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1372,6 +1452,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1403,8 +1485,10 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
|
||||
# define CHIP_NUSBDMACHAN tbd
|
||||
@ -1434,8 +1518,10 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
|
||||
# define CHIP_NUSBDMACHAN tbd
|
||||
@ -1465,8 +1551,10 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
|
||||
# define CHIP_NUSBDMACHAN tbd
|
||||
@ -1496,8 +1584,10 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
|
||||
# define CHIP_NUSBDMACHAN tbd
|
||||
@ -1527,8 +1617,10 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
|
||||
# define CHIP_NUSBDMACHAN tbd
|
||||
@ -1558,8 +1650,10 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
|
||||
# define CHIP_NUSBDMACHAN tbd
|
||||
@ -1589,8 +1683,10 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
|
||||
# define CHIP_NUSBDMACHAN tbd
|
||||
@ -1620,8 +1716,10 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
|
||||
# define CHIP_NUSBDMACHAN tbd
|
||||
@ -1651,8 +1749,10 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
|
||||
# define CHIP_NUSBDMACHAN tbd
|
||||
@ -1682,8 +1782,10 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
|
||||
# define CHIP_NUSBDMACHAN tbd
|
||||
@ -1713,9 +1815,11 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */ /* 5 output compare */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
|
||||
# define CHIP_NUSBDMACHAN tbd
|
||||
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
|
||||
@ -1744,6 +1848,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1775,6 +1881,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1806,6 +1914,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1837,6 +1947,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1868,6 +1980,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1899,6 +2013,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1930,6 +2046,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1961,6 +2079,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -1992,6 +2112,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -2023,6 +2145,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -2054,6 +2178,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -2085,6 +2211,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -2116,6 +2244,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -2147,6 +2277,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -2178,6 +2310,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -2209,6 +2343,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
@ -2240,6 +2376,8 @@
|
||||
# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
|
||||
# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
|
||||
# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */
|
||||
# define CHIP_CHE 1 /* Has pre-fetch cache controller */
|
||||
# define CHIP_NPORTS 7 /* 7 ports (A, B, C, D, E, F, G) */
|
||||
# define CHIP_NTIMERS 5 /* 5 timers */
|
||||
# define CHIP_NIC 5 /* 5 input capture */
|
||||
# define CHIP_NOC 5 /* 5 output compare */
|
||||
|
||||
@ -1,89 +1,89 @@
|
||||
/****************************************************************************
|
||||
* arch/mips/src/pic32mx/pic32mx-can.h
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CAN_H
|
||||
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CAN_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "pic32mx-memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-Processor Definitions
|
||||
****************************************************************************/
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#warning "To be provided"
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#warning "To be provided"
|
||||
|
||||
/* Register Bit-Field Definitions *******************************************/
|
||||
|
||||
#warning "To be provided"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CAN_H */
|
||||
/****************************************************************************
|
||||
* arch/mips/src/pic32mx/pic32mx-can.h
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CAN_H
|
||||
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CAN_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "pic32mx-memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-Processor Definitions
|
||||
****************************************************************************/
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#warning "To be provided"
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#warning "To be provided"
|
||||
|
||||
/* Register Bit-Field Definitions *******************************************/
|
||||
|
||||
#warning "To be provided"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CAN_H */
|
||||
|
||||
@ -601,6 +601,14 @@
|
||||
# define CONFIG_PIC32MX_USERID 0x584e /* "NutX" */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_PMDL1WAY /* Peripheral module disable configuration */
|
||||
# define CONFIG_PIC32MX_PMDL1WAY 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_IOL1WAY /* Peripheral pin select configuration */
|
||||
# define CONFIG_PIC32MX_IOL1WAY 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_SRSSEL /* Shadow register interrupt priority */
|
||||
# define CONFIG_PIC32MX_SRSSEL INT_IPC_MIN_PRIORITY
|
||||
#endif
|
||||
|
||||
@ -48,6 +48,7 @@
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "chip.h"
|
||||
#include "pic32mx-ioport.h"
|
||||
#include "pic32mx-internal.h"
|
||||
|
||||
@ -55,8 +56,6 @@
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define GPIO_NPORTS 7
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
@ -65,11 +64,27 @@
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
static const uintptr_t g_gpiobase[GPIO_NPORTS] =
|
||||
static const uintptr_t g_gpiobase[CHIP_NPORTS] =
|
||||
{
|
||||
PIC32MX_IOPORTA_K1BASE, PIC32MX_IOPORTB_K1BASE, PIC32MX_IOPORTC_K1BASE,
|
||||
PIC32MX_IOPORTD_K1BASE, PIC32MX_IOPORTE_K1BASE, PIC32MX_IOPORTF_K1BASE,
|
||||
PIC32MX_IOPORTG_K1BASE
|
||||
PIC32MX_IOPORTA_K1BASE
|
||||
#if CHIP_NPORTS > 1
|
||||
, PIC32MX_IOPORTB_K1BASE
|
||||
#endif
|
||||
#if CHIP_NPORTS > 2
|
||||
, PIC32MX_IOPORTC_K1BASE
|
||||
#endif
|
||||
#if CHIP_NPORTS > 3
|
||||
, PIC32MX_IOPORTD_K1BASE
|
||||
#endif
|
||||
#if CHIP_NPORTS > 4
|
||||
, PIC32MX_IOPORTE_K1BASE
|
||||
#endif
|
||||
#if CHIP_NPORTS > 5
|
||||
, PIC32MX_IOPORTF_K1BASE
|
||||
#endif
|
||||
#if CHIP_NPORTS > 6
|
||||
, PIC32MX_IOPORTG_K1BASE
|
||||
#endif
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
@ -134,7 +149,7 @@ int pic32mx_configgpio(uint16_t cfgset)
|
||||
|
||||
/* Verify that the port number is within range */
|
||||
|
||||
if (port < GPIO_NPORTS)
|
||||
if (port < CHIP_NPORTS)
|
||||
{
|
||||
/* Get the base address of the ports */
|
||||
|
||||
@ -205,7 +220,7 @@ void pic32mx_gpiowrite(uint16_t pinset, bool value)
|
||||
|
||||
/* Verify that the port number is within range */
|
||||
|
||||
if (port < GPIO_NPORTS)
|
||||
if (port < CHIP_NPORTS)
|
||||
{
|
||||
/* Get the base address of the ports */
|
||||
|
||||
@ -240,7 +255,7 @@ bool pic32mx_gpioread(uint16_t pinset)
|
||||
|
||||
/* Verify that the port number is within range */
|
||||
|
||||
if (port < GPIO_NPORTS)
|
||||
if (port < CHIP_NPORTS)
|
||||
{
|
||||
/* Get the base address of the ports */
|
||||
|
||||
@ -271,7 +286,7 @@ void pic32mx_dumpgpio(uint32_t pinset, const char *msg)
|
||||
|
||||
/* Verify that the port number is within range */
|
||||
|
||||
if (port < GPIO_NPORTS)
|
||||
if (port < CHIP_NPORTS)
|
||||
{
|
||||
/* Get the base address of the ports */
|
||||
|
||||
|
||||
@ -597,12 +597,19 @@ halt:
|
||||
.type devconfig, object
|
||||
devconfig:
|
||||
devconfig3:
|
||||
#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
|
||||
.long CONFIG_PIC32MX_USERID << DEVCFG3_USERID_SHIFT | \
|
||||
CONFIG_PIC32MX_PMDL1WAY << 28 | CONFIG_PIC32MX_IOL1WAY << 29 | \
|
||||
CONFIG_PIC32MX_USBIDO << 30 | CONFIG_PIC32MX_VBUSIO << 31 | \
|
||||
DEVCFG3_UNUSED
|
||||
#else
|
||||
.long CONFIG_PIC32MX_USERID << DEVCFG3_USERID_SHIFT | \
|
||||
CONFIG_PIC32MX_SRSSEL << DEVCFG3_FSRSSEL_SHIFT | \
|
||||
CONFIG_PIC32MX_FMIIEN << 24 | CONFIG_PIC32MX_FETHIO << 25 | \
|
||||
CONFIG_PIC32MX_FCANIO << 26 | CONFIG_PIC32MX_FSCM1IO << 29 | \
|
||||
CONFIG_PIC32MX_USBIDO << 30 | CONFIG_PIC32MX_VBUSIO << 31 | \
|
||||
DEVCFG3_UNUSED
|
||||
#endif
|
||||
|
||||
devconfig2:
|
||||
.long CONFIG_PIC32MX_PLLIDIV | CONFIG_PIC32MX_PLLMULT | \
|
||||
|
||||
@ -457,7 +457,7 @@
|
||||
|
||||
# define INT_CMP1 (1 << 0) /* Vector: 27, Comparator 1 Interrupt */
|
||||
# define INT_CMP2 (1 << 1) /* Vector: 28, Comparator 2 Interrupt */
|
||||
# define INT_CMP2 (1 << 2) /* Vector: 29, Comparator 3 Interrupt */
|
||||
# define INT_CMP3 (1 << 2) /* Vector: 29, Comparator 3 Interrupt */
|
||||
# define INT_USB (1 << 3) /* Vector: 30, USB */
|
||||
# define INT_SPI1E (1 << 4) /* Vector: 31, SPI1 */
|
||||
# define INT_SPI1TX (1 << 5) /* Vector: 31, " " */
|
||||
|
||||
@ -46,6 +46,7 @@
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
#include "pic32mx-internal.h"
|
||||
#include "pic32mx-bmx.h"
|
||||
#include "pic32mx-che.h"
|
||||
@ -109,13 +110,16 @@
|
||||
|
||||
static inline void pic32mx_waitstates(void)
|
||||
{
|
||||
#ifdef CHIP_CHE
|
||||
unsigned int nwaits;
|
||||
unsigned int residual;
|
||||
#endif
|
||||
|
||||
/* Disable DRM wait states */
|
||||
|
||||
putreg32(BMX_CON_BMXWSDRM, PIC32MX_BMX_CONCLR);
|
||||
|
||||
#ifdef CHIP_CHE
|
||||
/* Configure pre-fetch cache FLASH wait states */
|
||||
|
||||
residual = BOARD_CPU_CLOCK;
|
||||
@ -131,6 +135,7 @@ static inline void pic32mx_waitstates(void)
|
||||
/* Set the FLASH wait states -- clearing all other bits! */
|
||||
|
||||
putreg32(nwaits, PIC32MX_CHE_CON);
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -148,11 +153,13 @@ static inline void pic32mx_cache(void)
|
||||
{
|
||||
register uint32_t regval;
|
||||
|
||||
/* Enable caching on all regions */
|
||||
/* Enable prefetch on all regions */
|
||||
|
||||
#ifdef CHIP_CHE
|
||||
regval = getreg32(PIC32MX_CHE_CON);
|
||||
regval |= CHE_CON_PREFEN_ALL;
|
||||
putreg32(regval, PIC32MX_CHE_CON);
|
||||
#endif
|
||||
|
||||
/* Enable cache on KSEG 0 in the CP0 CONFIG register*/
|
||||
|
||||
|
||||
275
arch/mips/src/pic32mx/pic32mx-pps.h
Normal file
275
arch/mips/src/pic32mx/pic32mx-pps.h
Normal file
@ -0,0 +1,275 @@
|
||||
/****************************************************************************
|
||||
* arch/mips/src/pic32mx/pic32mx-pps.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PPS_H
|
||||
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PPS_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "pic32mx-memorymap.h"
|
||||
|
||||
#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-Processor Definitions
|
||||
****************************************************************************/
|
||||
/* Register Offsets *********************************************************/
|
||||
/* Peripheral pin select input registers */
|
||||
|
||||
#define PIC32MX_PPS_INT1R_OFFSET 0x0004
|
||||
#define PIC32MX_PPS_INT2R_OFFSET 0x0008
|
||||
#define PIC32MX_PPS_INT3R_OFFSET 0x000c
|
||||
#define PIC32MX_PPS_INT4R_OFFSET 0x0010
|
||||
#define PIC32MX_PPS_T2CKR_OFFSET 0x0018
|
||||
#define PIC32MX_PPS_T3CKR_OFFSET 0x001c
|
||||
#define PIC32MX_PPS_T4CKR_OFFSET 0x0020
|
||||
#define PIC32MX_PPS_T5CKR_OFFSET 0x0024
|
||||
#define PIC32MX_PPS_IC1R_OFFSET 0x0028
|
||||
#define PIC32MX_PPS_IC2R_OFFSET 0x002c
|
||||
#define PIC32MX_PPS_IC3R_OFFSET 0x0030
|
||||
#define PIC32MX_PPS_IC4R_OFFSET 0x0034
|
||||
#define PIC32MX_PPS_IC5R_OFFSET 0x0038
|
||||
#define PIC32MX_PPS_OCFAR_OFFSET 0x0048
|
||||
#define PIC32MX_PPS_OCFBR_OFFSET 0x004c
|
||||
#define PIC32MX_PPS_U1RXR_OFFSET 0x0050
|
||||
#define PIC32MX_PPS_U1CTSR_OFFSET 0x0054
|
||||
#define PIC32MX_PPS_U2RXR_OFFSET 0x0058
|
||||
#define PIC32MX_PPS_U2CTSR_OFFSET 0x005c
|
||||
#define PIC32MX_PPS_SDI1R_OFFSET 0x0084
|
||||
#define PIC32MX_PPS_SS1R_OFFSET 0x0088
|
||||
#define PIC32MX_PPS_SDI2R_OFFSET 0x0090
|
||||
#define PIC32MX_PPS_SS2R_OFFSET 0x0094
|
||||
#define PIC32MX_PPS_REFCLKIR_OFFSET 0x00b8
|
||||
|
||||
/* Peripheral pin select output registers */
|
||||
|
||||
#define PIC32MX_PPS_RPA0R_OFFSET 0x0000
|
||||
#define PIC32MX_PPS_RPA1R_OFFSET 0x0004
|
||||
#define PIC32MX_PPS_RPA2R_OFFSET 0x0008
|
||||
#define PIC32MX_PPS_RPA3R_OFFSET 0x000c
|
||||
#define PIC32MX_PPS_RPA4R_OFFSET 0x0010
|
||||
#define PIC32MX_PPS_RPA8R_OFFSET 0x0020
|
||||
#define PIC32MX_PPS_RPA9R_OFFSET 0x0024
|
||||
#define PIC32MX_PPS_RPB0R_OFFSET 0x002c
|
||||
#define PIC32MX_PPS_RPB1R_OFFSET 0x0030
|
||||
#define PIC32MX_PPS_RPB2R_OFFSET 0x0034
|
||||
#define PIC32MX_PPS_RPB3R_OFFSET 0x0038
|
||||
#define PIC32MX_PPS_RPB4R_OFFSET 0x003c
|
||||
#define PIC32MX_PPS_RPB5R_OFFSET 0x0040
|
||||
#define PIC32MX_PPS_RPB6R_OFFSET 0x0044
|
||||
#define PIC32MX_PPS_RPB7R_OFFSET 0x0048
|
||||
#define PIC32MX_PPS_RPB8R_OFFSET 0x004c
|
||||
#define PIC32MX_PPS_RPB9R_OFFSET 0x0050
|
||||
#define PIC32MX_PPS_RPB10R_OFFSET 0x0054
|
||||
#define PIC32MX_PPS_RPB11R_OFFSET 0x0058
|
||||
#define PIC32MX_PPS_RPB13R_OFFSET 0x0060
|
||||
#define PIC32MX_PPS_RPB14R_OFFSET 0x0064
|
||||
#define PIC32MX_PPS_RPB15R_OFFSET 0x0068
|
||||
#define PIC32MX_PPS_RPC0R_OFFSET 0x006c
|
||||
#define PIC32MX_PPS_RPC1R_OFFSET 0x0070
|
||||
#define PIC32MX_PPS_RPC2R_OFFSET 0x0074
|
||||
#define PIC32MX_PPS_RPC3R_OFFSET 0x0078
|
||||
#define PIC32MX_PPS_RPC4R_OFFSET 0x007c
|
||||
#define PIC32MX_PPS_RPC5R_OFFSET 0x0080
|
||||
#define PIC32MX_PPS_RPC6R_OFFSET 0x0084
|
||||
#define PIC32MX_PPS_RPC7R_OFFSET 0x0088
|
||||
#define PIC32MX_PPS_RPC8R_OFFSET 0x008c
|
||||
#define PIC32MX_PPS_RPC9R_OFFSET 0x0090
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
/* Peripheral pin select input registers */
|
||||
|
||||
#define PIC32MX_PPS_INT1R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_INT1R_OFFSET)
|
||||
#define PIC32MX_PPS_INT2R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_INT2R_OFFSET)
|
||||
#define PIC32MX_PPS_INT3R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_INT3R_OFFSET)
|
||||
#define PIC32MX_PPS_INT4R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_INT4R_OFFSET)
|
||||
#define PIC32MX_PPS_T2CKR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_T2CKR_OFFSET)
|
||||
#define PIC32MX_PPS_T3CKR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_T3CKR_OFFSET)
|
||||
#define PIC32MX_PPS_T4CKR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_T4CKR_OFFSET)
|
||||
#define PIC32MX_PPS_T5CKR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_T5CKR_OFFSET)
|
||||
#define PIC32MX_PPS_IC1R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_IC1R_OFFSET)
|
||||
#define PIC32MX_PPS_IC2R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_IC2R_OFFSET)
|
||||
#define PIC32MX_PPS_IC3R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_IC3R_OFFSET)
|
||||
#define PIC32MX_PPS_IC4R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_IC4R_OFFSET)
|
||||
#define PIC32MX_PPS_IC5R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_IC5R_OFFSET)
|
||||
#define PIC32MX_PPS_OCFAR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_OCFAR_OFFSET)
|
||||
#define PIC32MX_PPS_OCFBR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_OCFBR_OFFSET)
|
||||
#define PIC32MX_PPS_U1RXR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_U1RXR_OFFSET)
|
||||
#define PIC32MX_PPS_U1CTSR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_U1CTSR_OFFSET)
|
||||
#define PIC32MX_PPS_U2RXR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_U2RXR_OFFSET)
|
||||
#define PIC32MX_PPS_U2CTSR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_U2CTSR_OFFSET)
|
||||
#define PIC32MX_PPS_SDI1R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_SDI1R_OFFSET)
|
||||
#define PIC32MX_PPS_SS1R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_SS1R_OFFSET)
|
||||
#define PIC32MX_PPS_SDI2R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_SDI2R_OFFSET)
|
||||
#define PIC32MX_PPS_SS2R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_SS2R_OFFSET)
|
||||
#define PIC32MX_PPS_REFCLKIR (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_REFCLKIR_OFFSET)
|
||||
|
||||
/* Peripheral pin select output registers */
|
||||
|
||||
#define PIC32MX_PPS_RPA0R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPA0R_OFFSET)
|
||||
#define PIC32MX_PPS_RPA1R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPA1R_OFFSET)
|
||||
#define PIC32MX_PPS_RPA2R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPA2R_OFFSET)
|
||||
#define PIC32MX_PPS_RPA3R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPA3R_OFFSET)
|
||||
#define PIC32MX_PPS_RPA4R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPA4R_OFFSET)
|
||||
#define PIC32MX_PPS_RPA8R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPA8R_OFFSET)
|
||||
#define PIC32MX_PPS_RPA9R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPA9R_OFFSET)
|
||||
#define PIC32MX_PPS_RPB0R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB0R_OFFSET)
|
||||
#define PIC32MX_PPS_RPB1R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB1R_OFFSET)
|
||||
#define PIC32MX_PPS_RPB2R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB2R_OFFSET)
|
||||
#define PIC32MX_PPS_RPB3R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB3R_OFFSET)
|
||||
#define PIC32MX_PPS_RPB4R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB4R_OFFSET)
|
||||
#define PIC32MX_PPS_RPB5R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB5R_OFFSET)
|
||||
#define PIC32MX_PPS_RPB6R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB6R_OFFSET)
|
||||
#define PIC32MX_PPS_RPB7R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB7R_OFFSET)
|
||||
#define PIC32MX_PPS_RPB8R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB8R_OFFSET)
|
||||
#define PIC32MX_PPS_RPB9R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB9R_OFFSET)
|
||||
#define PIC32MX_PPS_RPB10R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB10R_OFFSET)
|
||||
#define PIC32MX_PPS_RPB11R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB11R_OFFSET)
|
||||
#define PIC32MX_PPS_RPB13R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB13R_OFFSET)
|
||||
#define PIC32MX_PPS_RPB14R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB14R_OFFSET)
|
||||
#define PIC32MX_PPS_RPB15R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPB15R_OFFSET)
|
||||
#define PIC32MX_PPS_RPC0R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC0R_OFFSET)
|
||||
#define PIC32MX_PPS_RPC1R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC1R_OFFSET)
|
||||
#define PIC32MX_PPS_RPC2R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC2R_OFFSET)
|
||||
#define PIC32MX_PPS_RPC3R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC3R_OFFSET)
|
||||
#define PIC32MX_PPS_RPC4R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC4R_OFFSET)
|
||||
#define PIC32MX_PPS_RPC5R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC5R_OFFSET)
|
||||
#define PIC32MX_PPS_RPC6R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC6R_OFFSET)
|
||||
#define PIC32MX_PPS_RPC7R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC7R_OFFSET)
|
||||
#define PIC32MX_PPS_RPC8R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC8R_OFFSET)
|
||||
#define PIC32MX_PPS_RPC9R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC9R_OFFSET)
|
||||
|
||||
/* Register Bit-Field Definitions *******************************************/
|
||||
/* Peripheral pin select input registers */
|
||||
|
||||
#define PPS_INSEL_MASK 0x0000000f
|
||||
|
||||
#define PPS_INSEL_RPA0 0
|
||||
#define PPS_INSEL_RPB3 1
|
||||
#define PPS_INSEL_RPB4 2
|
||||
#define PPS_INSEL_RPB15 3
|
||||
#define PPS_INSEL_RPB7 4
|
||||
#define PPS_INSEL_RPC7 5
|
||||
#define PPS_INSEL_RPC0 6
|
||||
#define PPS_INSEL_RPC5 7
|
||||
|
||||
#define PPS_INSEL_RPA1 0
|
||||
#define PPS_INSEL_RPB5 1
|
||||
#define PPS_INSEL_RPB1 2
|
||||
#define PPS_INSEL_RPB11 3
|
||||
#define PPS_INSEL_RPB8 4
|
||||
#define PPS_INSEL_RPA8 5
|
||||
#define PPS_INSEL_RPC8 6
|
||||
#define PPS_INSEL_RPA9 7
|
||||
|
||||
#define PPS_INSEL_RPA2 0
|
||||
#define PPS_INSEL_RPB6 1
|
||||
#define PPS_INSEL_RPA4 2
|
||||
#define PPS_INSEL_RPB13 3
|
||||
#define PPS_INSEL_RPB2 4
|
||||
#define PPS_INSEL_RPC6 5
|
||||
#define PPS_INSEL_RPC1 6
|
||||
#define PPS_INSEL_RPC3 7
|
||||
|
||||
#define PPS_INSEL_RPA3 0
|
||||
#define PPS_INSEL_RPB14 1
|
||||
#define PPS_INSEL_RPB0 2
|
||||
#define PPS_INSEL_RPB10 3
|
||||
#define PPS_INSEL_RPB9 4
|
||||
#define PPS_INSEL_RPC9 5
|
||||
#define PPS_INSEL_RPC2 6
|
||||
#define PPS_INSEL_RPC4 7
|
||||
|
||||
/* Peripheral pin select output registers */
|
||||
|
||||
#define PPS_OUTSEL_MASK 0x0000000f
|
||||
|
||||
#define PPS_OUTSEL_NOCONNECT 0
|
||||
|
||||
#define PPS_OUTSEL_U1TX 1
|
||||
#define PPS_OUTSEL_U2RTS 2
|
||||
#define PPS_OUTSEL_SS1 3
|
||||
#define PPS_OUTSEL_OC1 5
|
||||
#define PPS_OUTSEL_C2OUT 7
|
||||
|
||||
#define PPS_OUTSEL_SDO1 3
|
||||
#define PPS_OUTSEL_SDO2 4
|
||||
#define PPS_OUTSEL_OC2 5
|
||||
|
||||
//#define PPS_OUTSEL_SDO1 3
|
||||
//#define PPS_OUTSEL_SDO2 4
|
||||
#define PPS_OUTSEL_OC4 5
|
||||
#define PPS_OUTSEL_OC5 6
|
||||
#define PPS_OUTSEL_REFCLKO 7
|
||||
|
||||
#define PPS_OUTSEL_U1RTS 1
|
||||
#define PPS_OUTSEL_U2TX 2
|
||||
#define PPS_OUTSEL_SS2 4
|
||||
#define PPS_OUTSEL_OC3 5
|
||||
#define PPS_OUTSEL_C1OUT 7
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CHIP_PIC32MX1 || CHIP_PIC32MX2 */
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PPS_H */
|
||||
Loading…
x
Reference in New Issue
Block a user