SAMA5: Correct vector mapping
This commit is contained in:
Gregory Nutt
parent
9a5311296f
commit
f191ac94c0
@ -94,10 +94,10 @@
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* Public Symbols
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****************************************************************************/
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.globl cp15_coherent_dcache_for_dma
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.globl cp15_invalidate_dcache_for_dma
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.globl cp15_clean_dcache_for_dma
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.globl cp15_flush_dcache_for_dma
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.globl cp15_coherent_dcache
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.globl cp15_invalidate_dcache
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.globl cp15_clean_dcache
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.globl cp15_flush_dcache
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/****************************************************************************
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* Public Functions
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@ -106,7 +106,7 @@
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.text
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/****************************************************************************
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* Name: cp15_coherent_dcache_for_dma
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* Name: cp15_coherent_dcache
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*
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* Description:
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* Ensure that the I and D caches are coherent within specified region
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@ -123,10 +123,10 @@
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*
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****************************************************************************/
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.globl cp15_coherent_dcache_for_dma
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.type cp15_coherent_dcache_for_dma, function
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.globl cp15_coherent_dcache
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.type cp15_coherent_dcache, function
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cp15_coherent_dcache_for_dma:
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cp15_coherent_dcache:
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mrc CP15_TR(r3) /* Read the Cache Type Register */
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lsr r3, r3, #16 /* Isolate the DMinLine field */
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and r3, r3, #0xf
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@ -167,10 +167,10 @@ cp15_coherent_dcache_for_dma:
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dsb
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isb
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bx lr
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.size cp15_coherent_dcache_for_dma, . - cp15_coherent_dcache_for_dma
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.size cp15_coherent_dcache, . - cp15_coherent_dcache
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/****************************************************************************
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* Name: cp15_invalidate_dcache_for_dma
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* Name: cp15_invalidate_dcache
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*
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* Description:
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* Invalidate the data cache within the specified region; we will be
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@ -186,10 +186,10 @@ cp15_coherent_dcache_for_dma:
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*
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****************************************************************************/
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.globl cp15_invalidate_dcache_for_dma
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.type cp15_invalidate_dcache_for_dma, function
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.globl cp15_invalidate_dcache
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.type cp15_invalidate_dcache, function
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cp15_invalidate_dcache_for_dma:
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cp15_invalidate_dcache:
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mrc CP15_TR(r3) /* Read the Cache Type Register */
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lsr r3, r3, #16 /* Isolate the DMinLine field */
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@ -216,10 +216,10 @@ cp15_invalidate_dcache_for_dma:
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dsb
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bx lr
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.size cp15_coherent_dcache_for_dma, . - cp15_coherent_dcache_for_dma
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.size cp15_coherent_dcache, . - cp15_coherent_dcache
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/****************************************************************************
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* Name: cp15_clean_dcache_for_dma
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* Name: cp15_clean_dcache
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*
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* Description:
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* Clean the data cache within the specified region by flushing the
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@ -234,10 +234,10 @@ cp15_invalidate_dcache_for_dma:
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*
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****************************************************************************/
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.globl cp15_clean_dcache_for_dma
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.type cp15_clean_dcache_for_dma, function
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.globl cp15_clean_dcache
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.type cp15_clean_dcache, function
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cp15_clean_dcache_for_dma:
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cp15_clean_dcache:
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mrc CP15_TR(r3) /* Read the Cache Type Register */
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lsr r3, r3, #16 /* Isolate the DMinLine field */
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@ -258,10 +258,10 @@ cp15_clean_dcache_for_dma:
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dsb
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bx lr
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.size cp15_clean_dcache_for_dma, . - cp15_clean_dcache_for_dma
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.size cp15_clean_dcache, . - cp15_clean_dcache
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/****************************************************************************
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* Name: cp15_flush_dcache_for_dma
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* Name: cp15_flush_dcache
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*
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* Description:
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* Flush the data cache within the specified region by cleaning and
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@ -276,10 +276,10 @@ cp15_clean_dcache_for_dma:
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*
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****************************************************************************/
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.globl cp15_flush_dcache_for_dma
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.type cp15_flush_dcache_for_dma, function
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.globl cp15_flush_dcache
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.type cp15_flush_dcache, function
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cp15_flush_dcache_for_dma:
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cp15_flush_dcache:
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mrc CP15_TR(r3) /* Read the Cache Type Register */
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lsr r3, r3, #16 /* Isolate the DMinLine field */
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@ -300,5 +300,5 @@ cp15_flush_dcache_for_dma:
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dsb
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bx lr
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.size cp15_flush_dcache_for_dma, . - cp15_flush_dcache_for_dma
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.size cp15_flush_dcache, . - cp15_flush_dcache
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.end
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@ -765,7 +765,7 @@ extern "C" {
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****************************************************************************/
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/****************************************************************************
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* Name: cp15_coherent_dcache_for_dma
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* Name: cp15_coherent_dcache
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*
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* Description:
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* Ensure that the I and D caches are coherent within specified region
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@ -782,10 +782,10 @@ extern "C" {
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*
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****************************************************************************/
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void cp15_coherent_dcache_for_dma(uintptr_t start, uintptr_t end);
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void cp15_coherent_dcache(uintptr_t start, uintptr_t end);
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/****************************************************************************
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* Name: cp15_invalidate_dcache_for_dma
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* Name: cp15_invalidate_dcache
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*
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* Description:
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* Invalidate the data cache within the specified region; we will be
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@ -801,10 +801,10 @@ void cp15_coherent_dcache_for_dma(uintptr_t start, uintptr_t end);
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*
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****************************************************************************/
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void cp15_invalidate_dcache_for_dma(uintptr_t start, uintptr_t end);
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void cp15_invalidate_dcache(uintptr_t start, uintptr_t end);
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/****************************************************************************
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* Name: cp15_clean_dcache_for_dma
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* Name: cp15_clean_dcache
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*
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* Description:
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* Clean the data cache within the specified region by flushing the
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@ -819,10 +819,10 @@ void cp15_invalidate_dcache_for_dma(uintptr_t start, uintptr_t end);
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*
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****************************************************************************/
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void cp15_clean_dcache_for_dma(uintptr_t start, uintptr_t end);
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void cp15_clean_dcache(uintptr_t start, uintptr_t end);
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/****************************************************************************
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* Name: cp15_flush_dcache_for_dma
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* Name: cp15_flush_dcache
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*
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* Description:
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* Flush the data cache within the specified region by cleaning and
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@ -837,7 +837,7 @@ void cp15_clean_dcache_for_dma(uintptr_t start, uintptr_t end);
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*
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****************************************************************************/
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void cp15_flush_dcache_for_dma(uintptr_t start, uintptr_t end);
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void cp15_flush_dcache(uintptr_t start, uintptr_t end);
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#undef EXTERN
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#ifdef __cplusplus
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@ -486,55 +486,69 @@
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*
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* 0x80000000-0xefffffff: Undefined (1.75 GB)
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*
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* That is the offset where the main L2 page table will be positioned. This
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* corresponds to page table offsets 0x000002000 through 0x000003c00. That
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* That is the offset where the main L2 page tables will be positioned. This
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* corresponds to page table offsets 0x000002000 up to 0x000003c00. That
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* is 1792 entries, each mapping 4KB of address for a total of 7MB of virtual
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* address space)
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*
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* Up to two L2 page tables may be used:
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*
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* 1) One mapping the vector table. However, L2 page tables must be aligned
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* to 1KB address boundaries, so the minimum L2 page table size is then
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* 1KB, mapping up a full megabyte of virtual address space.
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*
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* This L2 page table is only allocated if CONFIG_ARCH_LOWVECTORS is *not*
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* defined. The SAMA5 boot-up logic will map the beginning of the boot
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* memory to address 0x0000:0000 using both the MMU and the AXI matrix
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* REMAP register. So no L2 page table is required.
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*
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* 2) If on-demand paging is supported (CONFIG_PAGING=y), than an additional
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* L2 page table is needed. This page table will use the remainder of
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* the address space.
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*/
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#define PGTABLE_L2_OFFSET 0x000002000
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#define PGTABLE_L2_SIZE 0x000001c00
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#ifndef CONFIG_ARCH_LOWVECTORS
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/* Vector L2 page table offset/size */
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/* This other small region is reserved for the vector table L2 page table
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*
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* 0x00a00000-0x0fffffff: Undefined (246 MB)
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*
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* This corresponds to page table offsets 0x000000028 through 0x00000400.
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* That is 246 entries each mapping 4KB of address each for a total of 984KB
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* of virtual address space). For low vectors, this L2 page table can can
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* span: 0x0000:0000 through 0x000f:6000 leaving up to the full 984KB for
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* vector logic. For high vectors located at 0xffff:0000, this L2 page
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* table can cover only 0xfff0:0000 through 0xffff:6000 which leaves 5KB for
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* vectors.
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*/
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# define VECTOR_L2_OFFSET 0x000002000
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# define VECTOR_L2_SIZE 0x000000400
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#define VECTOR_L2_OFFSET 0x000000028
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#define VECTOR_L2_SIZE 0x000000400
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/* Vector L2 page table base addresses */
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/* If we need more L2 page tables, there additional entries can be obtained
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* from other unused areas in the physical memory map:
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# define VECTOR_L2_PBASE (PGTABLE_BASE_PADDR+VECTOR_L2_OFFSET)
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# define VECTOR_L2_VBASE (PGTABLE_BASE_VADDR+VECTOR_L2_OFFSET)
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/* Vector L2 page table end addresses */
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# define VECTOR_L2_END_PADDR (VECTOR_L2_PBASE+VECTOR_L2_SIZE)
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# define VECTOR_L2_END_VADDR (VECTOR_L2_VBASE+VECTOR_L2_SIZE)
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/* Paging L2 page table offset/size */
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# define PGTABLE_L2_OFFSET 0x000002400
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# define PGTABLE_L2_SIZE 0x000001800
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#else
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/* Paging L2 page table offset/size */
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# define PGTABLE_L2_OFFSET 0x000002000
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# define PGTABLE_L2_SIZE 0x000001c00
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#endif
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/* Paging L2 page table base addresses
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*
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* 0x0003c000-0x07ffffff: Reserved (127.8 MB)
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* 0x00044000-0x00ffbfff: Reserved ( 15.7 MB)
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*
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* NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual address
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* of the page table.
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* NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual
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* address of the page table.
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*/
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#define PGTABLE_L2_PBASE (PGTABLE_BASE_PADDR+PGTABLE_L2_OFFSET)
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#define PGTABLE_L2_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_OFFSET)
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#define VECTOR_L2_PBASE (PGTABLE_BASE_PADDR+VECTOR_L2_OFFSET)
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#define VECTOR_L2_VBASE (PGTABLE_BASE_VADDR+VECTOR_L2_OFFSET)
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/* Page table end addresses: */
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/* Paging L2 page table end addresses */
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#define PGTABLE_L2_END_PADDR (PGTABLE_L2_PBASE+PGTABLE_L2_SIZE)
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#define PGTABLE_L2_END_VADDR (PGTABLE_L2_VBASE+PGTABLE_L2_SIZE)
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#define VECTOR_L2_END_PADDR (VECTOR_L2_PBASE+VECTOR_L2_SIZE)
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#define VECTOR_L2_END_VADDR (VECTOR_L2_VBASE+VECTOR_L2_SIZE)
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/* Base address of the interrupt vector table.
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*
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* SAM_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM
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@ -66,23 +66,23 @@
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/* The vectors are, by default, positioned at the beginning of the text
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* section. Under what conditions do we have to remap the these vectors?
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*
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* 1) If we are using high vectors. In this case, the vectors will lie at
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* virtual address 0xfffc0000 and we will need to a) copy the vectors to
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* another location, and 2) map the vectors to that address.
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* 2) If we are using low vectors but the .text region is not already mapped
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* to address 0x0000:0000
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* 3) We are not using a ROM page table. We cannot set any custom mappings in
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* 1) If we are using high vectors (CONFIG_ARCH_LOWVECTORS=n). In this case,
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* the vectors will lie at virtual address 0xffff:000 and we will need
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* to a) copy the vectors to another location, and b) map the vectors
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* to that address, and
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*
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* For the case of CONFIG_ARCH_LOWVECTORS=y, defined. The SAMA5 boot-up
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* logic will map the beginning of the boot memory to address 0x0000:0000
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* using both the MMU and the AXI matrix REMAP register. No vector copy
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* is required because the vectors are position at the beginning of the
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* boot memory at link time and no additional MMU mapping required.
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*
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* 2) We are not using a ROM page table. We cannot set any custom mappings in
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* the case and the build must conform to the ROM page table properties
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*/
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#undef NEED_VECTORMAP
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#if !defined(CONFIG_ARCH_LOWVECTORS) || (NUTTX_START_VADDR & 0xfff00000) != 0
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# if defined(CONFIG_ARCH_ROMPGTABLE)
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# error Vector remap cannot be performed if we are using a ROM page table
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# endif
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# define NEED_VECTORMAP
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#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_ARCH_ROMPGTABLE)
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# error High vector remap cannot be performed if we are using a ROM page table
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#endif
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/****************************************************************************
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@ -117,10 +117,8 @@ static const struct section_mapping_s section_mapping[] =
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{
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/* SAMA5 Internal Memories */
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#ifndef CONFIG_ARCH_LOWVECTORS
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{ SAM_BOOTMEM_PSECTION, SAM_BOOTMEM_VSECTION,
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SAM_BOOTMEM_MMUFLAGS, SAM_BOOTMEM_NSECTIONS},
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#endif
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{ SAM_ROM_PSECTION, SAM_ROM_VSECTION,
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SAM_ROM_MMUFLAGS, SAM_ROM_NSECTIONS},
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{ SAM_NFCSRAM_PSECTION, SAM_NFCSRAM_VSECTION,
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@ -261,7 +259,8 @@ static void sam_setupmappings(void)
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*
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****************************************************************************/
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#if defined(NEED_VECTORMAP) && defined(CONFIG_PAGING)
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#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \
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defined(CONFIG_PAGING)
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static void sam_vectorpermissions(uint32_t mmuflags)
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{
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/* The PTE for the beginning of ISRAM is at the base of the L2 page table */
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@ -304,7 +303,7 @@ static void sam_vectorpermissions(uint32_t mmuflags)
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*
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****************************************************************************/
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#ifdef NEED_VECTORMAP
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#if !defined(CONFIG_ARCH_ROMPGTABLE) && !defined(CONFIG_ARCH_LOWVECTORS)
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static void sam_vectormapping(void)
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{
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uint32_t vector_paddr = SAM_VECTOR_PADDR & PTE_SMALL_PADDR_MASK;
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@ -312,7 +311,7 @@ static void sam_vectormapping(void)
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uint32_t vector_size = (uint32_t)&_vector_end - (uint32_t)&_vector_start;
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uint32_t end_paddr = SAM_VECTOR_PADDR + vector_size;
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/* REVISIT: Can really assert in this context */
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/* REVISIT: Cannot really assert in this context */
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DEBUGASSERT (vector_size <= VECTOR_TABLE_SIZE);
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@ -363,7 +362,7 @@ static void sam_copyvectorblock(void)
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* read only, then temparily mark the mapping write-able (non-buffered).
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*/
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#if defined(NEED_VECTORMAP) && defined(CONFIG_PAGING)
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#ifdef CONFIG_PAGING
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sam_vectorpermissions(MMU_L2_VECTRWFLAGS);
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#endif
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@ -387,7 +386,7 @@ static void sam_copyvectorblock(void)
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/* Make the vectors read-only, cacheable again */
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#if defined(NEED_VECTORMAP) && defined(CONFIG_PAGING)
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#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING)
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sam_vectorpermissions(MMU_L2_VECTORFLAGS);
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#endif
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}
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@ -407,9 +406,7 @@ static void sam_copyvectorblock(void)
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static inline void sam_wdtdisable(void)
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{
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#if 0 // REVISIT
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putreg32(WDT_MR_WDDIS, SAM_WDT_MR);
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#endif
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}
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/****************************************************************************
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@ -501,13 +498,12 @@ void up_boot(void)
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sam_vectormapping();
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/* The SRAM address hold the the page table is probably buffered. Make sure
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* that the modified contents of the page table are flushed into physical
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* memory.
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*/
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cp15_clean_dcache_for_dma(VECTOR_L2_VBASE, VECTOR_L2_VBASE + PGTABLE_SIZE);
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cp15_clean_dcache(PGTABLE_BASE_VADDR, PGTABLE_BASE_VADDR + PGTABLE_SIZE);
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#endif /* CONFIG_ARCH_ROMPGTABLE */
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@ -283,14 +283,17 @@ void up_irqinitialize(void)
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putreg32(AIC_WPMR_WPKEY | AIC_WPMR_WPEN, SAM_AIC_WPMR);
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#ifndef CONFIG_ARCH_LOWVECTORS
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/* Set remap state 0:
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#ifdef CONFIG_ARCH_LOWVECTORS
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/* Set remap state 0. This is done late in the boot sequence. Any
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* exceptions taken before this point in time will be handled by the
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* ROM code, not by the NuttX interrupt since which was, up to this
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* point, uninitialized.
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*
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* Boot state: ROM is seen at address 0x00000000
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* Remap State 0: SRAM is seen at address 0x00000000 (through AHB slave
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* interface) instead of ROM.
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* Remap State 1: HEBI is seen at address 0x00000000 (through AHB slave
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* interface) instead of ROM for external boot.
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* Boot state: ROM is seen at address 0x00000000
|
||||
* Remap State 0: SRAM is seen at address 0x00000000 (through AHB slave
|
||||
* interface) instead of ROM.
|
||||
* Remap State 1: HEBI is seen at address 0x00000000 (through AHB slave
|
||||
* interface) instead of ROM for external boot.
|
||||
*
|
||||
* Here we are assuming that vectors reside in the lower end of ISRAM.
|
||||
* Hmmm... this probably does not matter since we will map a page to
|
||||
@ -299,6 +302,8 @@ void up_irqinitialize(void)
|
||||
|
||||
putreg32(MATRIX_MRCR_RCB0, SAM_MATRIX_MRCR); /* Enable remap */
|
||||
putreg32(AXIMX_REMAP_REMAP0, SAM_AXIMX_REMAP); /* Remap SRAM */
|
||||
|
||||
/* It might be wise to flush the instruction cache here */
|
||||
#endif
|
||||
|
||||
/* currents_regs is non-NULL only while processing an interrupt */
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user