Updated STM32 ADC driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4181 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
1b0f79e2bd
commit
f1b2a1ed8c
@ -190,7 +190,7 @@
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#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI 1 reset */
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#define RCC_APB2RSTR_TIM8RST (1 << 13) /* Bit 13: TIM8 Timer reset */
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#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */
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#define RCC_APB2RTST_ADC2RST (1 << 15) /* Bit 15: ADC3 interface reset */
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#define RCC_APB2RSTR_ADC3RST (1 << 15) /* Bit 15: ADC3 interface reset */
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/* APB1 Peripheral reset register */
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@ -95,18 +95,25 @@
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# define ADC_CR1_ALLINTS (ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_JEOCIE | ADC_CR1_OVRIE)
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#endif
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/* The maximum number of samples */
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#define ADC_MAX_SAMPLES 16
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This structure describes the state of one ADC block */
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struct stm32_dev_s
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{
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int irq; /* Interrupt generated by this ADC block */
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uint8_t irq; /* Interrupt generated by this ADC block */
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uint8_t nchannels; /* Number of channels */
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uint8_t intf; /* ADC interface number */
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xcpt_t isr; /* Interrupt handler for this ADC block */
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uint32_t base; /* Base address of registers unique to this ADC block */
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uint8_t chanlist[ADC_MAX_SAMPLES];
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int32_t buf[8];
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uint8_t count[8];
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};
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@ -118,19 +125,20 @@ struct stm32_dev_s
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/* ADC Register access */
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static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset);
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static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value);
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static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value);
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static void adc_rccreset(int regaddr, bool reset);
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/* ADC Interrupt Handler */
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static void adc_interrupt(FAR struct stm32_dev_s *priv);
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static int adc_interrupt(FAR struct stm32_dev_s *priv);
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#if defined(CONFIG_STM32_STM32F10XX) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2))
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static int adc12_interrupt(int irq, void *context)
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static int adc12_interrupt(int irq, void *context);
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#endif
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#ifdef CONFIG_STM32_STM32F10XX && defined (CONFIG_STM32_ADC3)
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static int adc3_interrupt(int irq, void *context)
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#if defined(CONFIG_STM32_STM32F10XX) && defined (CONFIG_STM32_ADC3)
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static int adc3_interrupt(int irq, void *context);
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#endif
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#ifdef CONFIG_STM32_STM32F40XX
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static int adc123_interrupt(int irq, void *context)
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static int adc123_interrupt(int irq, void *context);
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#endif
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/* ADC Driver Methods */
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@ -140,6 +148,7 @@ static int adc_setup(FAR struct adc_dev_s *dev);
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static void adc_shutdown(FAR struct adc_dev_s *dev);
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static void adc_rxint(FAR struct adc_dev_s *dev, bool enable);
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static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg);
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static void adc_enable(FAR struct adc_dev_s *dev, bool enable);
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/****************************************************************************
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* Private Data
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@ -168,6 +177,7 @@ static struct stm32_dev_s g_adcpriv1 =
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.irq = STM32_IRQ_ADC,
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.isr = adc123_interrupt,
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#endif
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.intf = 1;
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.base = STM32_ADC1_BASE,
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};
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@ -190,6 +200,7 @@ static struct stm32_dev_s g_adcpriv2 =
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.irq = STM32_IRQ_ADC,
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.isr = adc123_interrupt,
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#endif
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.intf = 2;
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.base = STM32_ADC2_BASE,
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};
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@ -212,6 +223,7 @@ static struct stm32_dev_s g_adcpriv3 =
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.irq = STM32_IRQ_ADC,
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.isr = adc123_interrupt,
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#endif
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.intf = 3;
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.base = STM32_ADC3_BASE,
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};
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@ -264,6 +276,108 @@ static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value)
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putreg32(value, priv->base + offset);
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}
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/****************************************************************************
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* Name: adc_rccreset
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*
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* Description:
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* Deinitializes the ADCx peripheral registers to their default
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* reset values. It could set all the ADCs configured.
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*
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* Input Parameters:
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* regaddr - The register to read
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* reset - Condition, set or reset
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*
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* Returned Value:
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*
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****************************************************************************/
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static void adc_rccreset(struct stm32_dev_s *priv, bool reset)
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{
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uint32_t regval;
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uint32_t adcbit;
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/* Pick the appropriate bit in the APB2 reset register */
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#ifdef CONFIG_STM32_STM32F10XX
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/* For the STM32 F1, there is an individual bit to reset each ADC. */
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switch (priv->intf)
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{
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#ifdef CONFIG_STM32_ADC1
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case 1:
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adcbit = RCC_APB2RSTR_ADC1RST;
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break;
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#endif
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#ifdef CONFIG_STM32_ADC2
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case 2:
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adcbit = RCC_APB2RSTR_ADC2RST;
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break;
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#endif
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#ifdef CONFIG_STM32_ADC3
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case 3:
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adcbit = RCC_APB2RSTR_ADC3RST;
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break;
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#endif
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default:
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return;
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}
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#else
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/* For the STM32 F4, there is one common reset for all ADC block.
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* THIS will probably cause some problems!
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*/
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adcbit = RCC_APB2RSTR_ADCRST;
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#endif
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/* Set or clear the selected bit in the APB2 reset register */
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regval = getreg32(STM32_RCC_APB2RSTR);
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if (reset)
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{
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/* Enable ADC reset state */
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regval |= adcbit;
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}
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else
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{
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/* Release ADC from reset state */
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regval &= ~adcbit;
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}
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putreg32(regval, STM32_RCC_APB2RSTR);
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}
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/*******************************************************************************
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* Name: adc_enable
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*
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* Description : Enables or disables the specified ADC peripheral.
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*
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* Input Parameters:
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*
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* enable - true: enable ADC convertion
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* false: disable ADC convertion
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*
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* Returned Value:
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*
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*******************************************************************************/
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static void adc_enable(FAR struct adc_dev_s *dev, bool enable)
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{
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FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
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uint32_t regval;
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regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
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if (enable)
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{
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regval |= ADC_CR2_ADON;
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}
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else
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{
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regval &= ~ADC_CR2_ADON;
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}
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adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
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}
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/****************************************************************************
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* Name: adc_reset
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*
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@ -279,15 +393,64 @@ static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value)
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static void adc_reset(FAR struct adc_dev_s *dev)
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{
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adbg("Initializing the ADC to the reset values \n");
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FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
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irqstate_t flags;
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uint32_t regval;
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uint32_t L = priv->nchannels;
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uint32_t ch;
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int offset = 0;
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flags = irqsave();
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/* Enable ADC reset state */
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adc_rccreset(priv, true);
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/* Release ADC from reset state */
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adc_rccreset(priv, false);
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/* Initialize the ADC data structures */
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/* ADC1 CR Configuration */
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/* Initialize the watchdog high threshold register */
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adc_putreg(priv, STM32_ADC_HTR_OFFSET, 0x00000fff);
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/* Initialize the watchdog low threshold register */
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adc_putreg(priv, STM32_ADC_LTR_OFFSET, 0x00000000);
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#ifdef CONFIG_STM32_STM32F40XX
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/* Initialize ADC Prescaler*/
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regval = getreg32(STM32_ADC_CCR_OFFSET);
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/* PCLK2 divided by 2 */
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regval &= ~ADC_CCR_ADCPRE_MASK;
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putreg32(regval,STM32_ADC_CCR_OFFSET);
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#endif
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/* Initialize the same sample time for each ADC 1.5 cycles
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*
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* During sample cycles channel selection bits must remain unchanged.
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*
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* 000: 1.5 cycles
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* 001: 7.5 cycles
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* 010: 13.5 cycles
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* 011: 28.5 cycles
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* 100: 41.5 cycles
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* 101: 55.5 cycles
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* 110: 71.5 cycles
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* 111: 239.5 cycles
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*/
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adc_putreg(priv,STM32_ADC_SMPR1_OFFSET,0x00000000);
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adc_putreg(priv,STM32_ADC_SMPR2_OFFSET,0x00000000);
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/* ADC CR1 Configuration */
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regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET);
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regval &= ~ADC_CR1_DUALMOD_MASK;
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@ -305,6 +468,12 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval);
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/* ADC1 CR2 Configuration */
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/* Set the ADON bit to wake up the ADC from power down mode */
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regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
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regval |= ADC_CR2_ADON;
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/* Clear CONT, ALIGN and EXTTRIG bits */
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regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
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@ -328,13 +497,183 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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regval &= ~ADC_CR2_CONT;
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adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
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/* ADC1 SQR1 Configuration */
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/* ADC1 SQR Configuration */
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L = L << 20;
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regval = adc_getreg(priv, STM32_ADC_SQR1_OFFSET);
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regval &= ~ADC_SQR1_L_MASK; /* L = 0000: 1 conversion */
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adc_putreg(priv, STM32_ADC_SQR_OFFSET1, regval);
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regval &= ~ADC_SQR1_L_MASK; /* Clear L Mask */
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regval |= L; /* SetL, # of convertions */
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adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval);
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irqrestore(flags);
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/* Configuration of the channels convertions */
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#warning "I can improve the ugly code below with a logic using offsets"
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#warning "Or.. better yet, a loop"
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regval = adc_getreg(priv, STM32_ADC_SQR3_OFFSET);
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if (priv->nchannels >= 1)
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{
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ch = priv->chanlist[0];
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ch <<= offset;
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regval &= ~ADC_SQR3_SQ1_MASK; /* clear SQ1 */
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regval |= ch; /* Set SQ1 */
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adc_putreg(priv, STM32_ADC_SQR3_OFFSET, regval);
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offset += 5;
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}
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if (priv->nchannels >= 2)
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{
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ch = priv->chanlist[1];
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ch <<= offset;
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regval &= ~ADC_SQR3_SQ2_MASK; /* clear SQ2 */
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regval |= ch; /* Set SQ2 */
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adc_putreg(priv, STM32_ADC_SQR3_OFFSET, regval);
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offset += 5;
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}
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if (priv->nchannels >= 3)
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{
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ch = priv->chanlist[2];
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ch <<= offset;
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regval &= ~ADC_SQR3_SQ3_MASK; /* clear SQ3 */
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regval |= ch; /* SetSQ3 */
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adc_putreg(priv, STM32_ADC_SQR3_OFFSET, regval);
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offset += 5;
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}
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if (priv->nchannels >= 4)
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{
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ch = priv->chanlist[3];
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ch <<= offset;
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regval &= ~ADC_SQR3_SQ4_MASK; /* clear SQ4 */
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regval |= ch; /* SetSQ4 */
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adc_putreg(priv, STM32_ADC_SQR3_OFFSET, regval);
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offset += 5;
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}
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if (priv->nchannels >= 5)
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{
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ch = priv->chanlist[4];
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ch <<= offset;
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regval &= ~ADC_SQR3_SQ5_MASK; /* clear SQ5 */
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regval |= ch; /* SetSQ5 */
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adc_putreg(priv, STM32_ADC_SQR3_OFFSET, regval);
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offset += 5;
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}
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if (priv->nchannels >= 6)
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{
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ch = priv->chanlist[5];
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ch <<= offset;
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regval &= ~ADC_SQR3_SQ6_MASK; /* clear SQ6 */
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regval |= ch; /* SetSQ6 */
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adc_putreg(priv, STM32_ADC_SQR3_OFFSET, regval);
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offset = 0;
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}
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if (priv->nchannels >= 7)
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{
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ch = priv->chanlist[6];
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ch <<= offset;
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regval &= ~ADC_SQR2_SQ7_MASK; /* clear SQ7 */
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regval |= ch; /* SetSQ7 */
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adc_putreg(priv, STM32_ADC_SQR2_OFFSET, regval);
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offset += 5;
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}
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if (priv->nchannels >= 8)
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{
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ch = priv->chanlist[7];
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ch <<= offset;
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regval &= ~ADC_SQR2_SQ8_MASK; /* clear SQ8 */
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regval |= ch; /* SetSQ8 */
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adc_putreg(priv, STM32_ADC_SQR2_OFFSET, regval);
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offset += 5;
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}
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if (priv->nchannels >= 9)
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{
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ch = priv->chanlist[8];
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ch <<= offset;
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regval &= ~ADC_SQR2_SQ9_MASK; /* clear SQ9 */
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regval |= ch; /* SetSQ9 */
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adc_putreg(priv, STM32_ADC_SQR2_OFFSET, regval);
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offset += 5;
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}
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if (priv->nchannels >= 10)
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{
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ch = priv->chanlist[9];
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ch <<= offset;
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regval &= ~ADC_SQR2_SQ10_MASK; /* clear SQ10 */
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regval |= ch; /* SetSQ10 */
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adc_putreg(priv, STM32_ADC_SQR2_OFFSET, regval);
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offset += 5;
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}
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if (priv->nchannels >= 11)
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{
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ch = priv->chanlist[10];
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ch <<= offset;
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regval &= ~ADC_SQR2_SQ11_MASK; /* clear SQ11 */
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regval |= ch; /* SetSQ11 */
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adc_putreg(priv, STM32_ADC_SQR2_OFFSET, regval);
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offset += 5;
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}
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if (priv->nchannels >= 12)
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{
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ch = priv->chanlist[11];
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ch <<= offset;
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regval &= ~ADC_SQR2_SQ12_MASK; /* clear SQ12 */
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regval |= ch; /* SetSQ12 */
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adc_putreg(priv, STM32_ADC_SQR2_OFFSET, regval);
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offset = 0;
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}
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if (priv->nchannels >= 13)
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{
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ch = priv->chanlist[12];
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ch <<= offset;
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regval &= ~ADC_SQR1_SQ13_MASK; /* clear SQ13 */
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regval |= ch; /* SetSQ13 */
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adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval);
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offset += 5;
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}
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if (priv->nchannels >= 14)
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{
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ch = priv->chanlist[13];
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ch <<= offset;
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regval &= ~ADC_SQR1_SQ14_MASK; /* clear SQ14 */
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regval |= ch; /* SetSQ14 */
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adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval);
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offset += 5;
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}
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if (priv->nchannels >= 15)
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{
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ch = priv->chanlist[14];
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ch <<= offset;
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regval &= ~ADC_SQR1_SQ15_MASK; /* clear SQ15 */
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regval |= ch; /* SetSQ15 */
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adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval);
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offset += 5;
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}
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if (priv->nchannels >= 16)
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{
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ch = priv->chanlist[15];
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ch <<= offset;
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regval &= ~ADC_SQR1_SQ16_MASK; /* clear SQ16 */
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regval |= ch; /* SetSQ16 */
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adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval);
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}
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if (priv->nchannels >= 17)
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{
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adbg("ERROR: Number of channels exceeded\n");
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}
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irqrestore(flags);
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}
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/****************************************************************************
|
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@ -356,7 +695,6 @@ static int adc_setup(FAR struct adc_dev_s *dev)
|
||||
{
|
||||
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
|
||||
int ret;
|
||||
uint32_t regval = 0;
|
||||
int i;
|
||||
/* Attach the ADC interrupt */
|
||||
|
||||
@ -373,6 +711,7 @@ static int adc_setup(FAR struct adc_dev_s *dev)
|
||||
|
||||
up_enable_irq(priv->irq);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -418,7 +757,7 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
|
||||
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
|
||||
uint32_t regval;
|
||||
|
||||
uint32_t adc_getreg(priv, STM32_ADC_CR1_OFFSET);
|
||||
regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET);
|
||||
if (enable)
|
||||
{
|
||||
/* Enable the end-of-conversion ADC interrupt */
|
||||
@ -463,24 +802,38 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void adc_interrupt(FAR struct stm32_dev_s *priv)
|
||||
static int adc_interrupt(FAR struct stm32_dev_s *priv)
|
||||
{
|
||||
uint32_t regval;
|
||||
unsigned char ch; /* channel */
|
||||
int32_t value;
|
||||
uint32_t adcsr;
|
||||
int32_t value;
|
||||
uint8_t ch;
|
||||
int i;
|
||||
|
||||
regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET);
|
||||
regval &= ADC_CR1_AWDCH_MASK;
|
||||
ch = regval;
|
||||
/* Identifies the interruption AWD or EOC */
|
||||
|
||||
adcsr = adc_getreg(priv, STM32_ADC_SR_OFFSET);
|
||||
if ((adcsr & ADC_SR_AWD) != 0)
|
||||
{
|
||||
adbg(" Analog Watchdog, Value converted out of range!\n");
|
||||
}
|
||||
|
||||
/* EOC: End of conversion */
|
||||
|
||||
/* Handle the ADC interrupt */
|
||||
if ((adcsr & ADC_SR_EOC) != 0)
|
||||
{
|
||||
value = adc_getreg(priv, STM32_ADC_DR_OFFSET);
|
||||
value &= ADC_DR_DATA_MASK;
|
||||
#error "i is not assigned a value"
|
||||
ch = priv->chanlist[i]; /* Channel converted */
|
||||
|
||||
/* Handle the ADC interrupt */
|
||||
|
||||
# warning "still missing logic, value computation"
|
||||
adc_receive(priv, ch, value);
|
||||
priv->buf[ch] = 0;
|
||||
priv->count[ch] = 0;
|
||||
adc_receive(priv, ch, value);
|
||||
priv->buf[ch] = 0;
|
||||
priv->count[ch] = 0;
|
||||
}
|
||||
|
||||
return OK;
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -498,13 +851,13 @@ static void adc_interrupt(FAR struct stm32_dev_s *priv)
|
||||
#if defined(CONFIG_STM32_STM32F10XX) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2))
|
||||
static int adc12_interrupt(int irq, void *context)
|
||||
{
|
||||
uint32_regval;
|
||||
uint32_t regval;
|
||||
uint32_t pending;
|
||||
|
||||
/* Check for pending ADC1 interrupts */
|
||||
|
||||
#ifdef CONFIG_STM32_ADC1
|
||||
regval = getreg32(priv, STM32_ADC1_SR);
|
||||
regval = getreg32(STM32_ADC1_SR);
|
||||
pending = regval & ADC_SR_ALLINTS;
|
||||
if (pending != 0)
|
||||
{
|
||||
@ -517,7 +870,7 @@ static int adc12_interrupt(int irq, void *context)
|
||||
/* Check for pending ADC2 interrupts */
|
||||
|
||||
#ifdef CONFIG_STM32_ADC2
|
||||
regval = getreg32(priv, STM32_ADC2_SR);
|
||||
regval = getreg32(STM32_ADC2_SR);
|
||||
pending = regval & ADC_SR_ALLINTS;
|
||||
if (pending != 0)
|
||||
{
|
||||
@ -542,7 +895,7 @@ static int adc12_interrupt(int irq, void *context)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F10XX && defined (CONFIG_STM32_ADC3)
|
||||
#if defined (CONFIG_STM32_STM32F10XX) && defined (CONFIG_STM32_ADC3)
|
||||
static int adc3_interrupt(int irq, void *context)
|
||||
{
|
||||
uint32_t regval;
|
||||
@ -550,7 +903,7 @@ static int adc3_interrupt(int irq, void *context)
|
||||
|
||||
/* Check for pending ADC3 interrupts */
|
||||
|
||||
regval = getreg32(priv, STM32_ADC3_SR);
|
||||
regval = getreg32(STM32_ADC3_SR);
|
||||
pending = regval & ADC_SR_ALLINTS;
|
||||
if (pending != 0)
|
||||
{
|
||||
@ -584,7 +937,7 @@ static int adc123_interrupt(int irq, void *context)
|
||||
/* Check for pending ADC1 interrupts */
|
||||
|
||||
#ifdef CONFIG_STM32_ADC1
|
||||
regval = getreg32(priv, STM32_ADC1_SR);
|
||||
regval = getreg32(STM32_ADC1_SR);
|
||||
pending = regval & ADC_SR_ALLINTS;
|
||||
if (pending != 0)
|
||||
{
|
||||
@ -597,7 +950,7 @@ static int adc123_interrupt(int irq, void *context)
|
||||
/* Check for pending ADC2 interrupts */
|
||||
|
||||
#ifdef CONFIG_STM32_ADC2
|
||||
regval = getreg32(priv, STM32_ADC2_SR);
|
||||
regval = getreg32(STM32_ADC2_SR);
|
||||
pending = regval & ADC_SR_ALLINTS;
|
||||
if (pending != 0)
|
||||
{
|
||||
@ -610,7 +963,7 @@ static int adc123_interrupt(int irq, void *context)
|
||||
/* Check for pending ADC3 interrupts */
|
||||
|
||||
#ifdef CONFIG_STM32_ADC3
|
||||
regval = getreg32(priv, STM32_ADC3_SR);
|
||||
regval = getreg32(STM32_ADC3_SR);
|
||||
pending = regval & ADC_SR_ALLINTS;
|
||||
if (pending != 0)
|
||||
{
|
||||
@ -628,45 +981,74 @@ static int adc123_interrupt(int irq, void *context)
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_adcinitialize
|
||||
* Name: stm32_adcinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the adc
|
||||
* Initialize the ADC. The logic is, save nchannels : # of channels
|
||||
* (conversions) in ADC_SQR1_L
|
||||
* Then, take the chanlist array and store it in the SQR Regs,
|
||||
* chanlist[0] -> ADC_SQR3_SQ1
|
||||
* chanlist[1] -> ADC_SQR3_SQ2
|
||||
* chanlist[2] -> ADC_SQR3_SQ3
|
||||
* chanlist[3] -> ADC_SQR3_SQ4
|
||||
* chanlist[4] -> ADC_SQR3_SQ5
|
||||
* chanlist[5] -> ADC_SQR3_SQ6
|
||||
* ...
|
||||
* chanlist[15]-> ADC_SQR1_SQ16
|
||||
*
|
||||
* up to
|
||||
* chanlist[nchannels]
|
||||
*
|
||||
* Input Parameters:
|
||||
* intf - Could be {1,2,3} for ADC1, ADC2, or ADC3
|
||||
* chanlist - The list of channels
|
||||
* nchannels - Number of channels
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid can device structure reference on succcess; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct adc_dev_s *up_adcinitialize(int intf)
|
||||
struct adc_dev_s *stm32_adcinitialize(int intf, uint8_t *chanlist, int nchannels)
|
||||
{
|
||||
# warning "Question: How do you plan to handle the ADC channels? Can we do"
|
||||
# " 16 or 18 individual channels? or one group?"
|
||||
|
||||
FAR struct adc_dev_s *dev;
|
||||
FAR struct stm32_dev_s *priv;
|
||||
|
||||
#ifdef CONFIG_STM32_ADC1
|
||||
if (intf == 1)
|
||||
{
|
||||
return &g_adcdev1;
|
||||
adbg("ADC1 Selected \n");
|
||||
dev = &g_adcdev1;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_ADC2
|
||||
if (intf == 2)
|
||||
{
|
||||
return &g_adcdev2;
|
||||
adbg("ADC2 Selected \n");
|
||||
dev = &g_adcdev2;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_ADC3
|
||||
if (intf == 3)
|
||||
{
|
||||
return &g_adcdev3;
|
||||
adbg("ADC3 Selected \n");
|
||||
dev = &g_adcdev3;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
adbg("No ADC interface defined\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Configure the selected ADC */
|
||||
|
||||
priv = dev->ad_priv;
|
||||
priv->nchannels = nchannels;
|
||||
memcpy(priv->chanlist, chanlist, nchannels);
|
||||
return dev;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STM32_ADC || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user