configs/lpcxpresso-lpc54628: Add the fb configuration testing the LCD. arch/arm/src/lpc54xx: Various fixes needed to get the fb configuration to build errorfree. The configuration is not functional as of this writing.
This commit is contained in:
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48879933a9
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@ -723,18 +723,18 @@ config LPC54_LCD_BPP24_RGB565
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bool "24 BPP, 5:6:5 mode"
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bool "24 BPP, 5:6:5 mode"
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depends on !LPC54_LCD_MONOCHROME && LPC54_LCD_TFTPANEL
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depends on !LPC54_LCD_MONOCHROME && LPC54_LCD_TFTPANEL
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---help---
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---help---
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16-bit color is, by default, provide on LCD VD0-VD15; 24-bit color
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16-bit color is, by default, provided on LCD VD0-VD15; 24-bit color
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is provided on VD0-23:
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is provided on VD0-23:
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RRRRRGGG GGGB BBBB
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16-bit: RRRRRGGG GGGB BBBB
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........ RRRRRRRR GGGGGGGG BBBBBBBB
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24-bit: ........ RRRRRRRR GGGGGGGG BBBBBBBB
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This option selects an alternative pin configuration where 16-bit
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This option selects an alternative pin configuration where 16-bit
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RGB565 is provided on VD3-7, VD10-15, and VD19-23. This essentially
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RGB565 is provided on VD3-7, VD10-15, and VD19-23. This essentially
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accepts 32-bit RGB888 color as input but only uses the RGB565 color
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accepts 32-bit RGB888 color as input but only uses the RGB565 color
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resolution:
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resolution:
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........ RRRRR... GGGGGG.. BBBBB...
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24-bit: ........ RRRRR... GGGGGG.. BBBBB...
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config LPC54_LCD_BPP24
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config LPC54_LCD_BPP24
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bool "24 BPP, 8:8:8 mode"
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bool "24 BPP, 8:8:8 mode"
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@ -46,6 +46,7 @@
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#include <nuttx/arch.h>
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#include <nuttx/arch.h>
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#include <nuttx/board.h>
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#include <nuttx/board.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/userspace.h>
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#include <nuttx/userspace.h>
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#include "up_arch.h"
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#include "up_arch.h"
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@ -103,7 +104,7 @@
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# if defined(CONFIG_LPC54_EMC_STATIC_CS1) && CONFIG_LPC54_EMC_STATIC_CS1_SIZE > 0
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# if defined(CONFIG_LPC54_EMC_STATIC_CS1) && CONFIG_LPC54_EMC_STATIC_CS1_SIZE > 0
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# define HAVE_STATIC_CS1 1
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# define HAVE_STATIC_CS1 1
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# endif
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# endif
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# if defined(CONFIG_LPC54_EMC_STATIC_CS0) && CONFIG_LPC54_EMC_STATIC_CS0_SIZE > 0
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# if defined(CONFIG_LPC54_EMC_STATIC_CS2) && CONFIG_LPC54_EMC_STATIC_CS2_SIZE > 0
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# define HAVE_STATIC_CS2 1
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# define HAVE_STATIC_CS2 1
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# endif
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# endif
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# if defined(CONFIG_LPC54_EMC_STATIC_CS3) && CONFIG_LPC54_EMC_STATIC_CS3_SIZE > 0
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# if defined(CONFIG_LPC54_EMC_STATIC_CS3) && CONFIG_LPC54_EMC_STATIC_CS3_SIZE > 0
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@ -117,7 +118,7 @@
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# if defined(CONFIG_LPC54_EMC_DYNAMIC_CS1) && CONFIG_LPC54_EMC_DYNAMIC_CS1_SIZE > 0
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# if defined(CONFIG_LPC54_EMC_DYNAMIC_CS1) && CONFIG_LPC54_EMC_DYNAMIC_CS1_SIZE > 0
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# define HAVE_DYNAMIC_CS1 1
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# define HAVE_DYNAMIC_CS1 1
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# endif
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# endif
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# if defined(CONFIG_LPC54_EMC_DYNAMIC_CS0) && CONFIG_LPC54_EMC_DYNAMIC_CS0_SIZE > 0
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# if defined(CONFIG_LPC54_EMC_DYNAMIC_CS2) && CONFIG_LPC54_EMC_DYNAMIC_CS2_SIZE > 0
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# define HAVE_DYNAMIC_CS2 1
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# define HAVE_DYNAMIC_CS2 1
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# endif
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# endif
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# if defined(CONFIG_LPC54_EMC_DYNAMIC_CS3) && CONFIG_LPC54_EMC_DYNAMIC_CS3_SIZE > 0
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# if defined(CONFIG_LPC54_EMC_DYNAMIC_CS3) && CONFIG_LPC54_EMC_DYNAMIC_CS3_SIZE > 0
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@ -126,7 +127,6 @@
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# endif /* CONFIG_LPC54_EMC_DYNAMIC */
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# endif /* CONFIG_LPC54_EMC_DYNAMIC */
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#endif /* CONFIG_LPC54_EMC */
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#endif /* CONFIG_LPC54_EMC */
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/****************************************************************************
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/****************************************************************************
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* Public Data
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* Public Data
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****************************************************************************/
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****************************************************************************/
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@ -271,7 +271,7 @@ void up_addregion(void)
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heapstart = (FAR void *)(LPC54_SRAMCS0_BASE + CONFIG_LPC54_EMC_STATIC_CS0_OFFSET);
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heapstart = (FAR void *)(LPC54_SRAMCS0_BASE + CONFIG_LPC54_EMC_STATIC_CS0_OFFSET);
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heapsize = CONFIG_LPC54_EMC_STATIC_CS0_SIZE;
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heapsize = CONFIG_LPC54_EMC_STATIC_CS0_SIZE;
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mem_addregion(heapstart, heapsize);
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kumm_addregion(heapstart, heapsize);
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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/* Allow user-mode access to the SDRAM heap */
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/* Allow user-mode access to the SDRAM heap */
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@ -289,7 +289,7 @@ void up_addregion(void)
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heapstart = (FAR void *)(LPC54_SRAMCS1_BASE + CONFIG_LPC54_EMC_STATIC_CS1_OFFSET);
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heapstart = (FAR void *)(LPC54_SRAMCS1_BASE + CONFIG_LPC54_EMC_STATIC_CS1_OFFSET);
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heapsize = CONFIG_LPC54_EMC_STATIC_CS1_SIZE;
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heapsize = CONFIG_LPC54_EMC_STATIC_CS1_SIZE;
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mem_addregion(heapstart, heapsize);
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kumm_addregion(heapstart, heapsize);
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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/* Allow user-mode access to the SDRAM heap */
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/* Allow user-mode access to the SDRAM heap */
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@ -307,7 +307,7 @@ void up_addregion(void)
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heapstart = (FAR void *)(LPC54_SRAMCS2_BASE + CONFIG_LPC54_EMC_STATIC_CS2_OFFSET);
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heapstart = (FAR void *)(LPC54_SRAMCS2_BASE + CONFIG_LPC54_EMC_STATIC_CS2_OFFSET);
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heapsize = CONFIG_LPC54_EMC_STATIC_CS2_SIZE;
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heapsize = CONFIG_LPC54_EMC_STATIC_CS2_SIZE;
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mem_addregion(heapstart, heapsize);
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kumm_addregion(heapstart, heapsize);
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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/* Allow user-mode access to the SDRAM heap */
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/* Allow user-mode access to the SDRAM heap */
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@ -325,7 +325,7 @@ void up_addregion(void)
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heapstart = (FAR void *)(LPC54_SRAMCS3_BASE + CONFIG_LPC54_EMC_STATIC_CS3_OFFSET);
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heapstart = (FAR void *)(LPC54_SRAMCS3_BASE + CONFIG_LPC54_EMC_STATIC_CS3_OFFSET);
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heapsize = CONFIG_LPC54_EMC_STATIC_CS3_SIZE;
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heapsize = CONFIG_LPC54_EMC_STATIC_CS3_SIZE;
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mem_addregion(heapstart, heapsize);
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kumm_addregion(heapstart, heapsize);
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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/* Allow user-mode access to the SDRAM heap */
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/* Allow user-mode access to the SDRAM heap */
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@ -341,9 +341,9 @@ void up_addregion(void)
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{
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{
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/* Add the SDRAM to the user heap */
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/* Add the SDRAM to the user heap */
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heapstart = (FAR void *)(LPC54_DRAMCS2_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS0_OFFSET);
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heapstart = (FAR void *)(LPC54_DRAMCS0_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS0_OFFSET);
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heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS0_SIZE;
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heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS0_SIZE;
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mem_addregion(heapstart, heapsize);
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kumm_addregion(heapstart, heapsize);
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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/* Allow user-mode access to the SDRAM heap */
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/* Allow user-mode access to the SDRAM heap */
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@ -361,7 +361,7 @@ void up_addregion(void)
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heapstart = (FAR void *)(LPC54_DRAMCS1_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS1_OFFSET);
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heapstart = (FAR void *)(LPC54_DRAMCS1_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS1_OFFSET);
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heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS1_SIZE;
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heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS1_SIZE;
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mem_addregion(heapstart, heapsize);
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kumm_addregion(heapstart, heapsize);
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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/* Allow user-mode access to the SDRAM heap */
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/* Allow user-mode access to the SDRAM heap */
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@ -379,7 +379,7 @@ void up_addregion(void)
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heapstart = (FAR void *)(LPC54_DRAMCS2_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS2_OFFSET);
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heapstart = (FAR void *)(LPC54_DRAMCS2_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS2_OFFSET);
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heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS2_SIZE;
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heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS2_SIZE;
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mem_addregion(heapstart, heapsize);
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kumm_addregion(heapstart, heapsize);
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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/* Allow user-mode access to the SDRAM heap */
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/* Allow user-mode access to the SDRAM heap */
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@ -397,7 +397,7 @@ void up_addregion(void)
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heapstart = (FAR void *)(LPC54_DRAMCS3_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS3_OFFSET);
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heapstart = (FAR void *)(LPC54_DRAMCS3_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS3_OFFSET);
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heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS3_SIZE;
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heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS3_SIZE;
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mem_addregion(heapstart, heapsize);
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kumm_addregion(heapstart, heapsize);
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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/* Allow user-mode access to the SDRAM heap */
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/* Allow user-mode access to the SDRAM heap */
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@ -4,6 +4,9 @@
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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*
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* This driver derives from the LPC1788 LCD driver. The LPC1788 LCD is
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* identical tot he LPC54628 LCD other than some minor clocking differences.
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* modification, are permitted provided that the following conditions
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* are met:
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* are met:
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@ -45,13 +48,15 @@
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#include <debug.h>
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#include <debug.h>
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#include <nuttx/video/fb.h>
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#include <nuttx/video/fb.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "up_arch.h"
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#include "chip/lpc54_syscon.h"
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#include "chip/lpc54_syscon.h"
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#include "chip/lpc54_pinmux.h"
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#include "lpc54_gpio.h"
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#include "lpc54_gpio.h"
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#include "lpc54_lcd.h"
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#include "lpc54_lcd.h"
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#include <arch/board/board.h>
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/****************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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* Pre-processor Definitions
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****************************************************************************/
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****************************************************************************/
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@ -474,8 +479,6 @@ int up_fbinitialize(int display)
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uint32_t lcddiv;
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uint32_t lcddiv;
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int i;
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int i;
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lcdinfo("Entry\n");
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/* Configure pins */
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/* Configure pins */
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/* LCD panel data. Pins used depend on the panel configuration */
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/* LCD panel data. Pins used depend on the panel configuration */
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@ -503,12 +506,12 @@ int up_fbinitialize(int display)
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lpc54_gpio_config(GPIO_LCD_VD14);
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lpc54_gpio_config(GPIO_LCD_VD14);
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lpc54_gpio_config(GPIO_LCD_VD15);
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lpc54_gpio_config(GPIO_LCD_VD15);
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#if LPC54_BPP > 16 && !defined(CONFIG_LPC54_LCD_BPP24_RGB565)
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#if LPC54_BPP > 16
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#ifndef CONFIG_LPC54_LCD_BPP24_RGB565
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lpc54_gpio_config(GPIO_LCD_VD16);
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lpc54_gpio_config(GPIO_LCD_VD16);
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lpc54_gpio_config(GPIO_LCD_VD17);
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lpc54_gpio_config(GPIO_LCD_VD17);
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lpc54_gpio_config(GPIO_LCD_VD18);
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lpc54_gpio_config(GPIO_LCD_VD18);
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#endif
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#endif
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#if LPC54_BPP > 16
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lpc54_gpio_config(GPIO_LCD_VD19);
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lpc54_gpio_config(GPIO_LCD_VD19);
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lpc54_gpio_config(GPIO_LCD_VD20);
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lpc54_gpio_config(GPIO_LCD_VD20);
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lpc54_gpio_config(GPIO_LCD_VD21);
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lpc54_gpio_config(GPIO_LCD_VD21);
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@ -531,7 +534,7 @@ int up_fbinitialize(int display)
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lpc54_gpio_config(GPIO_LCD_CLKIN); /* Optional clock input */
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lpc54_gpio_config(GPIO_LCD_CLKIN); /* Optional clock input */
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#endif
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#endif
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/* Route Main clock (or LCK CLKIN) to LCD. */
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/* Route Main clock (or LCK CLKIN) to the LCD. */
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#ifdef CONFIG_LPC54_LCD_USE_CLKIN
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#ifdef CONFIG_LPC54_LCD_USE_CLKIN
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putreg32(SYSCON_LCDCLKSEL_LCDCLKIN, LPC54_SYSCON_LCDCLKSEL);
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putreg32(SYSCON_LCDCLKSEL_LCDCLKIN, LPC54_SYSCON_LCDCLKSEL);
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@ -551,7 +554,7 @@ int up_fbinitialize(int display)
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putreg32(LCD_INTCLR_ALL, LPC54_LCD_INTCLR);
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putreg32(LCD_INTCLR_ALL, LPC54_LCD_INTCLR);
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/* Disable GLCD controller */
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/* Disable the LCD controller */
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putreg32(0, LPC54_LCD_CTRL);
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putreg32(0, LPC54_LCD_CTRL);
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@ -559,9 +562,9 @@ int up_fbinitialize(int display)
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#ifdef CONFIG_LPC54_LCD_USE_CLKIN
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#ifdef CONFIG_LPC54_LCD_USE_CLKIN
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lcddiv = ((uint32_t)CONFIG_LPC54_LCD_CLKIN_FREQUENCY /
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lcddiv = ((uint32_t)CONFIG_LPC54_LCD_CLKIN_FREQUENCY /
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(uint32_t)LPC54_LCD_PIXEL_CLOCK) + 1
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(uint32_t)LPC54_LCD_PIXEL_CLOCK) + 1;
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#else
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#else
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lcddiv = ((uint32_t)BOARD_MAIN_CLK / (uint32_t)LPC54_LCD_PIXEL_CLOCK) + 1
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lcddiv = ((uint32_t)BOARD_MAIN_CLK / (uint32_t)LPC54_LCD_PIXEL_CLOCK) + 1;
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#endif
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#endif
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putreg32(lcddiv, LPC54_SYSCON_LCDCLKDIV);
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putreg32(lcddiv, LPC54_SYSCON_LCDCLKDIV);
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putreg32(lcddiv | SYSCON_LCDCLKDIV_REQFLAG, LPC54_SYSCON_LCDCLKDIV);
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putreg32(lcddiv | SYSCON_LCDCLKDIV_REQFLAG, LPC54_SYSCON_LCDCLKDIV);
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@ -654,7 +657,10 @@ int up_fbinitialize(int display)
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(CONFIG_LPC54_LCD_VBACKPORCH) << LCD_TIMV_VBP_SHIFT);
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(CONFIG_LPC54_LCD_VBACKPORCH) << LCD_TIMV_VBP_SHIFT);
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putreg32(regval, LPC54_LCD_TIMV);
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putreg32(regval, LPC54_LCD_TIMV);
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/* Initialize clock and signal polarity */
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/* Initialize clock and signal polarity.
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*
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* REVISIT: These need to be configurable.
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*/
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regval = getreg32(LPC54_LCD_POL);
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regval = getreg32(LPC54_LCD_POL);
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@ -681,10 +687,6 @@ int up_fbinitialize(int display)
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/* LCD_ENAB_M is active high */
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/* LCD_ENAB_M is active high */
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regval &= ~LCD_POL_IOE;
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regval &= ~LCD_POL_IOE;
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/* Select CCLK for the LCD block clock source */
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regval &= ~LCD_POL_CLKSEL;
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putreg32(regval, LPC54_LCD_POL);
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putreg32(regval, LPC54_LCD_POL);
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/* Frame base address doubleword aligned */
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/* Frame base address doubleword aligned */
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@ -321,10 +321,10 @@ static const struct uart_config_s g_console_config=
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static void lp54_setbaud(uintptr_t base, FAR const struct uart_config_s *config)
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static void lp54_setbaud(uintptr_t base, FAR const struct uart_config_s *config)
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{
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{
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uint32_t bestdiff = (uint32_t)-1;
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uint32_t bestdiff = (uint32_t)-1;
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uint32_t bestosr = 15;
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uint32_t bestosr = 15;
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uint32_t bestbrg = (uint32_t)-1;
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uint32_t bestbrg = (uint32_t)-1;
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uint32_t lastosr;
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uint32_t lastosr = 0; /* Initialized only to avoid warnings */
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uint32_t lastbrg;
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uint32_t lastbrg = 0;
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uint32_t osr;
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uint32_t osr;
|
||||||
uint32_t brg;
|
uint32_t brg;
|
||||||
uint32_t diff;
|
uint32_t diff;
|
||||||
|
@ -38,8 +38,11 @@ STATUS
|
|||||||
external SDRAM to the system heap. Brought in the LPC1788 LCD driver.
|
external SDRAM to the system heap. Brought in the LPC1788 LCD driver.
|
||||||
The LPC1788 LCD registers are identical to the LPC54xx (other than a
|
The LPC1788 LCD registers are identical to the LPC54xx (other than a
|
||||||
minor clock source setting). That port required modifications only
|
minor clock source setting). That port required modifications only
|
||||||
for differences in some SYSCON and pin-related settings. No testing
|
for differences in some SYSCON and pin-related settings.
|
||||||
has yet been performed.
|
2017-12-13: Created the fb configuration for testing the LCD. Only
|
||||||
|
minimal testing has been performed. As of this writing, there is
|
||||||
|
no video output from the apps/examples/fb test: The backlight is on
|
||||||
|
but the display is blank/white.
|
||||||
|
|
||||||
Configurations
|
Configurations
|
||||||
==============
|
==============
|
||||||
@ -100,6 +103,29 @@ Configurations
|
|||||||
Configuration sub-directories
|
Configuration sub-directories
|
||||||
-----------------------------
|
-----------------------------
|
||||||
|
|
||||||
|
fb:
|
||||||
|
|
||||||
|
A simple NSH configuration used for some basic debug of LCD using the
|
||||||
|
framebuffer character drivers. This configuration provides the test
|
||||||
|
programs:
|
||||||
|
|
||||||
|
- apps/examples/pdcurses, and
|
||||||
|
- apps/examples/fb
|
||||||
|
|
||||||
|
as NSH built-in applications.
|
||||||
|
|
||||||
|
NOTES:
|
||||||
|
1, This configuration enables SDRAM to hold the LCD framebuffer and
|
||||||
|
enables the LPC54xx LCD driver in order to support the LPCXpresso's
|
||||||
|
TFT panel. In this configuration, the framebuffer resides in the
|
||||||
|
the lower half megabyte of SDRAM beginning at address 0xa0000000
|
||||||
|
(only 522,240 bytes actually used for the framebuffer). The
|
||||||
|
remainder of the SDRAM from 0xa0080000 up to 0xa1000000 is added
|
||||||
|
to the heap.
|
||||||
|
|
||||||
|
2. The pdcurses test relies on some positional input device and so
|
||||||
|
is not yet usable.
|
||||||
|
|
||||||
nsh:
|
nsh:
|
||||||
|
|
||||||
Configures the NuttShell (nsh) application located at examples/nsh.
|
Configures the NuttShell (nsh) application located at examples/nsh.
|
||||||
|
63
configs/lpcxpresso-lpc54628/fb/defconfig
Normal file
63
configs/lpcxpresso-lpc54628/fb/defconfig
Normal file
@ -0,0 +1,63 @@
|
|||||||
|
# CONFIG_ARCH_FPU is not set
|
||||||
|
CONFIG_ARCH_BOARD_LPCXPRESSO_LPC54628=y
|
||||||
|
CONFIG_ARCH_BOARD="lpcxpresso-lpc54628"
|
||||||
|
CONFIG_ARCH_CHIP_LPC54628=y
|
||||||
|
CONFIG_ARCH_CHIP_LPC54XX=y
|
||||||
|
CONFIG_ARCH_STACKDUMP=y
|
||||||
|
CONFIG_ARCH_STDARG_H=y
|
||||||
|
CONFIG_ARCH="arm"
|
||||||
|
CONFIG_BOARD_LOOPSPERMSEC=18535
|
||||||
|
CONFIG_BUILTIN=y
|
||||||
|
CONFIG_DRIVERS_VIDEO=y
|
||||||
|
CONFIG_EXAMPLES_FB=y
|
||||||
|
CONFIG_EXAMPLES_NSH=y
|
||||||
|
CONFIG_EXAMPLES_PDCURSES=y
|
||||||
|
CONFIG_FAT_LCNAMES=y
|
||||||
|
CONFIG_FAT_LFN=y
|
||||||
|
CONFIG_FS_FAT=y
|
||||||
|
CONFIG_FS_PROCFS=y
|
||||||
|
CONFIG_GRAPHICS_PDCURSES=y
|
||||||
|
CONFIG_LPC54_EMC_DYNAMIC_CS0_OFFSET=0x00080000
|
||||||
|
CONFIG_LPC54_EMC_DYNAMIC_CS0_SIZE=0x00f80000
|
||||||
|
CONFIG_LPC54_EMC_DYNAMIC_CS0=y
|
||||||
|
CONFIG_LPC54_EMC=y
|
||||||
|
CONFIG_LPC54_LCD_BPP24_RGB565=y
|
||||||
|
CONFIG_LPC54_LCD_HBACKPORCH=43
|
||||||
|
CONFIG_LPC54_LCD_HFRONTPORCH=8
|
||||||
|
CONFIG_LPC54_LCD_VBACKPORCH=12
|
||||||
|
CONFIG_LPC54_LCD_VFRONTPORCH=4
|
||||||
|
CONFIG_LPC54_LCD_VPULSE=10
|
||||||
|
CONFIG_LPC54_LCD_VRAMBASE=0xa0000000
|
||||||
|
CONFIG_LPC54_LCD=y
|
||||||
|
CONFIG_LPC54_USART0=y
|
||||||
|
CONFIG_MAX_TASKS=16
|
||||||
|
CONFIG_MAX_WDOGPARMS=2
|
||||||
|
CONFIG_MM_REGIONS=2
|
||||||
|
CONFIG_NFILE_DESCRIPTORS=8
|
||||||
|
CONFIG_NFILE_STREAMS=8
|
||||||
|
CONFIG_NSH_ARCHINIT=y
|
||||||
|
CONFIG_NSH_BUILTIN_APPS=y
|
||||||
|
CONFIG_NSH_DISABLE_IFUPDOWN=y
|
||||||
|
CONFIG_NSH_FILEIOSIZE=512
|
||||||
|
CONFIG_NSH_LINELEN=64
|
||||||
|
CONFIG_NSH_READLINE=y
|
||||||
|
CONFIG_PDCURSES_COLORFMT_RGB888=y
|
||||||
|
CONFIG_PDCURSES_FONT_6X9=y
|
||||||
|
CONFIG_PREALLOC_MQ_MSGS=4
|
||||||
|
CONFIG_PREALLOC_TIMERS=4
|
||||||
|
CONFIG_PREALLOC_WDOGS=4
|
||||||
|
CONFIG_RAM_SIZE=32768
|
||||||
|
CONFIG_RAM_START=0x10000000
|
||||||
|
CONFIG_RAW_BINARY=y
|
||||||
|
CONFIG_RR_INTERVAL=200
|
||||||
|
CONFIG_SCHED_WAITPID=y
|
||||||
|
CONFIG_SDCLONE_DISABLE=y
|
||||||
|
CONFIG_START_DAY=13
|
||||||
|
CONFIG_START_MONTH=12
|
||||||
|
CONFIG_SYMTAB_ORDEREDBYNAME=y
|
||||||
|
CONFIG_SYSTEM_RAMTEST=y
|
||||||
|
CONFIG_TASK_NAME_SIZE=0
|
||||||
|
CONFIG_USART0_SERIAL_CONSOLE=y
|
||||||
|
CONFIG_USER_ENTRYPOINT="nsh_main"
|
||||||
|
CONFIG_VIDEO_FB=y
|
||||||
|
CONFIG_WDOG_INTRESERVE=0
|
@ -237,7 +237,28 @@
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
/* Button definitions *******************************************************/
|
/* Button definitions *******************************************************/
|
||||||
/* To be provided */
|
/* The LPCXpresso has four switches:
|
||||||
|
*
|
||||||
|
* SW2 ISP2 P0.6
|
||||||
|
* SW3 ISP1 P0.5
|
||||||
|
* SW4 ISP0 P0.4
|
||||||
|
* SW5 User Button P1.1
|
||||||
|
*
|
||||||
|
* In all cased, the signal is low when the button is pressed.
|
||||||
|
*
|
||||||
|
* SW2, SW3, SW4 can be used to force the LPC546xx in to ISP boot modes.
|
||||||
|
* After boot these buttons could be used as user buttons. However, they are
|
||||||
|
* not available when the on-board SRDRAM is used because P0.4, P0.5, and
|
||||||
|
* P0.6 are also used as EMC_D2, EMC_D3, and EMC_D4, respectively.
|
||||||
|
*
|
||||||
|
* So SW5 is really the only button that that is generally available for
|
||||||
|
* software usage.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define BOARD_BUTTON_USER 0
|
||||||
|
#define BOARD_NUM_BUTTONS 1
|
||||||
|
|
||||||
|
#define BOARD_BUTTON_USER_BIT (1 << BOARD_BUTTON_USER)
|
||||||
|
|
||||||
/* Pin Disambiguation *******************************************************/
|
/* Pin Disambiguation *******************************************************/
|
||||||
/* Flexcomm0/USART0
|
/* Flexcomm0/USART0
|
||||||
@ -249,10 +270,17 @@
|
|||||||
* BRIDGE_UART_TXD <- P0_30-ISP_FC0_TXD <- P0.30 GPIO_FC0_TXD_SCL_MISO_2
|
* BRIDGE_UART_TXD <- P0_30-ISP_FC0_TXD <- P0.30 GPIO_FC0_TXD_SCL_MISO_2
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifdef CONFIG_LPC54_USART0
|
#define GPIO_USART0_RXD (GPIO_FC0_RXD_SDA_MOSI_2 | GPIO_FILTER_OFF)
|
||||||
# define GPIO_USART0_RXD (GPIO_FC0_RXD_SDA_MOSI_2 | GPIO_FILTER_OFF)
|
#define GPIO_USART0_TXD (GPIO_FC0_TXD_SCL_MISO_2 | GPIO_FILTER_OFF)
|
||||||
# define GPIO_USART0_TXD (GPIO_FC0_TXD_SCL_MISO_2 | GPIO_FILTER_OFF)
|
|
||||||
#endif
|
/* LCD
|
||||||
|
*
|
||||||
|
* There are no alternatives for LCD pins except for the VD0-VD3 pins.
|
||||||
|
* VD0-VD2 are not used in this hardware configuration. VD3 is on
|
||||||
|
* P2.21.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define GPIO_LCD_VD3 GPIO_LCD_VD3_1
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Types
|
* Public Types
|
||||||
|
@ -43,6 +43,8 @@
|
|||||||
#include <sys/mount.h>
|
#include <sys/mount.h>
|
||||||
#include <syslog.h>
|
#include <syslog.h>
|
||||||
|
|
||||||
|
#include <nuttx/video/fb.h>
|
||||||
|
|
||||||
#include "lpcxpresso-lpc54628.h"
|
#include "lpcxpresso-lpc54628.h"
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@ -77,6 +79,16 @@ int lpc54_bringup(void)
|
|||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_VIDEO_FB
|
||||||
|
/* Initialize and register the framebuffer driver */
|
||||||
|
|
||||||
|
ret = fb_register(0, 0);
|
||||||
|
if (ret < 0)
|
||||||
|
{
|
||||||
|
syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
UNUSED(ret);
|
UNUSED(ret);
|
||||||
return OK;
|
return OK;
|
||||||
}
|
}
|
||||||
|
@ -67,7 +67,23 @@
|
|||||||
GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PUSHPULL | GPIO_PULLUP)
|
GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PUSHPULL | GPIO_PULLUP)
|
||||||
|
|
||||||
/* Button definitions *******************************************************/
|
/* Button definitions *******************************************************/
|
||||||
/* to be provided */
|
/* The LPCXpresso has four switches:
|
||||||
|
*
|
||||||
|
* SW2 ISP2 P0.6
|
||||||
|
* SW3 ISP1 P0.5
|
||||||
|
* SW4 ISP0 P0.4
|
||||||
|
* SW5 User Button P1.1
|
||||||
|
*
|
||||||
|
* In all cased, the signal is low when the button is pressed.
|
||||||
|
*
|
||||||
|
* SW2, SW3, SW4 can be used to force the LPC546xx in to ISP boot modes.
|
||||||
|
* After boot these buttons could be used as user buttons. However, they are
|
||||||
|
* not available when the on-board SRDRAM is used because P0.4, P0.5, and
|
||||||
|
* P0.6 are also used as EMC_D2, EMC_D3, and EMC_D4, respectively.
|
||||||
|
*
|
||||||
|
* So SW5 is really the only button that that is generally available for
|
||||||
|
* software usage.
|
||||||
|
*/
|
||||||
|
|
||||||
/* LCD/TSC definitions ******************************************************/
|
/* LCD/TSC definitions ******************************************************/
|
||||||
/* The backlight is controlled by P3.31 and is intended to connect via PWM
|
/* The backlight is controlled by P3.31 and is intended to connect via PWM
|
||||||
|
@ -375,7 +375,7 @@
|
|||||||
#define GPIO_LCD_VD6 GPIO_LCD_VD6_2
|
#define GPIO_LCD_VD6 GPIO_LCD_VD6_2
|
||||||
#define GPIO_LCD_VD7 GPIO_LCD_VD7_2
|
#define GPIO_LCD_VD7 GPIO_LCD_VD7_2
|
||||||
|
|
||||||
/* LED G:
|
/* LCD G:
|
||||||
*
|
*
|
||||||
* VD8 --- Connected to P0[6]
|
* VD8 --- Connected to P0[6]
|
||||||
* VD9 --- Connected to P0[7]
|
* VD9 --- Connected to P0[7]
|
||||||
|
Loading…
Reference in New Issue
Block a user