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arch/arm/src/imxrt,stm32,stm32f0,stm32f7,stm32l4: Fix scope of naming. CONFIG_PM_SERIAL_ACTIVITY->CONFIG_STM32_PM_SERIAL_ACTIVITY, for example.

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This commit is contained in:
Gregory Nutt 2018-06-28 16:18:15 -06:00
parent ceaafc2019
commit f24f523e4e
12 changed files with 133 additions and 115 deletions
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11
arch/arm/src/imxrt/Kconfig
View File

@ -462,6 +462,17 @@ config IMXRT_EDMA_EDBG
endmenu # eDMA Global Configuration
if PM
config IMXRT_PM_SERIAL_ACTIVITY
int "PM serial activity"
default 10
---help---
PM activity reported to power management logic on every serial
interrupt.
endif
menu "RTC Configuration"
depends on IMXRT_SNVS_HPRTC

8
arch/arm/src/imxrt/imxrt_serial.c
View File

@ -301,8 +301,8 @@
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_PM_SERIAL_ACTIVITY)
# define CONFIG_PM_SERIAL_ACTIVITY 10
#if defined(CONFIG_PM) && !defined(CONFIG_IMXRT_PM_SERIAL_ACTIVITY)
# define CONFIG_IMXRT_PM_SERIAL_ACTIVITY 10
#endif
#if defined(CONFIG_PM)
@ -861,10 +861,10 @@ static int imxrt_interrupt(int irq, void *context, FAR void *arg)
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct imxrt_uart_s *)dev->priv;
#if defined(CONFIG_PM) && CONFIG_PM_SERIAL_ACTIVITY > 0
#if defined(CONFIG_PM) && CONFIG_IMXRT_PM_SERIAL_ACTIVITY > 0
/* Report serial activity to the power management logic */
pm_activity(PM_IDLE_DOMAIN, CONFIG_PM_SERIAL_ACTIVITY);
pm_activity(PM_IDLE_DOMAIN, CONFIG_IMXRT_PM_SERIAL_ACTIVITY);
#endif
/* Loop until there are no characters to be transferred or,

58
arch/arm/src/stm32/Kconfig
View File

@ -5022,21 +5022,21 @@ choice
config STM32_TIM1_ADC1
bool "TIM1 ADC channel 1"
depends on STM32_ADC1
select HAVE_ADC1_TIMER
select STM32_HAVE_ADC1_TIMER
---help---
Reserve TIM1 to trigger ADC1
config STM32_TIM1_ADC2
bool "TIM1 ADC channel 2"
depends on STM32_ADC2
select HAVE_ADC2_TIMER
select STM32_HAVE_ADC2_TIMER
---help---
Reserve TIM1 to trigger ADC2
config STM32_TIM1_ADC3
bool "TIM1 ADC channel 3"
depends on STM32_ADC3
select HAVE_ADC3_TIMER
select STM32_HAVE_ADC3_TIMER
---help---
Reserve TIM1 to trigger ADC3
@ -5064,21 +5064,21 @@ choice
config STM32_TIM2_ADC1
bool "TIM2 ADC channel 1"
depends on STM32_ADC1
select HAVE_ADC1_TIMER
select STM32_HAVE_ADC1_TIMER
---help---
Reserve TIM2 to trigger ADC1
config STM32_TIM2_ADC2
bool "TIM2 ADC channel 2"
depends on STM32_ADC2
select HAVE_ADC2_TIMER
select STM32_HAVE_ADC2_TIMER
---help---
Reserve TIM2 to trigger ADC2
config STM32_TIM2_ADC3
bool "TIM2 ADC channel 3"
depends on STM32_ADC3
select HAVE_ADC3_TIMER
select STM32_HAVE_ADC3_TIMER
---help---
Reserve TIM2 to trigger ADC3
@ -5106,21 +5106,21 @@ choice
config STM32_TIM3_ADC1
bool "TIM3 ADC channel 1"
depends on STM32_ADC1
select HAVE_ADC1_TIMER
select STM32_HAVE_ADC1_TIMER
---help---
Reserve TIM3 to trigger ADC1
config STM32_TIM3_ADC2
bool "TIM3 ADC channel 2"
depends on STM32_ADC2
select HAVE_ADC2_TIMER
select STM32_HAVE_ADC2_TIMER
---help---
Reserve TIM3 to trigger ADC2
config STM32_TIM3_ADC3
bool "TIM3 ADC channel 3"
depends on STM32_ADC3
select HAVE_ADC3_TIMER
select STM32_HAVE_ADC3_TIMER
---help---
Reserve TIM3 to trigger ADC3
@ -5148,21 +5148,21 @@ choice
config STM32_TIM4_ADC1
bool "TIM4 ADC channel 1"
depends on STM32_ADC1
select HAVE_ADC1_TIMER
select STM32_HAVE_ADC1_TIMER
---help---
Reserve TIM4 to trigger ADC1
config STM32_TIM4_ADC2
bool "TIM4 ADC channel 2"
depends on STM32_ADC2
select HAVE_ADC2_TIMER
select STM32_HAVE_ADC2_TIMER
---help---
Reserve TIM4 to trigger ADC2
config STM32_TIM4_ADC3
bool "TIM4 ADC channel 3"
depends on STM32_ADC3
select HAVE_ADC3_TIMER
select STM32_HAVE_ADC3_TIMER
---help---
Reserve TIM4 to trigger ADC3
@ -5190,21 +5190,21 @@ choice
config STM32_TIM5_ADC1
bool "TIM5 ADC channel 1"
depends on STM32_ADC1
select HAVE_ADC1_TIMER
select STM32_HAVE_ADC1_TIMER
---help---
Reserve TIM5 to trigger ADC1
config STM32_TIM5_ADC2
bool "TIM5 ADC channel 2"
depends on STM32_ADC2
select HAVE_ADC2_TIMER
select STM32_HAVE_ADC2_TIMER
---help---
Reserve TIM5 to trigger ADC2
config STM32_TIM5_ADC3
bool "TIM5 ADC channel 3"
depends on STM32_ADC3
select HAVE_ADC3_TIMER
select STM32_HAVE_ADC3_TIMER
---help---
Reserve TIM5 to trigger ADC3
@ -5232,39 +5232,39 @@ choice
config STM32_TIM8_ADC1
bool "TIM8 ADC channel 1"
depends on STM32_ADC1
select HAVE_ADC1_TIMER
select STM32_HAVE_ADC1_TIMER
---help---
Reserve TIM8 to trigger ADC1
config STM32_TIM8_ADC2
bool "TIM8 ADC channel 2"
depends on STM32_ADC2
select HAVE_ADC2_TIMER
select STM32_HAVE_ADC2_TIMER
---help---
Reserve TIM8 to trigger ADC2
config STM32_TIM8_ADC3
bool "TIM8 ADC channel 3"
depends on STM32_ADC3
select HAVE_ADC3_TIMER
select STM32_HAVE_ADC3_TIMER
---help---
Reserve TIM8 to trigger ADC3
endchoice
config HAVE_ADC1_TIMER
config STM32_HAVE_ADC1_TIMER
bool
config HAVE_ADC2_TIMER
config STM32_HAVE_ADC2_TIMER
bool
config HAVE_ADC3_TIMER
config STM32_HAVE_ADC3_TIMER
bool
config STM32_ADC1_SAMPLE_FREQUENCY
int "ADC1 Sampling Frequency"
default 100
depends on HAVE_ADC1_TIMER
depends on STM32_HAVE_ADC1_TIMER
---help---
ADC1 sampling frequency. Default: 100Hz
@ -5272,14 +5272,14 @@ config STM32_ADC1_TIMTRIG
int "ADC1 Timer Trigger"
default 0
range 0 4
depends on HAVE_ADC1_TIMER
depends on STM32_HAVE_ADC1_TIMER
---help---
Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
config STM32_ADC2_SAMPLE_FREQUENCY
int "ADC2 Sampling Frequency"
default 100
depends on HAVE_ADC2_TIMER
depends on STM32_HAVE_ADC2_TIMER
---help---
ADC2 sampling frequency. Default: 100Hz
@ -5287,14 +5287,14 @@ config STM32_ADC2_TIMTRIG
int "ADC2 Timer Trigger"
default 0
range 0 4
depends on HAVE_ADC2_TIMER
depends on STM32_HAVE_ADC2_TIMER
---help---
Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
config STM32_ADC3_SAMPLE_FREQUENCY
int "ADC3 Sampling Frequency"
default 100
depends on HAVE_ADC3_TIMER
depends on STM32_HAVE_ADC3_TIMER
---help---
ADC3 sampling frequency. Default: 100Hz
@ -5302,7 +5302,7 @@ config STM32_ADC3_TIMTRIG
int "ADC3 Timer Trigger"
default 0
range 0 4
depends on HAVE_ADC3_TIMER
depends on STM32_HAVE_ADC3_TIMER
---help---
Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
@ -7446,12 +7446,14 @@ config STM32_HCIUART_LOWER_WATERMARK
endmenu # HCI UART Driver Configuration
if PM
config PM_SERIAL_ACTIVITY
config STM32_PM_SERIAL_ACTIVITY
int "PM serial activity"
default 10
---help---
PM activity reported to power management logic on every serial
interrupt.
endif
endmenu # U[S]ART Configuration

8
arch/arm/src/stm32/stm32_hciuart.c
View File

@ -224,8 +224,8 @@
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_PM_SERIAL_ACTIVITY)
# define CONFIG_PM_SERIAL_ACTIVITY 10
#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10
#endif
#if defined(CONFIG_PM)
@ -1712,8 +1712,8 @@ static int hciuart_interrupt(int irq, void *context, void *arg)
/* Report serial activity to the power management logic */
#if defined(CONFIG_PM) && CONFIG_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_PM_SERIAL_ACTIVITY);
#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY);
#endif
/* Loop until there are no characters to be transferred or,

8
arch/arm/src/stm32/stm32_serial.c
View File

@ -243,8 +243,8 @@
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_PM_SERIAL_ACTIVITY)
# define CONFIG_PM_SERIAL_ACTIVITY 10
#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10
#endif
#if defined(CONFIG_PM)
# define PM_IDLE_DOMAIN 0 /* Revisit */
@ -1804,8 +1804,8 @@ static int up_interrupt(int irq, void *context, void *arg)
/* Report serial activity to the power management logic */
#if defined(CONFIG_PM) && CONFIG_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_PM_SERIAL_ACTIVITY);
#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY);
#endif
/* Loop until there are no characters to be transferred or,

4
arch/arm/src/stm32f0/Kconfig
View File

@ -1471,12 +1471,14 @@ config USART8_RS485_DIR_POLARITY
endif # STM32F0_USART8_SERIALDRIVER
if PM
config PM_SERIAL_ACTIVITY
config STM32F0_PM_SERIAL_ACTIVITY
int "PM serial activity"
default 10
---help---
PM activity reported to power management logic on every serial
interrupt.
endif
endmenu

8
arch/arm/src/stm32f0/stm32f0_serial.c
View File

@ -174,8 +174,8 @@
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_PM_SERIAL_ACTIVITY)
# define CONFIG_PM_SERIAL_ACTIVITY 10
#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32F0_PM_SERIAL_ACTIVITY 10
#endif
#if defined(CONFIG_PM)
# define PM_IDLE_DOMAIN 0 /* Revisit */
@ -1461,8 +1461,8 @@ static int up_interrupt(int irq, FAR void *context, FAR void *arg)
/* Report serial activity to the power management logic */
#if defined(CONFIG_PM) && CONFIG_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_PM_SERIAL_ACTIVITY);
#if defined(CONFIG_PM) && CONFIG_STM32F0_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0_PM_SERIAL_ACTIVITY);
#endif
/* Loop until there are no characters to be transferred or,

58
arch/arm/src/stm32f7/Kconfig
View File

@ -1886,12 +1886,14 @@ config STM32F7_SERIALBRK_BSDCOMPAT
the break. This makes it is difficult to sent a long break.
if PM
config PM_SERIAL_ACTIVITY
config STM32F7_PM_SERIAL_ACTIVITY
int "PM serial activity"
default 10
---help---
PM activity reported to power management logic on every serial
interrupt.
endif
endmenu # U[S]ART Configuration
@ -3787,21 +3789,21 @@ choice
config STM32F7_TIM1_ADC1
bool "TIM1 ADC channel 1"
depends on STM32F7_ADC1
select HAVE_ADC1_TIMER
select STM32F7_HAVE_ADC1_TIMER
---help---
Reserve TIM1 to trigger ADC1
config STM32F7_TIM1_ADC2
bool "TIM1 ADC channel 2"
depends on STM32F7_ADC2
select HAVE_ADC2_TIMER
select STM32F7_HAVE_ADC2_TIMER
---help---
Reserve TIM1 to trigger ADC2
config STM32F7_TIM1_ADC3
bool "TIM1 ADC channel 3"
depends on STM32F7_ADC3
select HAVE_ADC3_TIMER
select STM32F7_HAVE_ADC3_TIMER
---help---
Reserve TIM1 to trigger ADC3
@ -3829,21 +3831,21 @@ choice
config STM32F7_TIM2_ADC1
bool "TIM2 ADC channel 1"
depends on STM32F7_ADC1
select HAVE_ADC1_TIMER
select STM32F7_HAVE_ADC1_TIMER
---help---
Reserve TIM2 to trigger ADC1
config STM32F7_TIM2_ADC2
bool "TIM2 ADC channel 2"
depends on STM32F7_ADC2
select HAVE_ADC2_TIMER
select STM32F7_HAVE_ADC2_TIMER
---help---
Reserve TIM2 to trigger ADC2
config STM32F7_TIM2_ADC3
bool "TIM2 ADC channel 3"
depends on STM32F7_ADC3
select HAVE_ADC3_TIMER
select STM32F7_HAVE_ADC3_TIMER
---help---
Reserve TIM2 to trigger ADC3
@ -3871,21 +3873,21 @@ choice
config STM32F7_TIM3_ADC1
bool "TIM3 ADC channel 1"
depends on STM32F7_ADC1
select HAVE_ADC1_TIMER
select STM32F7_HAVE_ADC1_TIMER
---help---
Reserve TIM3 to trigger ADC1
config STM32F7_TIM3_ADC2
bool "TIM3 ADC channel 2"
depends on STM32F7_ADC2
select HAVE_ADC2_TIMER
select STM32F7_HAVE_ADC2_TIMER
---help---
Reserve TIM3 to trigger ADC2
config STM32F7_TIM3_ADC3
bool "TIM3 ADC channel 3"
depends on STM32F7_ADC3
select HAVE_ADC3_TIMER
select STM32F7_HAVE_ADC3_TIMER
---help---
Reserve TIM3 to trigger ADC3
@ -3913,21 +3915,21 @@ choice
config STM32F7_TIM4_ADC1
bool "TIM4 ADC channel 1"
depends on STM32F7_ADC1
select HAVE_ADC1_TIMER
select STM32F7_HAVE_ADC1_TIMER
---help---
Reserve TIM4 to trigger ADC1
config STM32F7_TIM4_ADC2
bool "TIM4 ADC channel 2"
depends on STM32F7_ADC2
select HAVE_ADC2_TIMER
select STM32F7_HAVE_ADC2_TIMER
---help---
Reserve TIM4 to trigger ADC2
config STM32F7_TIM4_ADC3
bool "TIM4 ADC channel 3"
depends on STM32F7_ADC3
select HAVE_ADC3_TIMER
select STM32F7_HAVE_ADC3_TIMER
---help---
Reserve TIM4 to trigger ADC3
@ -3955,21 +3957,21 @@ choice
config STM32F7_TIM5_ADC1
bool "TIM5 ADC channel 1"
depends on STM32F7_ADC1
select HAVE_ADC1_TIMER
select STM32F7_HAVE_ADC1_TIMER
---help---
Reserve TIM5 to trigger ADC1
config STM32F7_TIM5_ADC2
bool "TIM5 ADC channel 2"
depends on STM32F7_ADC2
select HAVE_ADC2_TIMER
select STM32F7_HAVE_ADC2_TIMER
---help---
Reserve TIM5 to trigger ADC2
config STM32F7_TIM5_ADC3
bool "TIM5 ADC channel 3"
depends on STM32F7_ADC3
select HAVE_ADC3_TIMER
select STM32F7_HAVE_ADC3_TIMER
---help---
Reserve TIM5 to trigger ADC3
@ -3997,39 +3999,39 @@ choice
config STM32F7_TIM8_ADC1
bool "TIM8 ADC channel 1"
depends on STM32F7_ADC1
select HAVE_ADC1_TIMER
select STM32F7_HAVE_ADC1_TIMER
---help---
Reserve TIM8 to trigger ADC1
config STM32F7_TIM8_ADC2
bool "TIM8 ADC channel 2"
depends on STM32F7_ADC2
select HAVE_ADC2_TIMER
select STM32F7_HAVE_ADC2_TIMER
---help---
Reserve TIM8 to trigger ADC2
config STM32F7_TIM8_ADC3
bool "TIM8 ADC channel 3"
depends on STM32F7_ADC3
select HAVE_ADC3_TIMER
select STM32F7_HAVE_ADC3_TIMER
---help---
Reserve TIM8 to trigger ADC3
endchoice
config HAVE_ADC1_TIMER
config STM32F7_HAVE_ADC1_TIMER
bool
config HAVE_ADC2_TIMER
config STM32F7_HAVE_ADC2_TIMER
bool
config HAVE_ADC3_TIMER
config STM32F7_HAVE_ADC3_TIMER
bool
config STM32F7_ADC1_SAMPLE_FREQUENCY
int "ADC1 Sampling Frequency"
default 100
depends on HAVE_ADC1_TIMER
depends on STM32F7_HAVE_ADC1_TIMER
---help---
ADC1 sampling frequency. Default: 100Hz
@ -4037,14 +4039,14 @@ config STM32F7_ADC1_TIMTRIG
int "ADC1 Timer Trigger"
default 0
range 0 4
depends on HAVE_ADC1_TIMER
depends on STM32F7_HAVE_ADC1_TIMER
---help---
Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
config STM32F7_ADC2_SAMPLE_FREQUENCY
int "ADC2 Sampling Frequency"
default 100
depends on HAVE_ADC2_TIMER
depends on STM32F7_HAVE_ADC2_TIMER
---help---
ADC2 sampling frequency. Default: 100Hz
@ -4052,14 +4054,14 @@ config STM32F7_ADC2_TIMTRIG
int "ADC2 Timer Trigger"
default 0
range 0 4
depends on HAVE_ADC2_TIMER
depends on STM32F7_HAVE_ADC2_TIMER
---help---
Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
config STM32F7_ADC3_SAMPLE_FREQUENCY
int "ADC3 Sampling Frequency"
default 100
depends on HAVE_ADC3_TIMER
depends on STM32F7_HAVE_ADC3_TIMER
---help---
ADC3 sampling frequency. Default: 100Hz
@ -4067,7 +4069,7 @@ config STM32F7_ADC3_TIMTRIG
int "ADC3 Timer Trigger"
default 0
range 0 4
depends on HAVE_ADC3_TIMER
depends on STM32F7_HAVE_ADC3_TIMER
---help---
Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO

8
arch/arm/src/stm32f7/stm32_serial.c
View File

@ -209,8 +209,8 @@
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_PM_SERIAL_ACTIVITY)
# define CONFIG_PM_SERIAL_ACTIVITY 10
#if defined(CONFIG_PM) && !defined(CONFIG_STM32F7_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32F7_PM_SERIAL_ACTIVITY 10
#endif
#if defined(CONFIG_PM)
# define PM_IDLE_DOMAIN 0 /* Revisit */
@ -1791,8 +1791,8 @@ static int up_interrupt(int irq, void *context, FAR void *arg)
/* Report serial activity to the power management logic */
#if defined(CONFIG_PM) && CONFIG_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_PM_SERIAL_ACTIVITY);
#if defined(CONFIG_PM) && CONFIG_STM32F7_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F7_PM_SERIAL_ACTIVITY);
#endif
/* Loop until there are no characters to be transferred or,

2
arch/arm/src/stm32h7/Kconfig
View File

@ -573,7 +573,7 @@ config STM32H7_SERIALBRK_BSDCOMPAT
if PM
config PM_SERIAL_ACTIVITY
config STM32H7_PM_SERIAL_ACTIVITY
int "PM serial activity"
default 10
---help---

67
arch/arm/src/stm32l4/Kconfig
View File

@ -2693,21 +2693,21 @@ choice
config STM32L4_TIM1_ADC1
bool "TIM1 ADC channel 1"
depends on STM32L4_ADC1
select HAVE_ADC1_TIMER
select STM32L4_HAVE_ADC1_TIMER
---help---
Reserve TIM1 to trigger ADC1
config STM32L4_TIM1_ADC2
bool "TIM1 ADC channel 2"
depends on STM32L4_ADC2
select HAVE_ADC2_TIMER
select STM32L4_HAVE_ADC2_TIMER
---help---
Reserve TIM1 to trigger ADC2
config STM32L4_TIM1_ADC3
bool "TIM1 ADC channel 3"
depends on STM32L4_ADC3
select HAVE_ADC3_TIMER
select STM32L4_HAVE_ADC3_TIMER
---help---
Reserve TIM1 to trigger ADC3
@ -2735,21 +2735,21 @@ choice
config STM32L4_TIM2_ADC1
bool "TIM2 ADC channel 1"
depends on STM32L4_ADC1
select HAVE_ADC1_TIMER
select STM32L4_HAVE_ADC1_TIMER
---help---
Reserve TIM2 to trigger ADC1
config STM32L4_TIM2_ADC2
bool "TIM2 ADC channel 2"
depends on STM32L4_ADC2
select HAVE_ADC2_TIMER
select STM32L4_HAVE_ADC2_TIMER
---help---
Reserve TIM2 to trigger ADC2
config STM32L4_TIM2_ADC3
bool "TIM2 ADC channel 3"
depends on STM32L4_ADC3
select HAVE_ADC3_TIMER
select STM32L4_HAVE_ADC3_TIMER
---help---
Reserve TIM2 to trigger ADC3
@ -2777,21 +2777,21 @@ choice
config STM32L4_TIM3_ADC1
bool "TIM3 ADC channel 1"
depends on STM32L4_ADC1
select HAVE_ADC1_TIMER
select STM32L4_HAVE_ADC1_TIMER
---help---
Reserve TIM3 to trigger ADC1
config STM32L4_TIM3_ADC2
bool "TIM3 ADC channel 2"
depends on STM32L4_ADC2
select HAVE_ADC2_TIMER
select STM32L4_HAVE_ADC2_TIMER
---help---
Reserve TIM3 to trigger ADC2
config STM32L4_TIM3_ADC3
bool "TIM3 ADC channel 3"
depends on STM32L4_ADC3
select HAVE_ADC3_TIMER
select STM32L4_HAVE_ADC3_TIMER
---help---
Reserve TIM3 to trigger ADC3
@ -2819,21 +2819,21 @@ choice
config STM32L4_TIM4_ADC1
bool "TIM4 ADC channel 1"
depends on STM32L4_ADC1
select HAVE_ADC1_TIMER
select STM32L4_HAVE_ADC1_TIMER
---help---
Reserve TIM4 to trigger ADC1
config STM32L4_TIM4_ADC2
bool "TIM4 ADC channel 2"
depends on STM32L4_ADC2
select HAVE_ADC2_TIMER
select STM32L4_HAVE_ADC2_TIMER
---help---
Reserve TIM4 to trigger ADC2
config STM32L4_TIM4_ADC3
bool "TIM4 ADC channel 3"
depends on STM32L4_ADC3
select HAVE_ADC3_TIMER
select STM32L4_HAVE_ADC3_TIMER
---help---
Reserve TIM4 to trigger ADC3
@ -2861,21 +2861,21 @@ choice
config STM32L4_TIM6_ADC1
bool "TIM6 ADC channel 1"
depends on STM32L4_ADC1
select HAVE_ADC1_TIMER
select STM32L4_HAVE_ADC1_TIMER
---help---
Reserve TIM6 to trigger ADC1
config STM32L4_TIM6_ADC2
bool "TIM6 ADC channel 2"
depends on STM32L4_ADC2
select HAVE_ADC2_TIMER
select STM32L4_HAVE_ADC2_TIMER
---help---
Reserve TIM6 to trigger ADC2
config STM32L4_TIM6_ADC3
bool "TIM6 ADC channel 3"
depends on STM32L4_ADC3
select HAVE_ADC3_TIMER
select STM32L4_HAVE_ADC3_TIMER
---help---
Reserve TIM6 to trigger ADC3
@ -2903,21 +2903,21 @@ choice
config STM32L4_TIM8_ADC1
bool "TIM8 ADC channel 1"
depends on STM32L4_ADC1
select HAVE_ADC1_TIMER
select STM32L4_HAVE_ADC1_TIMER
---help---
Reserve TIM8 to trigger ADC1
config STM32L4_TIM8_ADC2
bool "TIM8 ADC channel 2"
depends on STM32L4_ADC2
select HAVE_ADC2_TIMER
select STM32L4_HAVE_ADC2_TIMER
---help---
Reserve TIM8 to trigger ADC2
config STM32L4_TIM8_ADC3
bool "TIM8 ADC channel 3"
depends on STM32L4_ADC3
select HAVE_ADC3_TIMER
select STM32L4_HAVE_ADC3_TIMER
---help---
Reserve TIM8 to trigger ADC3
@ -2945,39 +2945,39 @@ choice
config STM32L4_TIM15_ADC1
bool "TIM15 ADC channel 1"
depends on STM32L4_ADC1
select HAVE_ADC1_TIMER
select STM32L4_HAVE_ADC1_TIMER
---help---
Reserve TIM15 to trigger ADC1
config STM32L4_TIM15_ADC2
bool "TIM15 ADC channel 2"
depends on STM32L4_ADC2
select HAVE_ADC2_TIMER
select STM32L4_HAVE_ADC2_TIMER
---help---
Reserve TIM15 to trigger ADC2
config STM32L4_TIM15_ADC3
bool "TIM15 ADC channel 3"
depends on STM32L4_ADC3
select HAVE_ADC3_TIMER
select STM32L4_HAVE_ADC3_TIMER
---help---
Reserve TIM15 to trigger ADC3
endchoice
config HAVE_ADC1_TIMER
config STM32L4_HAVE_ADC1_TIMER
bool
config HAVE_ADC2_TIMER
config STM32L4_HAVE_ADC2_TIMER
bool
config HAVE_ADC3_TIMER
as
config STM32L4_HAVE_ADC3_TIMER
bool
config STM32L4_ADC1_SAMPLE_FREQUENCY
int "ADC1 Sampling Frequency"
default 100
depends on HAVE_ADC1_TIMER
depends on STM32L4_HAVE_ADC1_TIMER
---help---
ADC1 sampling frequency. Default: 100Hz
@ -2985,14 +2985,14 @@ config STM32L4_ADC1_TIMTRIG
int "ADC1 Timer Trigger"
default 0
range 0 4
depends on HAVE_ADC1_TIMER
depends on STM32L4_HAVE_ADC1_TIMER
---help---
Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
config STM32L4_ADC2_SAMPLE_FREQUENCY
int "ADC2 Sampling Frequency"
default 100
depends on HAVE_ADC2_TIMER
depends on STM32L4_HAVE_ADC2_TIMER
---help---
ADC2 sampling frequency. Default: 100Hz
@ -3000,14 +3000,14 @@ config STM32L4_ADC2_TIMTRIG
int "ADC2 Timer Trigger"
default 0
range 0 4
depends on HAVE_ADC2_TIMER
depends on STM32L4_HAVE_ADC2_TIMER
---help---
Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
config STM32L4_ADC3_SAMPLE_FREQUENCY
int "ADC3 Sampling Frequency"
default 100
depends on HAVE_ADC3_TIMER
depends on STM32L4_HAVE_ADC3_TIMER
---help---
ADC3 sampling frequency. Default: 100Hz
@ -3015,7 +3015,7 @@ config STM32L4_ADC3_TIMTRIG
int "ADC3 Timer Trigger"
default 0
range 0 4
depends on HAVE_ADC3_TIMER
depends on STM32L4_HAVE_ADC3_TIMER
---help---
Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
@ -3797,14 +3797,15 @@ config STM32L4_USART_SINGLEWIRE
TIOCSSINGLEWIRE ioctl in the STM32 serial driver.
if PM
config PM_SERIAL_ACTIVITY
config STM32L4_PM_SERIAL_ACTIVITY
int "PM serial activity"
default 10
---help---
PM activity reported to power management logic on every serial
interrupt.
endif
endif
endif # STM32L4_SERIALDRIVER
endmenu # U[S]ART Configuration

8
arch/arm/src/stm32l4/stm32l4_serial.c
View File

@ -176,8 +176,8 @@
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_PM_SERIAL_ACTIVITY)
# define CONFIG_PM_SERIAL_ACTIVITY 10
#if defined(CONFIG_PM) && !defined(CONFIG_STM32L4_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32L4_PM_SERIAL_ACTIVITY 10
#endif
#if defined(CONFIG_PM)
# define PM_IDLE_DOMAIN 0 /* Revisit */
@ -1654,8 +1654,8 @@ static int up_interrupt(int irq, FAR void *context, FAR void *arg)
/* Report serial activity to the power management logic */
#if defined(CONFIG_PM) && CONFIG_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_PM_SERIAL_ACTIVITY);
#if defined(CONFIG_PM) && CONFIG_STM32L4_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32L4_PM_SERIAL_ACTIVITY);
#endif
/* Loop until there are no characters to be transferred or,