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SAMA5 EMAC: Incremental progress. Still not code complete

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This commit is contained in:
Gregory Nutt 2013-09-16 11:36:12 -06:00
parent 47d4b41bad
commit f267cea5b6
5 changed files with 780 additions and 953 deletions
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197
arch/arm/src/sama5/Kconfig
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@ -14,18 +14,23 @@ choice
config ARCH_CHIP_ATSAMA5D31
bool "Atmel ATSAMA5D31"
select ARCH_CHIP_SAMA5D3
select SAMA5_HAVE_EMAC
config ARCH_CHIP_ATSAMA5D33
bool "Atmel ATSAMA5D33"
select ARCH_CHIP_SAMA5D3
select SAMA5_HAVE_GMAC
config ARCH_CHIP_ATSAMA5D34
bool "Atmel ATSAMA5D34"
select ARCH_CHIP_SAMA5D3
select SAMA5_HAVE_GMAC
config ARCH_CHIP_ATSAMA5D35
bool "Atmel ATSAMA5D35"
select ARCH_CHIP_SAMA5D3
select SAMA5_HAVE_EMAC
select SAMA5_HAVE_GMAC
endchoice # Atmel AT91SAMA5 Chip Selection
@ -149,14 +154,16 @@ config SAMA5_UHPHS
config SAMA5_UDPHS
bool "USB Device High Speed (UDPHS)"
default n
depends on SAMA5_HAVE_GMAC
config SAMA5_GMAC
bool "Gigabit Ethernet MAC (GMAC)"
default n
config SAMA5_EMAC
bool "Ethernet MAC (EMAC)"
bool "10/100MBps Ethernet MAC (EMAC)"
default n
depends on SAMA5_HAVE_EMAC
config SAMA5_LCDC
bool "LCD Controller (LCDC)"
@ -241,6 +248,194 @@ config SAMA5_PIOE_IRQ
endif # PIO_IRQ
config SAMA5_HAVE_GMAC
bool
default n
config SAMA5_HAVE_EMAC
bool
default n
if SAMA5_EMAC
menu "EMAC device driver options"
config SAMA5_EMAC_NRXBUFFERS
int "Number of RX buffers"
default 16
---help---
EMAC buffer memory is segmented into 128 byte units (not
configurable). This setting provides the number of such 128 byte
units used for reception. This is also equal to the number of RX
descriptors that will be allocate.d The selected value must be an
even power of 2.
config SAMA5_EMAC_NTXBUFFERS
int "Number of TX buffers"
default 1
---help---
EMAC buffer memory is segmented into 128 byte units (not
configurable). This setting provides the number of such 128 byte
units used for transmission. This is also equal to the number of TX
descriptors that will be allocated. The selected value must be an
even power of 2.
config SAMA5_EMAC_PREALLOCATE
bool "Preallocate buffers"
default n
---help---
Buffer an descriptor many may either be allocated from the memory
pool or pre-allocated to lie in .bss. This options selected pre-
allocated buffer memory.
config SAMA5_EMAC_NBC
bool "Disable Broadcast"
default n
---help---
Select to disable receipt of broadcast packets.
config SAMA5_EMAC_PHYADDR
int "PHY address"
default 1
---help---
The 5-bit address of the PHY on the board. Default: 1
config SAMA5_EMAC_PHYINIT
bool "Board-specific PHY Initialization"
default n
---help---
Some boards require specialized initialization of the PHY before it can be used.
This may include such things as configuring GPIOs, resetting the PHY, etc. If
SAMA5_EMAC_PHYINIT is defined in the configuration then the board specific logic must
provide sam_phyinitialize(); The SAMA5 EMAC driver will call this function
one time before it first uses the PHY.
config SAMA5_EMAC_MII
bool "Use MII interface"
default n
---help---
Support Ethernet MII interface (vs RMII).
config SAMA5_EMAC_RMII
bool
default y if !SAMA5_EMAC_MII
default n if SAMA5_EMAC_MII
config SAMA5_EMAC_AUTONEG
bool "Use autonegotiation"
default y
---help---
Use PHY autonegotiation to determine speed and mode
config SAMA5_EMAC_ETHFD
bool "Full duplex"
default n
depends on !SAMA5_EMAC_AUTONEG
---help---
If SAMA5_EMAC_AUTONEG is not defined, then this may be defined to select full duplex
mode. Default: half-duplex
config SAMA5_EMAC_ETH100MBPS
bool "100 Mbps"
default n
depends on !SAMA5_EMAC_AUTONEG
---help---
If SAMA5_EMAC_AUTONEG is not defined, then this may be defined to select 100 MBps
speed. Default: 10 Mbps
config SAMA5_EMAC_PHYSR
int "PHY Status Register Address (decimal)"
depends on SAMA5_EMAC_AUTONEG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. The PHY status register
address may diff from PHY to PHY. This configuration sets the address of
the PHY status register.
config SAMA5_EMAC_PHYSR_ALTCONFIG
bool "PHY Status Alternate Bit Layout"
default n
depends on SAMA5_EMAC_AUTONEG
---help---
Different PHYs present speed and mode information in different ways. Some
will present separate information for speed and mode (this is the default).
Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
full/half duplex indication. This options selects an alternative representation
where speed and mode information are combined. This might mean, for example,
separate bits for 10HD, 100HD, 10FD and 100FD.
config SAMA5_EMAC_PHYSR_SPEED
hex "PHY Speed Mask"
depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This provides bit mask
for isolating the 10 or 100MBps speed indication.
config SAMA5_EMAC_PHYSR_100MBPS
hex "PHY 100Mbps Speed Value"
depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This provides the value
of the speed bit(s) indicating 100MBps speed.
config SAMA5_EMAC_PHYSR_MODE
hex "PHY Mode Mask"
depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This provide bit mask
for isolating the full or half duplex mode bits.
config SAMA5_EMAC_PHYSR_FULLDUPLEX
hex "PHY Full Duplex Mode Value"
depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This provides the
value of the mode bits indicating full duplex mode.
config SAMA5_EMAC_PHYSR_ALTMODE
hex "PHY Mode Mask"
depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This provide bit mask
for isolating the speed and full/half duplex mode bits.
config SAMA5_EMAC_PHYSR_10HD
hex "10MHz/Half Duplex Value"
depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, half duplex setting.
config SAMA5_EMAC_PHYSR_100HD
hex "100MHz/Half Duplex Value"
depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, half duplex setting.
config SAMA5_EMAC_PHYSR_10FD
hex "10MHz/Full Duplex Value"
depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, full duplex setting.
config SAMA5_EMAC_PHYSR_100FD
hex "100MHz/Full Duplex Value"
depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, full duplex setting.
config SAMA5_EMAC_REGDEBUG
bool "Register-Level Debug"
default n
depends on DEBUG
---help---
Enable very low-level register access debug. Depends on DEBUG.
endmenu # EMAC device driver options
endif # SAMA5_EMAC
if SAMA5_SPI0 || SAMA5_SPI1
menu "SPI device driver options"

9
arch/arm/src/sama5/Make.defs
View File

@ -140,6 +140,15 @@ endif
endif
endif
ifeq ($(CONFIG_NET),y)
ifeq ($(CONFIG_SAMA5_EMAC),y)
CHIP_CSRCS += sam_emac.c
endif
ifeq ($(CONFIG_SAMA5_GMAC),y)
CHIP_CSRCS += sam_gmac.c
endif
endif
ifeq ($(CONFIG_SAMA5_TWI0),y)
CHIP_CSRCS += sam_twi.c
else

72
arch/arm/src/sama5/chip/sam_emac.h
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@ -236,6 +236,8 @@
#define EMAC_INT_PTZ (1 << 13) /* Bit 13: Pause Time Zero */
#define EMAC_INT_WOL (1 << 14) /* Bit 14: Wake On LAN */
#define EMAC_INT_ALL (0x00007cff)
/* Phy Maintenance Register */
#define EMAC_MAN_DATA_SHIFT (0) /* Bits 0-15: Read/write data */
@ -256,7 +258,7 @@
# define EMAC_MAN_WRITE (1 << EMAC_MAN_RW_SHIFT)
#define EMAC_MAN_SOF_SHIFT (30) /* Bits 30-31: Start of frame */
#define EMAC_MAN_SOF_MASK (3 << EMAC_MAN_SOF_SHIFT)
# define EMAC_MAN_SOF_MASK (1 << EMAC_MAN_SOF_SHIFT) /* Must be written b01 */
# define EMAC_MAN_SOF (1 << EMAC_MAN_SOF_SHIFT) /* Must be written b01 */
/* Pause Time Register */
@ -387,49 +389,49 @@
/* Receive buffer descriptor: Address word */
#define RXDESC_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=EMAC owns */
#define RXDESC_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */
#define RXDESC_ADDR_MASK (0xfffffffc) /* Bits 2-31: Aligned buffer address */
#define EMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=EMAC owns */
#define EMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */
#define EMACRXD_ADDR_MASK (0xfffffffc) /* Bits 2-31: Aligned buffer address */
/* Receive buffer descriptor: Control word */
#define RXDESC_CTRL_FRLEN_SHIFT (0) /* Bits 0-11: Length of frame */
#define RXDESC_CTRL_FRLEN_MASK (0x000007ff << RXDESC_CTRL_FRLEN_SHIFT)
#define RXDESC_CTRL_BOFFS_SHIFT (12) /* Bits 12-13: Receive buffer offset */
#define RXDESC_CTRL_BOFFS_MASK (3 << RXDESC_CTRL_BOFFS_SHIFT)
#define RXDESC_CTRL_SOF (1 << 14) /* Bit 14: Start of frame */
#define RXDESC_CTRL_EOF (1 << 15) /* Bit 15: End of frame */
#define RXDESC_CTRL_CFI (1 << 16) /* Bit 16: Concatenation format indicator (CFI) bit */
#define RXDESC_CTRL_VLPRIO_SHIFT (17) /* Bits 17-19: VLAN priority */
#define RXDESC_CTRL_VLPRIO_MASK (7 << RXDESC_CTRL_VLANPRIO_SHIFT)
#define RXDESC_CTRL_PRIODET (1 << 20) /* Bit 20: Priority tag detected */
#define RXDESC_CTRL_VLANTAG (1 << 21) /* Bit 21: VLAN tag detected */
#define RXDESC_CTRL_TYPEID (1 << 22) /* Bit 22: Type ID match */
#define RXDESC_CTRL_ADDR4 (1 << 23) /* Bit 23: Specific address register 4 match */
#define RXDESC_CTRL_ADDR3 (1 << 24) /* Bit 24: Specific address register 3 match */
#define RXDESC_CTRL_ADDR2 (1 << 25) /* Bit 25: Specific address register 2 match */
#define RXDESC_CTRL_ADDR1 (1 << 26) /* Bit 26: Specific address register 1 match */
#define EMACRXD_CTRL_FRLEN_SHIFT (0) /* Bits 0-11: Length of frame */
#define EMACRXD_CTRL_FRLEN_MASK (0x000007ff << EMACRXD_CTRL_FRLEN_SHIFT)
#define EMACRXD_CTRL_BOFFS_SHIFT (12) /* Bits 12-13: Receive buffer offset */
#define EMACRXD_CTRL_BOFFS_MASK (3 << EMACRXD_CTRL_BOFFS_SHIFT)
#define EMACRXD_CTRL_SOF (1 << 14) /* Bit 14: Start of frame */
#define EMACRXD_CTRL_EOF (1 << 15) /* Bit 15: End of frame */
#define EMACRXD_CTRL_CFI (1 << 16) /* Bit 16: Concatenation format indicator (CFI) bit */
#define EMACRXD_CTRL_VLPRIO_SHIFT (17) /* Bits 17-19: VLAN priority */
#define EMACRXD_CTRL_VLPRIO_MASK (7 << EMACRXD_CTRL_VLANPRIO_SHIFT)
#define EMACRXD_CTRL_PRIODET (1 << 20) /* Bit 20: Priority tag detected */
#define EMACRXD_CTRL_VLANTAG (1 << 21) /* Bit 21: VLAN tag detected */
#define EMACRXD_CTRL_TYPEID (1 << 22) /* Bit 22: Type ID match */
#define EMACRXD_CTRL_ADDR4 (1 << 23) /* Bit 23: Specific address register 4 match */
#define EMACRXD_CTRL_ADDR3 (1 << 24) /* Bit 24: Specific address register 3 match */
#define EMACRXD_CTRL_ADDR2 (1 << 25) /* Bit 25: Specific address register 2 match */
#define EMACRXD_CTRL_ADDR1 (1 << 26) /* Bit 26: Specific address register 1 match */
/* Bit 27: Reserved */
#define RXDESC_CTRL_EXTADDR (1 << 28) /* Bit 28: External address match */
#define RXDESC_CTRL_UCAST (1 << 29) /* Bit 29: Unicast hash match */
#define RXDESC_CTRL_MCAST (1 << 30) /* Bit 30: Multicast hash match */
#define RXDESC_CTRL_ONES (1 << 31) /* Bit 31: Global all ones broadcast address detected */
#define EMACRXD_CTRL_EXTADDR (1 << 28) /* Bit 28: External address match */
#define EMACRXD_CTRL_UCAST (1 << 29) /* Bit 29: Unicast hash match */
#define EMACRXD_CTRL_MCAST (1 << 30) /* Bit 30: Multicast hash match */
#define EMACRXD_CTRL_BCAST (1 << 31) /* Bit 31: Global all ones broadcast address detected */
/* Transmit buffer descriptor: Address word (un-aligned, 32-bit address */
/* Transmit buffer descriptor: Control word */
#define TXDESC_CTRL_BUFLEN_SHIFT (0) /* Bits 0-10: Length of buffer */
#define TXDESC_CTRL_BUFLEN_MASK (0x000003ff << TXDESC_CTRL_BUFLEN_SHIFT)
#define EMACTXD_CTRL_BUFLEN_SHIFT (0) /* Bits 0-10: Length of buffer */
#define EMACTXD_CTRL_BUFLEN_MASK (0x000003ff << EMACTXD_CTRL_BUFLEN_SHIFT)
/* Bits 11-14: Reserved */
#define TXDESC_CTRL_LAST (1 << 15) /* Bit 15: Last buffer in the current frame */
#define TXDESC_CTRL_NOCRC (1 << 16) /* Bit 16: No CRC*/
#define EMACTXD_CTRL_LAST (1 << 15) /* Bit 15: Last buffer in the current frame */
#define EMACTXD_CTRL_NOCRC (1 << 16) /* Bit 16: No CRC*/
/* Bits 17-26: Reserved */
#define TXDESC_CTRL_NOBUFFER (1 << 27) /* Bit 27: Buffers exhausted in mid frame*/
#define TXDESC_CTRL_TXUR (1 << 28) /* Bit 28: Transmit underrun*/
#define TXDESC_CTRL_TXERR (1 << 29) /* Bit 29: Retry limit exceeded, transmit error detected*/
#define TXDESC_CTRL_WRAP (1 << 30) /* Bit 30: Last descriptor in descriptor list*/
#define TXDESC_CTRL_USED (1 << 31) /* Bit 31: Zero for the EMAC to read from buffer*/
#define EMACTXD_CTRL_NOBUFFER (1 << 27) /* Bit 27: Buffers exhausted in mid frame*/
#define EMACTXD_CTRL_TXUR (1 << 28) /* Bit 28: Transmit underrun*/
#define EMACTXD_CTRL_TXERR (1 << 29) /* Bit 29: Retry limit exceeded, transmit error detected*/
#define EMACTXD_CTRL_WRAP (1 << 30) /* Bit 30: Last descriptor in descriptor list*/
#define EMACTXD_CTRL_USED (1 << 31) /* Bit 31: Zero for the EMAC to read from buffer*/
/************************************************************************************
* Public Types
@ -439,7 +441,7 @@
struct emac_rxdesc_s
{
uint32_t addr; /* Buffer address */
uint32_t ctrl; /* RX controls */
uint32_t status; /* RX status and controls */
};
/* Transmit buffer descriptor */
@ -447,6 +449,6 @@ struct emac_rxdesc_s
struct emac_txdesc_s
{
uint32_t addr; /* Buffer address */
uint32_t ctrl; /* TX controls */
uint32_t status; /* TX status and controls */
};
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMAC_H */

14
arch/arm/src/sama5/chip/sam_gmac.h
View File

@ -148,8 +148,8 @@
#define SAM_GMAC_EFRN_OFFSET 0x01ec /* PTP Event Frame Received Nanoseconds */
#define SAM_GMAC_PEFTS_OFFSET 0x01f0 /* PTP Peer Event Frame Transmitted Seconds */
#define SAM_GMAC_PEFTN_OFFSET 0x01f4 /* PTP Peer Event Frame Transmitted Nanoseconds */
#define SAM_GMAC_PEFRS_OFFSET 0x01f8 /* PTP Peer Event Frame ReceiveGMAC_PEFRNd Seconds */
#define SAM_GMAC_PEFRS_OFFSET 0x01fc /* PTP Peer Event Frame Received Nanoseconds */
#define SAM_GMAC_PEFRS_OFFSET 0x01f8 /* PTP Peer Event Frame Received Seconds */
#define SAM_GMAC_PEFRN_OFFSET 0x01fc /* PTP Peer Event Frame Received Nanoseconds */
/* 0x0200-0x023c Reserved */
/* 0x0280-0x0298 Reserved */
#define SAM_GMAC_ISRPQ_OFFSET(n) (0x400 + ((n) << 2)) /* n=0..6 */
@ -344,7 +344,7 @@
#define SAM_GMAC_PEFTS (SAM_GMAC_VBASE+SAM_GMAC_PEFTS_OFFSET)
#define SAM_GMAC_PEFTN (SAM_GMAC_VBASE+SAM_GMAC_PEFTN_OFFSET)
#define SAM_GMAC_PEFRS (SAM_GMAC_VBASE+SAM_GMAC_PEFRS_OFFSET)
#define SAM_GMAC_PEFRS (SAM_GMAC_VBASE+SAM_GMAC_PEFRS_OFFSET)
#define SAM_GMAC_PEFRN (SAM_GMAC_VBASE+SAM_GMAC_PEFRN_OFFSET)
#define SAM_GMAC_ISRPQ(n) (SAM_GMAC_VBASE+SAM_GMAC_ISRPQ_OFFSET(n))
#define SAM_GMAC_ISRPQ0 (SAM_GMAC_VBASE+SAM_GMAC_ISRPQ0_OFFSET)
#define SAM_GMAC_ISRPQ1 (SAM_GMAC_VBASE+SAM_GMAC_ISRPQ1_OFFSET)
@ -628,8 +628,8 @@
#define GMAC_PEFTS_
/* PTP Peer Event Frame Transmitted Nanoseconds */
#define GMAC_PEFTN_
/* PTP Peer Event Frame ReceiveGMAC_PEFRNd Seconds */
#define GMAC_PEFRS_
/* PTP Peer Event Frame Received Seconds */
#define GMAC_PEFRN_
/* PTP Peer Event Frame Received Nanoseconds */
#define GMAC_PEFRS_
/* Interrupt Status Register Priority Queue 0-6 */
@ -651,8 +651,4 @@
/* Interrupt Mask Register Priority Queue 0-6 */
#define GMAC_IMRPQ0_
(1 << nn) /* Bit nn:
_SHIFT (nn) /* Bits nn-nn:
_MASK (xx << yy)
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_GMAC_H */

1371
arch/arm/src/sama5/sam_emac.c
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