diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h index 610ad37282..555669585b 100644 --- a/arch/arm/include/stm32/chip.h +++ b/arch/arm/include/stm32/chip.h @@ -104,7 +104,7 @@ /* (2) Comparators */ # define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ # define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NETHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -142,7 +142,7 @@ /* (2) Comparators */ # define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ # define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NETHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -180,7 +180,7 @@ /* (2) Comparators */ # define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ # define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NETHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -218,7 +218,7 @@ /* (2) Comparators */ # define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ # define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NETHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -256,7 +256,7 @@ /* (2) Comparators */ # define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ # define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NETHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -294,7 +294,7 @@ /* (2) Comparators */ # define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ # define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NETHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -332,7 +332,7 @@ # define STM32_NDAC 2 /* DAC 1-2 */ # define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ # define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NETHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -367,7 +367,7 @@ # define STM32_NDAC 2 /* DAC 1-2 */ # define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ # define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NETHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -405,7 +405,7 @@ # define STM32_NDAC 2 /* DAC 1-2 */ # define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ # define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NETHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -441,13 +441,14 @@ # define STM32_NDAC 2 /* DAC 1-2 */ # define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ # define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NETHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ /* STM32 F103 Low Density Family *************************************************/ /* STM32F103C4 & STM32F103C6 */ + #elif defined(CONFIG_ARCH_CHIP_STM32F103C4) # define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */ # define CONFIG_STM32_LOWDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ @@ -456,7 +457,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ -# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ @@ -474,7 +475,7 @@ # define STM32_NADC 2 /* ADC1-2 */ # define STM32_NDAC 0 /* No DAC */ # define STM32_NCRC 1 /* CRC */ -# define STM32_NTHERNET 0 /* No ethernet */ +# define STM32_NTHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -511,7 +512,7 @@ # define STM32_NDAC 0 /* No DAC */ # define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ # define STM32_NCRC 1 /* CRC */ -# define STM32_NTHERNET 0 /* No ethernet */ +# define STM32_NTHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -546,7 +547,7 @@ # define STM32_NDAC 0 /* No DAC */ # define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ # define STM32_NCRC 1 /* CRC */ -# define STM32_NTHERNET 0 /* No ethernet */ +# define STM32_NTHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -581,7 +582,7 @@ # define STM32_NDAC 0 /* No DAC */ # define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ # define STM32_NCRC 1 /* CRC */ -# define STM32_NTHERNET 0 /* No ethernet */ +# define STM32_NTHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -604,7 +605,7 @@ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* 16-bit generall timers TIM2,3,4,5 with DMA */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2,3,4,5 with DMA */ # define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */ # define STM32_NDMA 2 /* DMA1-2 */ # define STM32_NSPI 3 /* SPI1-3 */ @@ -620,7 +621,7 @@ # define STM32_NDAC 2 /* DAC1-2 */ # define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ # define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NETHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -658,7 +659,7 @@ # define STM32_NDAC 2 /* DAC1-2 */ # define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ # define STM32_NCRC 1 /* CRC */ -# define STM32_NTHERNET 0 /* No ethernet */ +# define STM32_NTHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -680,7 +681,7 @@ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 4 /* 16-bit generall timers TIM2,3,4,5 with DMA */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2,3,4,5 with DMA */ # define STM32_NBTIM 0 /* No basic timers */ # define STM32_NDMA 2 /* DMA1-2 */ # define STM32_NSPI 3 /* SPI1-3 */ @@ -696,7 +697,7 @@ # define STM32_NDAC 0 /* No DAC */ # define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ # define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NETHERNET 0 /* No Ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ @@ -716,7 +717,7 @@ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit generall timers TIM2,3,4,5 with DMA */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2,3,4,5 with DMA */ # define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ # define STM32_NDMA 2 /* DMA1-2 */ # define STM32_NSPI 3 /* SPI1-3 */ @@ -750,7 +751,7 @@ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit generall timers TIM2,3,4,5 with DMA */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2,3,4,5 with DMA */ # define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ # define STM32_NDMA 2 /* DMA1-2 */ # define STM32_NSPI 3 /* SPI1-3 */ @@ -817,9 +818,9 @@ # undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ -# define CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ -# undef CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ # define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA @@ -1660,7 +1661,6 @@ # define STM32_NRNG 1 /* Random number generator (RNG) */ # define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - #else # error "Unsupported STM32 chip" #endif diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 6fd470569f..174061e1c0 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -564,6 +564,10 @@ endchoice config STM32_STM32L15XX bool default n + +config STM32_ENERGYLITE + bool + default n select STM32_HAVE_USBDEV select STM32_HAVE_USART3 select STM32_HAVE_TIM6 @@ -571,19 +575,7 @@ config STM32_STM32L15XX select STM32_HAVE_TIM9 select STM32_HAVE_TIM10 select STM32_HAVE_TIM11 - -config STM32_ENERGYLITE - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_USART4 - select STM32_HAVE_USART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM10 + select STM32_HAVE_ADC2 config STM32_STM32F10XX bool @@ -605,6 +597,7 @@ config STM32_VALUELINE select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 + select STM32_HAVE_ADC2 config STM32_CONNECTIVITYLINE bool @@ -618,6 +611,9 @@ config STM32_CONNECTIVITYLINE select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 config STM32_PERFORMANCELINE bool @@ -631,6 +627,8 @@ config STM32_PERFORMANCELINE select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 config STM32_HIGHDENSITY bool @@ -644,6 +642,9 @@ config STM32_HIGHDENSITY select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 config STM32_MEDIUMDENSITY bool @@ -656,6 +657,9 @@ config STM32_MEDIUMDENSITY select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 config STM32_LOWDENSITY bool @@ -668,6 +672,8 @@ config STM32_LOWDENSITY select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 if !STM32_VALUELINE config STM32_STM32F20XX bool @@ -690,6 +696,10 @@ config STM32_STM32F20XX select STM32_HAVE_TIM12 select STM32_HAVE_TIM13 select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 config STM32_STM32F30XX bool @@ -703,6 +713,10 @@ config STM32_STM32F30XX select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_CAN1 config STM32_STM32F40XX bool @@ -739,6 +753,10 @@ config STM32_STM32F405 select STM32_HAVE_TIM12 select STM32_HAVE_TIM13 select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 config STM32_STM32F407 bool @@ -760,6 +778,10 @@ config STM32_STM32F407 select STM32_HAVE_TIM12 select STM32_HAVE_TIM13 select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 # This is really 427/437, but we treat the two the same. config STM32_STM32F427 @@ -784,6 +806,10 @@ config STM32_STM32F427 select STM32_HAVE_TIM12 select STM32_HAVE_TIM13 select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 # This is really 429/439, but we treat the two the same. config STM32_STM32F429 @@ -807,6 +833,10 @@ config STM32_STM32F429 select STM32_HAVE_TIM12 select STM32_HAVE_TIM13 select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 config STM32_DFU bool "DFU bootloader" @@ -917,6 +947,26 @@ config STM32_HAVE_TIM17 bool default n +config STM32_HAVE_ADC2 + bool + default n + +config STM32_HAVE_ADC3 + bool + default n + +config STM32_HAVE_ADC4 + bool + default n + +config STM32_HAVE_CAN1 + bool + default n + +config STM32_HAVE_CAN2 + bool + default n + # These are the peripheral selections proper config STM32_ADC1 @@ -928,19 +978,19 @@ config STM32_ADC2 bool "ADC2" default n select STM32_ADC - depends on !STM32_VALUELINE + depends on STM32_HAVE_ADC2 config STM32_ADC3 bool "ADC3" default n select STM32_ADC - depends on !STM32_VALUELINE + depends on STM32_HAVE_ADC3 config STM32_ADC4 bool "ADC4" default n select STM32_ADC - depends on STM32_STM32F30XX + depends on STM32_HAVE_ADC4 config STM32_COMP bool "COMP" @@ -962,14 +1012,14 @@ config STM32_CAN1 default n select CAN select STM32_CAN - depends on !STM32_VALUELINE && !STM32_STM32L15XX + depends on STM32_HAVE_CAN1 config STM32_CAN2 bool "CAN2" default n - depends on STM32_STM32F20XX || STM32_STM32F40XX select CAN select STM32_CAN + depends on STM32_HAVE_CAN2 config STM32_CCMDATARAM bool "CMD/DATA RAM" diff --git a/binfmt/symtab_findorderedbyname.c b/binfmt/symtab_findorderedbyname.c index 7ca2ea0338..ce63b458b0 100644 --- a/binfmt/symtab_findorderedbyname.c +++ b/binfmt/symtab_findorderedbyname.c @@ -139,4 +139,3 @@ symtab_findorderedbyname(FAR const struct symtab_s *symtab, return strcmp(name, symtab[low].sym_name) == 0 ? &symtab[low] : NULL; } -