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imxrt:lpi2c add parens for macros expansions

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David Sidrane 2022-06-01 14:00:23 -07:00 committed by Xiang Xiao
parent 22d41f6b9c
commit f34acdb936
1 changed files with 30 additions and 30 deletions
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60
arch/arm/src/imxrt/hardware/imxrt_lpi2c.h
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@ -301,7 +301,7 @@
/* LPI2C Master Config Register 1 */
#define LPI2C_MCFGR1_PRESCALE_MASK (7 << 0) /* Clock Prescaler Bit Mask */
#define LPI2C_MCFGR1_PRESCALE(n) (n & LPI2C_MCFGR1_PRESCALE_MASK)
#define LPI2C_MCFGR1_PRESCALE(n) ((n) & LPI2C_MCFGR1_PRESCALE_MASK)
# define LPI2C_MCFGR1_PRESCALE_1 (0)
# define LPI2C_MCFGR1_PRESCALE_2 (1)
# define LPI2C_MCFGR1_PRESCALE_4 (2)
@ -316,7 +316,7 @@
/* Bits 15-11 Reserved */
#define LPI2C_MCFGR1_MATCFG_SHIFT (16)
#define LPI2C_MCFGR1_MATCFG_MASK (7 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match Configuration Bit Mask */
#define LPI2C_MCFGR1_MATCFG(n) ((n << LPI2C_MCFGR1_MATCFG_SHIFT) & LPI2C_MCFGR1_MATCFG_MASK)
#define LPI2C_MCFGR1_MATCFG(n) (((n) << LPI2C_MCFGR1_MATCFG_SHIFT) & LPI2C_MCFGR1_MATCFG_MASK)
# define LPI2C_MCFGR1_MATCFG_DISABLE (0 << LPI2C_MCFGR1_MATCFG_SHIFT)
/* LPI2C_MCFG1_MATCFG = 001b Reserved */
# define LPI2C_MCFGR1_MATCFG2 (2 << LPI2C_MCFGR1_MATCFG_SHIFT)
@ -328,7 +328,7 @@
/* Bits 23-19 Reserved */
#define LPI2C_MCFGR1_PINCFG_SHIFT (24)
#define LPI2C_MCFGR1_PINCFG_MASK (7 << LPI2C_MCFGR1_PINCFG_SHIFT) /* Pin Configuration Bit Mask */
#define LPI2C_MCFGR1_PINCFG(n) ((n << LPI2C_MCFGR1_PINCFG_SHIFT) & LPI2C_MCFGR1_PINCFG_MASK)
#define LPI2C_MCFGR1_PINCFG(n) (((n) << LPI2C_MCFGR1_PINCFG_SHIFT) & LPI2C_MCFGR1_PINCFG_MASK)
# define LPI2C_MCFGR1_PINCFG0 (0 << LPI2C_MCFGR1_PINCFG_SHIFT)
# define LPI2C_MCFGR1_PINCFG1 (1 << LPI2C_MCFGR1_PINCFG_SHIFT)
# define LPI2C_MCFGR1_PINCFG2 (2 << LPI2C_MCFGR1_PINCFG_SHIFT)
@ -343,17 +343,17 @@
#define LPI2C_MCFG2_BUSIDLE_MASK (0xfff << 0) /* Bus Idle Timeout Period in Clock Cycles */
#define LPI2C_MCFG2_BUSIDLE_DISABLE (0)
#define LPI2C_MCFG2_BUSIDLE(n) (n & LPI2C_MCFG2_BUSIDLE_MASK)
#define LPI2C_MCFG2_BUSIDLE(n) ((n) & LPI2C_MCFG2_BUSIDLE_MASK)
/* Bits 15-12 Reserved */
#define LPI2C_MCFG2_FILTSCL_SHIFT (16)
#define LPI2C_MCFG2_FILTSCL_MASK (15 << LPI2C_MCFG2_FILTSCL_SHIFT) /* Glitch Filter SCL */
#define LPI2C_MCFG2_FILTSCL_DISABLE (0 << LPI2C_MCFG2_FILTSCL_SHIFT)
#define LPI2C_MCFG2_FILTSCL_CYCLES(n) ((n << LPI2C_MCFG2_FILTSCL_SHIFT) & LPI2C_MCFG2_FILTSCL_MASK)
#define LPI2C_MCFG2_FILTSCL_CYCLES(n) (((n) << LPI2C_MCFG2_FILTSCL_SHIFT) & LPI2C_MCFG2_FILTSCL_MASK)
/* Bits 23-20 Reserved */
#define LPI2C_MCFG2_FILTSDA_SHIFT (24)
#define LPI2C_MCFG2_FILTSDA_MASK (15 << LPI2C_MCFG2_FILTSDA_SHIFT) /* Glitch Filter SDA */
#define LPI2C_MCFG2_FILTSDA_DISABLE (0 << LPI2C_MCFG2_FILTSDA_SHIFT)
#define LPI2C_MCFG2_FILTSDA_CYCLES(n) ((n << LPI2C_MCFG2_FILTSDA_SHIFT) & LPI2C_MCFG2_FILTSDA_MASK)
#define LPI2C_MCFG2_FILTSDA_CYCLES(n) (((n) << LPI2C_MCFG2_FILTSDA_SHIFT) & LPI2C_MCFG2_FILTSDA_MASK)
/* Bits 31-28 Reserved */
/* LPI2C Master Config Register 3 */
@ -361,57 +361,57 @@
/* Bits 7-0 Reserved */
#define LPI2C_MCFG3_PINLOW_SHIFT (8)
#define LPI2C_MCFG3_PINLOW_MASK (0xfff << LPI2C_MCFG3_PINLOW_SHIFT) /* Configure The Pin Low Timeout in Clock Cycles */
#define LPI2C_MCFG3_PINLOW_CYCLES(n) ((n << LPI2C_MCFG3_PINLOW_SHIFT) & LPI2C_MCFG3_PINLOW_MASK)
#define LPI2C_MCFG3_PINLOW_CYCLES(n) (((n) << LPI2C_MCFG3_PINLOW_SHIFT) & LPI2C_MCFG3_PINLOW_MASK)
/* Bits 31-20 Reserved */
/* LPI2C Master Data Match Register */
#define LPI2C_MDMR_MATCH0_SHIFT (0)
#define LPI2C_MDMR_MATCH0_MASK (0xff << LPI2C_MDMR_MATCH0_SHIFT) /* Match 0 Value */
#define LPI2C_MDMR_MATCH0(n) ((n << LPI2C_MDMR_MATCH0_SHIFT) & LPI2C_MDMR_MATCH0_MASK)
#define LPI2C_MDMR_MATCH0(n) (((n) << LPI2C_MDMR_MATCH0_SHIFT) & LPI2C_MDMR_MATCH0_MASK)
/* Bits 15-8 Reserved */
#define LPI2C_MDMR_MATCH1_SHIFT (16)
#define LPI2C_MDMR_MATCH1_MASK (0xff << LPI2C_MDMR_MATCH1_SHIFT) /* Match 1 Value */
#define LPI2C_MDMR_MATCH1(n) ((n << LPI2C_MDMR_MATCH1_SHIFT) & LPI2C_MDMR_MATCH1_MASK)
#define LPI2C_MDMR_MATCH1(n) (((n) << LPI2C_MDMR_MATCH1_SHIFT) & LPI2C_MDMR_MATCH1_MASK)
/* Bits 31-24 Reserved */
/* LPI2C Master Clock Configuration Register 0 */
#define LPI2C_MCCR0_CLKLO_SHIFT (0)
#define LPI2C_MCCR0_CLKLO_MASK (0x3f << LPI2C_MCCR0_CLKLO_SHIFT) /* Clock Low Period */
#define LPI2C_MCCR0_CLKLO(n) ((n << LPI2C_MCCR0_CLKLO_SHIFT) & LPI2C_MCCR0_CLKLO_MASK)
#define LPI2C_MCCR0_CLKLO(n) (((n) << LPI2C_MCCR0_CLKLO_SHIFT) & LPI2C_MCCR0_CLKLO_MASK)
/* Bits 7-6 Reserved */
#define LPI2C_MCCR0_CLKHI_SHIFT (8)
#define LPI2C_MCCR0_CLKHI_MASK (0x3f << LPI2C_MCCR0_CLKHI_SHIFT) /* Clock High Period */
#define LPI2C_MCCR0_CLKHI(n) ((n << LPI2C_MCCR0_CLKHI_SHIFT) & LPI2C_MCCR0_CLKHI_MASK)
#define LPI2C_MCCR0_CLKHI(n) (((n) << LPI2C_MCCR0_CLKHI_SHIFT) & LPI2C_MCCR0_CLKHI_MASK)
/* Bits 15-14 Reserved */
#define LPI2C_MCCR0_SETHOLD_SHIFT (16)
#define LPI2C_MCCR0_SETHOLD_MASK (0x3f << LPI2C_MCCR0_SETHOLD_SHIFT) /* Setup Hold Delay */
#define LPI2C_MCCR0_SETHOLD(n) ((n << LPI2C_MCCR0_SETHOLD_SHIFT) & LPI2C_MCCR0_SETHOLD_MASK)
#define LPI2C_MCCR0_SETHOLD(n) (((n) << LPI2C_MCCR0_SETHOLD_SHIFT) & LPI2C_MCCR0_SETHOLD_MASK)
/* Bits 23-22 Reserved */
#define LPI2C_MCCR0_DATAVD_SHIFT (24)
#define LPI2C_MCCR0_DATAVD_MASK (0x3f << LPI2C_MCCR0_DATAVD_SHIFT) /* Setup Hold Delay */
#define LPI2C_MCCR0_DATAVD(n) ((n << LPI2C_MCCR0_DATAVD_SHIFT) & LPI2C_MCCR0_DATAVD_MASK)
#define LPI2C_MCCR0_DATAVD(n) (((n) << LPI2C_MCCR0_DATAVD_SHIFT) & LPI2C_MCCR0_DATAVD_MASK)
/* Bits 31-30 Reserved */
/* LPI2C Master Clock Configuration Register 1 */
#define LPI2C_MCCR1_CLKLO_SHIFT (0)
#define LPI2C_MCCR1_CLKLO_MASK (0x3f << LPI2C_MCCR1_CLKLO_SHIFT) /* Clock Low Period */
#define LPI2C_MCCR1_CLKLO(n) ((n << LPI2C_MCCR1_CLKLO_SHIFT) & LPI2C_MCCR1_CLKLO_MASK)
#define LPI2C_MCCR1_CLKLO(n) (((n) << LPI2C_MCCR1_CLKLO_SHIFT) & LPI2C_MCCR1_CLKLO_MASK)
/* Bits 7-6 Reserved */
#define LPI2C_MCCR1_CLKHI_SHIFT (8)
#define LPI2C_MCCR1_CLKHI_MASK (0x3f << LPI2C_MCCR1_CLKHI_SHIFT) /* Clock High Period */
#define LPI2C_MCCR1_CLKHI(n) ((n << LPI2C_MCCR1_CLKHI_SHIFT) & LPI2C_MCCR1_CLKHI_MASK)
#define LPI2C_MCCR1_CLKHI(n) (((n) << LPI2C_MCCR1_CLKHI_SHIFT) & LPI2C_MCCR1_CLKHI_MASK)
/* Bits 15-14 Reserved */
#define LPI2C_MCCR1_SETHOLD_SHIFT (16)
#define LPI2C_MCCR1_SETHOLD_MASK (0x3f << LPI2C_MCCR1_SETHOLD_SHIFT) /* Setup Hold Delay */
#define LPI2C_MCCR1_SETHOLD(n) ((n << LPI2C_MCCR1_SETHOLD_SHIFT) & LPI2C_MCCR1_SETHOLD_MASK)
#define LPI2C_MCCR1_SETHOLD(n) (((n) << LPI2C_MCCR1_SETHOLD_SHIFT) & LPI2C_MCCR1_SETHOLD_MASK)
/* Bits 23-22 Reserved */
#define LPI2C_MCCR1_DATAVD_SHIFT (24)
#define LPI2C_MCCR1_DATAVD_MASK (0x3f << LPI2C_MCCR1_DATAVD_SHIFT) /* Setup Hold Delay */
#define LPI2C_MCCR1_DATAVD(n) ((n << LPI2C_MCCR1_DATAVD_SHIFT) & LPI2C_MCCR1_DATAVD_MASK)
#define LPI2C_MCCR1_DATAVD(n) (((n) << LPI2C_MCCR1_DATAVD_SHIFT) & LPI2C_MCCR1_DATAVD_MASK)
/* Bits 31-30 Reserved */
@ -420,13 +420,13 @@
#define LPI2C_MFCR_TXWATER_SHIFT (0)
#define LPI2C_MFCR_TXWATER_MASK (3 << LPI2C_MFCR_TXWATER_SHIFT) /* Transmit FIFO Watermark*/
#define LPI2C_MFCR_TXWATER(n) ((n << LPI2C_MFCR_TXWATER_SHIFT) & LPI2C_MFCR_TXWATER_MASK) /* Transmit FIFO Watermark */
#define LPI2C_MFCR_TXWATER(n) (((n) << LPI2C_MFCR_TXWATER_SHIFT) & LPI2C_MFCR_TXWATER_MASK) /* Transmit FIFO Watermark */
/* Bits 15-2 Reserved */
#define LPI2C_MFCR_RXWATER_SHIFT (16)
#define LPI2C_MFCR_RXWATER_MASK (3 << LPI2C_MFCR_RXWATER_SHIFT) /* Receive FIFO Watermark */
#define LPI2C_MFCR_RXWATER(n) ((n << LPI2C_MFCR_RXWATER_SHIFT) & LPI2C_MFCR_RXWATER_MASK) /* Transmit FIFO Watermark */
#define LPI2C_MFCR_RXWATER(n) (((n) << LPI2C_MFCR_RXWATER_SHIFT) & LPI2C_MFCR_RXWATER_MASK) /* Transmit FIFO Watermark */
/* Bits 31-18 Reserved */
@ -445,10 +445,10 @@
#define LPI2C_MTDR_DATA_SHIFT (0)
#define LPI2C_MTDR_DATA_MASK (0xff << LPI2C_MTDR_DATA_SHIFT) /* Transmit Data */
#define LPI2C_MTDR_DATA(n) (n & LPI2C_MTDR_DATA_MASK)
#define LPI2C_MTDR_DATA(n) ((n) & LPI2C_MTDR_DATA_MASK)
#define LPI2C_MTDR_CMD_SHIFT (8)
#define LPI2C_MTDR_CMD_MASK (7 << LPI2C_MTDR_CMD_SHIFT) /* Command Data */
#define LPI2C_MTDR_CMD(n) ((n << LPI2C_MTDR_CMD_SHIFT) & LPI2C_MTDR_CMD_MASK)
#define LPI2C_MTDR_CMD(n) (((n) << LPI2C_MTDR_CMD_SHIFT) & LPI2C_MTDR_CMD_MASK)
# define LPI2C_MTDR_CMD_TXD (0 << LPI2C_MTDR_CMD_SHIFT)
# define LPI2C_MTDR_CMD_RXD (1 << LPI2C_MTDR_CMD_SHIFT)
# define LPI2C_MTDR_CMD_STOP (2 << LPI2C_MTDR_CMD_SHIFT)
@ -543,7 +543,7 @@
/* Bits 15-14 Reserved */
#define LPI2C_SCFG1_ADDRCFG_SHIFT (16)
#define LPI2C_SCFG1_ADDRCFG_MASK (7 << LPI2C_SCFG1_ADDRCFG_SHIFT) /* Address Configuration Bit Mask */
#define LPI2C_SCFG1_ADDRCFG(n) ((n << LPI2C_SCFG1_ADDRCFG_SHIFT) & LPI2C_SCFG1_ADDRCFG_MASK)
#define LPI2C_SCFG1_ADDRCFG(n) (((n) << LPI2C_SCFG1_ADDRCFG_SHIFT) & LPI2C_SCFG1_ADDRCFG_MASK)
# define LPI2C_SCFG1_ADDRCFG0 (0 << LPI2C_SCFG1_ADDRCFG_SHIFT)
# define LPI2C_SCFG1_ADDRCFG1 (2 << LPI2C_SCFG1_ADDRCFG_SHIFT)
# define LPI2C_SCFG1_ADDRCFG2 (2 << LPI2C_SCFG1_ADDRCFG_SHIFT)
@ -557,21 +557,21 @@
/* LPI2C Slave Configuration Register 2 */
#define LPI2C_SCFG2_CLKHOLD_MASK (15 << 0) /* Clock Hold Time */
#define LPI2C_SCFG2_CLKHOLD(n) (n & LPI2C_SCFG2_CLKHOLD_MASK)
#define LPI2C_SCFG2_CLKHOLD(n) ((n) & LPI2C_SCFG2_CLKHOLD_MASK)
/* Bits 7-4 Reserved */
#define LPI2C_SCFG2_DATAVD_SHIFT (8)
#define LPI2C_SCFG2_DATAVD_MASK (0x3f << LPI2C_SCFG2_DATAVD_SHIFT) /* Data Valid Delay */
#define LPI2C_SCFG2_DATAVD(n) ((n << LPI2C_SCFG2_DATAVD_SHIFT) & LPI2C_SCFG2_DATAVD_MASK)
#define LPI2C_SCFG2_DATAVD(n) (((n) << LPI2C_SCFG2_DATAVD_SHIFT) & LPI2C_SCFG2_DATAVD_MASK)
/* Bits 15-14 Reserved */
#define LPI2C_SCFG2_FILTSCL_SHIFT (16)
#define LPI2C_SCFG2_FILTSCL_MASK (15 << LPI2C_SCFG2_FILTSCL_SHIFT) /* Glitch Filter SCL */
#define LPI2C_SCFG2_FILTSCL_DISABLE (0 << LPI2C_SCFG2_FILTSCL_SHIFT)
#define LPI2C_SCFG2_FILTSCL_CYCLES(n) ((n << LPI2C_SCFG2_FILTSCL_SHIFT) & LPI2C_SCFG2_FILTSCL_MASK)
#define LPI2C_SCFG2_FILTSCL_CYCLES(n) (((n) << LPI2C_SCFG2_FILTSCL_SHIFT) & LPI2C_SCFG2_FILTSCL_MASK)
/* Bits 23-20 Reserved */
#define LPI2C_SCFG2_FILTSDA_SHIFT (24)
#define LPI2C_SCFG2_FILTSDA_MASK (15 << LPI2C_SCFG2_FILTSDA_SHIFT) /* Glitch Filter SDA */
#define LPI2C_SCFG2_FILTSDA_DISABLE (0 << LPI2C_SCFG2_FILTSDA_SHIFT)
#define LPI2C_SCFG2_FILTSDA_CYCLES(n) ((n << LPI2C_SCFG2_FILTSDA_SHIFT) & LPI2C_SCFG2_FILTSDA_MASK)
#define LPI2C_SCFG2_FILTSDA_CYCLES(n) (((n) << LPI2C_SCFG2_FILTSDA_SHIFT) & LPI2C_SCFG2_FILTSDA_MASK)
/* Bits 31-28 Reserved */
/* LPI2C Slave Address Match Register */
@ -579,11 +579,11 @@
/* Bit 0 Reserved */
#define LPI2C_SAMR_ADDR0_SHIFT (1)
#define LPI2C_SAMR_ADDR0_MASK (0x3ff << LPI2C_SAMR_ADDR0_SHIFT) /* Address 0 Value */
#define LPI2C_SAMR_ADDR0(n) ((n << LPI2C_SAMR_ADDR0_SHIFT) & LPI2C_SAMR_ADDR0_MASK)
#define LPI2C_SAMR_ADDR0(n) (((n) << LPI2C_SAMR_ADDR0_SHIFT) & LPI2C_SAMR_ADDR0_MASK)
/* Bits 16-11 Reserved */
#define LPI2C_SAMR_ADDR1_SHIFT (17)
#define LPI2C_SAMR_ADDR1_MASK (0x3ff << LPI2C_SAMR_ADDR1_SHIFT) /* Address 1 Value */
#define LPI2C_SAMR_ADDR1(n) ((n << LPI2C_SAMR_ADDR1_SHIFT) & LPI2C_SAMR_ADDR1_MASK)
#define LPI2C_SAMR_ADDR1(n) (((n) << LPI2C_SAMR_ADDR1_SHIFT) & LPI2C_SAMR_ADDR1_MASK)
/* Bits 31-27 Reserved */
/* LPI2C Slave Address Status Register */
@ -606,14 +606,14 @@
#define LPI2C_STDR_DATA_SHIFT (0)
#define LPI2C_STDR_DATA_MASK (0xff << LPI2C_STDR_DATA_SHIFT) /* Transmit Data */
#define LPI2C_STDR_DATA(n) ((n << LPI2C_STDR_DATA_SHIFT) & LPI2C_STDR_DATA_MASK)
#define LPI2C_STDR_DATA(n) (((n) << LPI2C_STDR_DATA_SHIFT) & LPI2C_STDR_DATA_MASK)
/* Bits 31-8 Reserved */
/* LPI2C Slave Receive Data Register */
#define LPI2C_SRDR_DATA_SHIFT (0)
#define LPI2C_SRDR_DATA_MASK (0xff << LPI2C_SRDR_DATA_SHIFT) /* Receive Data */
#define LPI2C_SRDR_DATA(n) ((n << LPI2C_SRDR_DATA_SHIFT) & LPI2C_SRDR_DATA_MASK)
#define LPI2C_SRDR_DATA(n) (((n) << LPI2C_SRDR_DATA_SHIFT) & LPI2C_SRDR_DATA_MASK)
/* Bits 13-8 Reserved */
#define LPI2C_STAR_SOF (1 << 14) /* RX Empty */
#define LPI2C_STAR_RXEMPTY (1 << 15) /* Start Of Frame */