Change *err() to either info() or err(ERROR:..), depending upon if an error has occurred.
This commit is contained in:
Gregory Nutt
parent
088e9920a8
commit
f35086dbf7
@ -143,18 +143,15 @@ void up_irqinitialize(void)
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/* And finally, enable interrupts */
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#if 1
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#define REG(x) (*(volatile uint32_t *)(x))
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_llerr("\n=============================================================\n");
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_llerr("TM CNTL=%08x INTRS=%08x MASK=%08x LOAD=%08x COUNT=%08x M1=%08x\n",
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REG(0x98400030), REG(0x98400034), REG(0x98400038), REG(0x98400004),
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REG(0x98400000), REG(0x98400008));
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_llerr("IRQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n",
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REG(0x98800014), REG(0x98800004), REG(0x9880000C), REG(0x98800010));
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_llerr("FIQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n",
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REG(0x98800034), REG(0x98800024), REG(0x9880002C), REG(0x98800020));
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_llerr("=============================================================\n");
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#endif
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irqinfo("TM CNTL=%08x INTRS=%08x MASK=%08x LOAD=%08x COUNT=%08x M1=%08x\n",
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getreg32(0x98400030), getreg32(0x98400034), getreg32(0x98400038),
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getreg32(0x98400004), getreg32(0x98400000), getreg32(0x98400008));
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irqinfo("IRQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n",
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getreg32(0x98800014), getreg32(0x98800004), getreg32(0x9880000C),
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getreg32(0x98800010));
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irqinfo("FIQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n",
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getreg32(0x98800034), getreg32(0x98800024), getreg32(0x9880002C),
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getreg32(0x98800020));
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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up_irq_restore(SVC_MODE | PSR_F_BIT);
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@ -49,14 +49,13 @@
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#include "chip.h"
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#include "nuc_gpio.h"
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#ifdef CONFIG_DEBUG_FEATURES
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#ifdef CONFIG_DEBUG_GPIO_INFO
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* Port letters for prettier debug output */
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#ifdef CONFIG_DEBUG_FEATURES
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static const char g_portchar[NUC_GPIO_NPORTS] =
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{
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#if NUC_GPIO_NPORTS > 9
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@ -83,15 +82,6 @@ static const char g_portchar[NUC_GPIO_NPORTS] =
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# error "Bad number of GPIOs"
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#endif
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};
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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@ -124,22 +114,22 @@ void nuc_dumpgpio(gpio_cfgset_t pinset, const char *msg)
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flags = enter_critical_section();
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_llerr("GPIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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_llerr(" PMD: %08x OFFD: %08x DOUT: %08x DMASK: %08x\n",
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getreg32(base + NUC_GPIO_PMD_OFFSET),
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getreg32(base + NUC_GPIO_OFFD_OFFSET),
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getreg32(base + NUC_GPIO_DOUT_OFFSET),
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getreg32(base + NUC_GPIO_DMASK_OFFSET));
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_llerr(" PIN: %08x DBEN: %08x IMD: %08x IEN: %08x\n",
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getreg32(base + NUC_GPIO_PIN_OFFSET),
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getreg32(base + NUC_GPIO_DBEN_OFFSET),
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getreg32(base + NUC_GPIO_IMD_OFFSET),
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getreg32(base + NUC_GPIO_IEN_OFFSET));
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_llerr(" ISRC: %08x\n",
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getreg32(base + NUC_GPIO_ISRC_OFFSET));
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gpioinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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gpioinfo(" PMD: %08x OFFD: %08x DOUT: %08x DMASK: %08x\n",
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getreg32(base + NUC_GPIO_PMD_OFFSET),
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getreg32(base + NUC_GPIO_OFFD_OFFSET),
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getreg32(base + NUC_GPIO_DOUT_OFFSET),
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getreg32(base + NUC_GPIO_DMASK_OFFSET));
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gpioinfo(" PIN: %08x DBEN: %08x IMD: %08x IEN: %08x\n",
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getreg32(base + NUC_GPIO_PIN_OFFSET),
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getreg32(base + NUC_GPIO_DBEN_OFFSET),
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getreg32(base + NUC_GPIO_IMD_OFFSET),
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getreg32(base + NUC_GPIO_IEN_OFFSET));
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gpioinfo(" ISRC: %08x\n",
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getreg32(base + NUC_GPIO_ISRC_OFFSET));
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leave_critical_section(flags);
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}
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#endif /* CONFIG_DEBUG_FEATURES */
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#endif /* CONFIG_DEBUG_GPIO_INFO */
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@ -1128,11 +1128,11 @@ config SAM34_SPI_DMADEBUG
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config SAM34_SPI_REGDEBUG
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bool "SPI Register level debug"
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depends on DEBUG_FEATURES
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depends on DEBUG_SPI_INFO
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default n
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---help---
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Output detailed register-level SPI device debug information.
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Requires also CONFIG_DEBUG_FEATURES.
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Requires also CONFIG_SPI_INFO.
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endmenu # AT91SAM3/4 SPI device driver options
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endif # SAM34_SPI0 || SAM34_SPI1
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@ -1336,9 +1336,9 @@ config SAM34_EMAC_PHYSR_100FD
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config SAM34_EMAC_REGDEBUG
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bool "Register-Level Debug"
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default n
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depends on DEBUG_FEATURES
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depends on DEBUG_NET_INFO
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---help---
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Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES.
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Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO.
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config SAM34_EMAC_ISETH0
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bool
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@ -1400,7 +1400,7 @@ menu "AT91SAM3/4 USB Full Speed Device Controller driver (DCD) options"
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config SAM34_UDP_REGDEBUG
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bool "Enable low-level UDP register debug"
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default n
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depends on DEBUG_FEATURES
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depends on DEBUG_USB_INFO
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endmenu # USB Full Speed Device Controller driver (DCD) options
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@ -1415,7 +1415,7 @@ menu "AT91SAM3/4 Timer/Counter options"
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config SAM34_TC_REGDEBUG
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bool "Enable low-level timer/counter register debug"
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default n
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depends on DEBUG_FEATURES
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depends on DEBUG_TIMER_INFO
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endmenu # USB Full Speed Device Controller driver (DCD) options
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@ -77,6 +77,10 @@
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef CONFIG_DEBUG_TIMER_INFO
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# undef CONFIG_SAM34_TC_REGDEBUG
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -390,21 +394,21 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg)
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uintptr_t base;
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base = chan->base;
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_llerr("TC%d [%08x]: %s\n", chan->chan, (int)base, msg);
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_llerr(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n",
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getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET),
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getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET));
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tmrinfo("TC%d [%08x]: %s\n", chan->chan, (int)base, msg);
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tmrinfo(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n",
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getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET),
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getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET));
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base = chan->base;
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_llerr("TC%d Channel %d [%08x]: %s\n", chan->chan, chan->chan, (int)base, msg);
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_llerr(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n",
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getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET),
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getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET));
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_llerr(" RA: %08x RB: %08x RC: %08x SR: %08x\n",
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getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET),
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getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_SR_OFFSET));
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_llerr(" IMR: %08x\n",
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getreg32(base+SAM_TC_IMR_OFFSET));
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tmrinfo("TC%d Channel %d [%08x]: %s\n", chan->chan, chan->chan, (int)base, msg);
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tmrinfo(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n",
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getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET),
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getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET));
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tmrinfo(" RA: %08x RB: %08x RC: %08x SR: %08x\n",
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getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET),
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getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_SR_OFFSET));
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tmrinfo(" IMR: %08x\n",
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getreg32(base+SAM_TC_IMR_OFFSET));
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}
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#endif
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@ -447,7 +451,7 @@ static bool sam_checkreg(struct sam_chan_s *chan, bool wr, uint32_t regaddr,
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{
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/* Yes... show how many times we did it */
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_llerr("...[Repeats %d times]...\n", chan->ntimes);
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tmrinfo("...[Repeats %d times]...\n", chan->ntimes);
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}
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/* Save information about the new access */
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@ -481,7 +485,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan,
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#ifdef CONFIG_SAM34_TC_REGDEBUG
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if (sam_checkreg(chan, false, regaddr, regval))
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{
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_llerr("%08x->%08x\n", regaddr, regval);
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tmrinfo("%08x->%08x\n", regaddr, regval);
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}
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#endif
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@ -504,7 +508,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset,
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#ifdef CONFIG_SAM34_TC_REGDEBUG
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if (sam_checkreg(chan, true, regaddr, regval))
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{
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_llerr("%08x<-%08x\n", regaddr, regval);
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tmrinfo("%08x<-%08x\n", regaddr, regval);
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}
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#endif
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@ -1730,7 +1730,7 @@ void sam_dmastop(DMA_HANDLE handle)
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_DMA
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#ifdef CONFIG_DEBUG_DMA_INFO
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void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
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{
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struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
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@ -1761,7 +1761,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
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regs->cfg = getreg32(dmach->base + SAM_DMACHAN_CFG_OFFSET);
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leave_critical_section(flags);
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}
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#endif /* CONFIG_DEBUG_DMA */
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#endif /* CONFIG_DEBUG_DMA_INFO */
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/****************************************************************************
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* Name: sam_dmadump
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@ -1774,28 +1774,28 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_DMA
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#ifdef CONFIG_DEBUG_DMA_INFO
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void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
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const char *msg)
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{
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struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
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dmaerr("%s\n", msg);
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dmaerr(" DMA Global Registers:\n");
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dmaerr(" GCFG[%08x]: %08x\n", SAM_DMAC_GCFG, regs->gcfg);
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dmaerr(" EN[%08x]: %08x\n", SAM_DMAC_EN, regs->en);
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dmaerr(" SREQ[%08x]: %08x\n", SAM_DMAC_SREQ, regs->sreq);
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dmaerr(" CREQ[%08x]: %08x\n", SAM_DMAC_CREQ, regs->creq);
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dmaerr(" LAST[%08x]: %08x\n", SAM_DMAC_LAST, regs->last);
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dmaerr(" EBCIMR[%08x]: %08x\n", SAM_DMAC_EBCIMR, regs->ebcimr);
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dmaerr(" CHSR[%08x]: %08x\n", SAM_DMAC_CHSR, regs->chsr);
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dmaerr(" DMA Channel Registers:\n");
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dmaerr(" SADDR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_SADDR_OFFSET, regs->saddr);
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dmaerr(" DADDR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_DADDR_OFFSET, regs->daddr);
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dmaerr(" DSCR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_DSCR_OFFSET, regs->dscr);
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dmaerr(" CTRLA[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CTRLA_OFFSET, regs->ctrla);
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dmaerr(" CTRLB[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CTRLB_OFFSET, regs->ctrlb);
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dmaerr(" CFG[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CFG_OFFSET, regs->cfg);
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dmainfo("%s\n", msg);
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dmainfo(" DMA Global Registers:\n");
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dmainfo(" GCFG[%08x]: %08x\n", SAM_DMAC_GCFG, regs->gcfg);
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dmainfo(" EN[%08x]: %08x\n", SAM_DMAC_EN, regs->en);
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dmainfo(" SREQ[%08x]: %08x\n", SAM_DMAC_SREQ, regs->sreq);
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dmainfo(" CREQ[%08x]: %08x\n", SAM_DMAC_CREQ, regs->creq);
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dmainfo(" LAST[%08x]: %08x\n", SAM_DMAC_LAST, regs->last);
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dmainfo(" EBCIMR[%08x]: %08x\n", SAM_DMAC_EBCIMR, regs->ebcimr);
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dmainfo(" CHSR[%08x]: %08x\n", SAM_DMAC_CHSR, regs->chsr);
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dmainfo(" DMA Channel Registers:\n");
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dmainfo(" SADDR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_SADDR_OFFSET, regs->saddr);
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dmainfo(" DADDR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_DADDR_OFFSET, regs->daddr);
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dmainfo(" DSCR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_DSCR_OFFSET, regs->dscr);
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dmainfo(" CTRLA[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CTRLA_OFFSET, regs->ctrla);
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dmainfo(" CTRLB[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CTRLB_OFFSET, regs->ctrlb);
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dmainfo(" CFG[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CFG_OFFSET, regs->cfg);
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}
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#endif /* CONFIG_DEBUG_DMA */
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#endif /* CONFIG_DEBUG_DMA_INFO */
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#endif /* CONFIG_SAM34_DMAC0 */
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@ -50,12 +50,6 @@
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* Pre-processor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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#ifndef CONFIG_DEBUG_FEATURES
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# undef CONFIG_DEBUG_DMA
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#endif
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/* DMA ******************************************************************************/
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/* Flags used to characterize the desired DMA channel. The naming convention is that
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@ -125,7 +119,7 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
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/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
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#ifdef CONFIG_DEBUG_DMA
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#ifdef CONFIG_DEBUG_DMA_INFO
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struct sam_dmaregs_s
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{
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/* Global Registers */
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@ -285,7 +279,7 @@ void sam_dmastop(DMA_HANDLE handle);
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_DMA
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#ifdef CONFIG_DEBUG_DMA_INFO
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void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs);
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#else
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# define sam_dmasample(handle,regs)
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@ -299,7 +293,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs);
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_DMA
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#ifdef CONFIG_DEBUG_DMA_INFO
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void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
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const char *msg);
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#else
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@ -231,7 +231,7 @@
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* enabled.
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*/
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#ifndef CONFIG_DEBUG_FEATURES
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#ifndef CONFIG_DEBUG_NET_INFO
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# undef CONFIG_SAM34_EMAC_REGDEBUG
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#endif
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@ -490,7 +490,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval,
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{
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/* Yes... show how many times we did it */
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_llerr("...[Repeats %d times]...\n", priv->ntimes);
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ninfo("...[Repeats %d times]...\n", priv->ntimes);
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}
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/* Save information about the new access */
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@ -522,7 +522,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t address)
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if (sam_checkreg(priv, false, regval, address))
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{
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_llerr("%08x->%08x\n", address, regval);
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ninfo("%08x->%08x\n", address, regval);
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}
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return regval;
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@ -543,7 +543,7 @@ static void sam_putreg(struct sam_emac_s *priv, uintptr_t address,
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{
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if (sam_checkreg(priv, true, regval, address))
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{
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_llerr("%08x<-%08x\n", address, regval);
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ninfo("%08x<-%08x\n", address, regval);
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}
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putreg32(regval, address);
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@ -636,7 +636,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
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priv->txdesc = (struct emac_txdesc_s *)kmm_memalign(8, allocsize);
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if (!priv->txdesc)
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{
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nllerr("ERROR: Failed to allocate TX descriptors\n");
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nerr("ERROR: Failed to allocate TX descriptors\n");
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return -ENOMEM;
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}
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@ -646,7 +646,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
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priv->rxdesc = (struct emac_rxdesc_s *)kmm_memalign(8, allocsize);
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if (!priv->rxdesc)
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{
|
||||
nllerr("ERROR: Failed to allocate RX descriptors\n");
|
||||
nerr("ERROR: Failed to allocate RX descriptors\n");
|
||||
sam_buffer_free(priv);
|
||||
return -ENOMEM;
|
||||
}
|
||||
@ -657,7 +657,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
|
||||
priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize);
|
||||
if (!priv->txbuffer)
|
||||
{
|
||||
nllerr("ERROR: Failed to allocate TX buffer\n");
|
||||
nerr("ERROR: Failed to allocate TX buffer\n");
|
||||
sam_buffer_free(priv);
|
||||
return -ENOMEM;
|
||||
}
|
||||
@ -666,7 +666,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
|
||||
priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize);
|
||||
if (!priv->rxbuffer)
|
||||
{
|
||||
nllerr("ERROR: Failed to allocate RX buffer\n");
|
||||
nerr("ERROR: Failed to allocate RX buffer\n");
|
||||
sam_buffer_free(priv);
|
||||
return -ENOMEM;
|
||||
}
|
||||
@ -1207,7 +1207,7 @@ static void sam_receive(struct sam_emac_s *priv)
|
||||
|
||||
if (dev->d_len > CONFIG_NET_ETH_MTU)
|
||||
{
|
||||
nllerr("DROPPED: Too big: %d\n", dev->d_len);
|
||||
nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
|
||||
continue;
|
||||
}
|
||||
|
||||
@ -1317,7 +1317,7 @@ static void sam_receive(struct sam_emac_s *priv)
|
||||
else
|
||||
#endif
|
||||
{
|
||||
nllerr("DROPPED: Unknown type: %04x\n", BUF->type);
|
||||
nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1578,7 +1578,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
|
||||
|
||||
if ((pending & EMAC_INT_PFNZ) != 0)
|
||||
{
|
||||
nllerr("Pause frame received\n");
|
||||
nllwarn("WARNING: Pause frame received\n");
|
||||
}
|
||||
|
||||
/* Check for Pause Time Zero (PTZ)
|
||||
@ -1588,7 +1588,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
|
||||
|
||||
if ((pending & EMAC_INT_PTZ) != 0)
|
||||
{
|
||||
nllerr("Pause TO!\n");
|
||||
nllwarn("WARNING: Pause TO!\n");
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@ -1725,7 +1725,7 @@ static int sam_emac_interrupt(int irq, void *context)
|
||||
|
||||
static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv)
|
||||
{
|
||||
nllerr("Timeout!\n");
|
||||
nllerr("ERROR: Timeout!\n");
|
||||
|
||||
/* Then reset the hardware. Just take the interface down, then back
|
||||
* up again.
|
||||
@ -1956,13 +1956,13 @@ static int sam_ifup(struct net_driver_s *dev)
|
||||
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
|
||||
int ret;
|
||||
|
||||
nllerr("Bringing up: %d.%d.%d.%d\n",
|
||||
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
|
||||
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
|
||||
ninfo("Bringing up: %d.%d.%d.%d\n",
|
||||
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
|
||||
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
|
||||
|
||||
/* Configure the EMAC interface for normal operation. */
|
||||
|
||||
nllinfo("Initialize the EMAC\n");
|
||||
ninfo("Initialize the EMAC\n");
|
||||
sam_emac_configure(priv);
|
||||
|
||||
/* Set the MAC address (should have been configured while we were down) */
|
||||
@ -1980,7 +1980,7 @@ static int sam_ifup(struct net_driver_s *dev)
|
||||
ret = sam_phyinit(priv);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: sam_phyinit failed: %d\n", ret);
|
||||
nerr("ERROR: sam_phyinit failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -1989,16 +1989,16 @@ static int sam_ifup(struct net_driver_s *dev)
|
||||
ret = sam_autonegotiate(priv);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: sam_autonegotiate failed: %d\n", ret);
|
||||
nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
while (sam_linkup(priv) == 0);
|
||||
nllinfo("Link detected \n");
|
||||
ninfo("Link detected \n");
|
||||
|
||||
/* Enable normal MAC operation */
|
||||
|
||||
nllinfo("Enable normal operation\n");
|
||||
ninfo("Enable normal operation\n");
|
||||
|
||||
/* Set and activate a timer process */
|
||||
|
||||
@ -2032,7 +2032,7 @@ static int sam_ifdown(struct net_driver_s *dev)
|
||||
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
|
||||
irqstate_t flags;
|
||||
|
||||
nllerr("Taking the network down\n");
|
||||
ninfo("Taking the network down\n");
|
||||
|
||||
/* Disable the EMAC interrupt */
|
||||
|
||||
@ -2077,7 +2077,7 @@ static int sam_ifdown(struct net_driver_s *dev)
|
||||
|
||||
static inline void sam_txavail_process(FAR struct sam_emac_s *priv)
|
||||
{
|
||||
nllinfo("ifup: %d\n", priv->ifup);
|
||||
ninfo("ifup: %d\n", priv->ifup);
|
||||
|
||||
/* Ignore the notification if the interface is not yet up */
|
||||
|
||||
@ -2331,8 +2331,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
|
||||
unsigned int bit;
|
||||
|
||||
UNUSED(priv);
|
||||
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
|
||||
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
|
||||
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
|
||||
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
|
||||
|
||||
/* Calculate the 6-bit has table index */
|
||||
|
||||
@ -2405,8 +2405,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
|
||||
unsigned int bit;
|
||||
|
||||
UNUSED(priv);
|
||||
nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
|
||||
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
|
||||
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
|
||||
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
|
||||
|
||||
/* Calculate the 6-bit has table index */
|
||||
|
||||
@ -2601,21 +2601,21 @@ static void sam_phydump(struct sam_emac_s *priv)
|
||||
sam_putreg(priv, SAM_EMAC_NCR, regval);
|
||||
|
||||
#ifdef CONFIG_SAM34_EMAC_RMII
|
||||
nllinfo("RMII Registers (Address %02x)\n", priv->phyaddr);
|
||||
ninfo("RMII Registers (Address %02x)\n", priv->phyaddr);
|
||||
#else /* defined(CONFIG_SAM34_EMAC_MII) */
|
||||
nllinfo("MII Registers (Address %02x)\n", priv->phyaddr);
|
||||
ninfo("MII Registers (Address %02x)\n", priv->phyaddr);
|
||||
#endif
|
||||
|
||||
sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
|
||||
nllinfo(" MCR: %04x\n", phyval);
|
||||
ninfo(" MCR: %04x\n", phyval);
|
||||
sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
|
||||
nllinfo(" MSR: %04x\n", phyval);
|
||||
ninfo(" MSR: %04x\n", phyval);
|
||||
sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
|
||||
nllinfo(" ADVERTISE: %04x\n", phyval);
|
||||
ninfo(" ADVERTISE: %04x\n", phyval);
|
||||
sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
|
||||
nllinfo(" LPR: %04x\n", phyval);
|
||||
ninfo(" LPR: %04x\n", phyval);
|
||||
sam_phyread(priv, priv->phyaddr, CONFIG_SAM34_EMAC_PHYSR, &phyval);
|
||||
nllinfo(" PHYSR: %04x\n", phyval);
|
||||
ninfo(" PHYSR: %04x\n", phyval);
|
||||
|
||||
/* Disable management port */
|
||||
|
||||
@ -2738,7 +2738,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
|
||||
int timeout;
|
||||
int ret;
|
||||
|
||||
nllinfo(" sam_phyreset\n");
|
||||
ninfo(" sam_phyreset\n");
|
||||
|
||||
/* Enable management port */
|
||||
|
||||
@ -2751,7 +2751,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
|
||||
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, MII_MCR_RESET);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: sam_phywrite failed: %d\n", ret);
|
||||
nerr("ERROR: sam_phywrite failed: %d\n", ret);
|
||||
}
|
||||
|
||||
/* Wait for the PHY reset to complete */
|
||||
@ -2763,7 +2763,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
|
||||
int result = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
|
||||
if (result < 0)
|
||||
{
|
||||
nllerr("ERROR: Failed to read the MCR register: %d\n", ret);
|
||||
nerr("ERROR: Failed to read the MCR register: %d\n", ret);
|
||||
ret = result;
|
||||
}
|
||||
else if ((mcr & MII_MCR_RESET) == 0)
|
||||
@ -2805,7 +2805,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
|
||||
unsigned int offset;
|
||||
int ret = -ESRCH;
|
||||
|
||||
nllinfo("Find a valid PHY address\n");
|
||||
ninfo("Find a valid PHY address\n");
|
||||
|
||||
/* Enable management port */
|
||||
|
||||
@ -2828,8 +2828,8 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
|
||||
|
||||
else
|
||||
{
|
||||
nllerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
|
||||
candidate, ret);
|
||||
nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
|
||||
candidate, ret);
|
||||
|
||||
for (offset = 0; offset < 32; offset++)
|
||||
{
|
||||
@ -2850,10 +2850,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
|
||||
|
||||
if (ret == OK)
|
||||
{
|
||||
nllinfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
|
||||
ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
|
||||
*phyaddr = candidate;
|
||||
sam_phyread(priv, candidate, CONFIG_SAM34_EMAC_PHYSR, &phyval);
|
||||
nllinfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
|
||||
ninfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
|
||||
}
|
||||
|
||||
/* Disable management port */
|
||||
@ -2894,7 +2894,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
|
||||
ret = sam_phywait(priv);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: sam_phywait failed: %d\n", ret);
|
||||
nerr("ERROR: sam_phywait failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -2918,7 +2918,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
|
||||
ret = sam_phywait(priv);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: sam_phywait failed: %d\n", ret);
|
||||
nerr("ERROR: sam_phywait failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -2958,7 +2958,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
|
||||
ret = sam_phywait(priv);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: sam_phywait failed: %d\n", ret);
|
||||
nerr("ERROR: sam_phywait failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -2982,7 +2982,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
|
||||
ret = sam_phywait(priv);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: sam_phywait failed: %d\n", ret);
|
||||
nerr("ERROR: sam_phywait failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -3026,32 +3026,32 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
|
||||
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID1, &phyid1);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: Failed to read PHYID1\n");
|
||||
nerr("ERROR: Failed to read PHYID1\n");
|
||||
goto errout;
|
||||
}
|
||||
|
||||
nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
|
||||
ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
|
||||
|
||||
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: Failed to read PHYID2\n");
|
||||
nerr("ERROR: Failed to read PHYID2\n");
|
||||
goto errout;
|
||||
}
|
||||
|
||||
nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
|
||||
ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
|
||||
|
||||
if (phyid1 == MII_OUI_MSB &&
|
||||
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) == MII_OUI_LSB)
|
||||
{
|
||||
nllinfo(" Vendor Model Number: %04x\n",
|
||||
(phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
|
||||
nllinfo(" Model Revision Number: %04x\n",
|
||||
(phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
|
||||
ninfo(" Vendor Model Number: %04x\n",
|
||||
(phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
|
||||
ninfo(" Model Revision Number: %04x\n",
|
||||
(phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
|
||||
}
|
||||
else
|
||||
{
|
||||
nllerr("ERROR: PHY not recognized\n");
|
||||
nerr("ERROR: PHY not recognized\n");
|
||||
}
|
||||
|
||||
/* Setup control register */
|
||||
@ -3059,7 +3059,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
|
||||
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: Failed to read MCR\n");
|
||||
nerr("ERROR: Failed to read MCR\n");
|
||||
goto errout;
|
||||
}
|
||||
|
||||
@ -3070,7 +3070,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
|
||||
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: Failed to write MCR\n");
|
||||
nerr("ERROR: Failed to write MCR\n");
|
||||
goto errout;
|
||||
}
|
||||
|
||||
@ -3085,7 +3085,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
|
||||
ret = sam_phywrite(priv, priv->phyaddr, MII_ADVERTISE, advertise);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: Failed to write ANAR\n");
|
||||
nerr("ERROR: Failed to write ANAR\n");
|
||||
goto errout;
|
||||
}
|
||||
|
||||
@ -3094,7 +3094,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
|
||||
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: Failed to read MCR\n");
|
||||
nerr("ERROR: Failed to read MCR\n");
|
||||
goto errout;
|
||||
}
|
||||
|
||||
@ -3102,7 +3102,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
|
||||
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: Failed to write MCR\n");
|
||||
nerr("ERROR: Failed to write MCR\n");
|
||||
goto errout;
|
||||
}
|
||||
|
||||
@ -3114,11 +3114,11 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
|
||||
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: Failed to write MCR\n");
|
||||
nerr("ERROR: Failed to write MCR\n");
|
||||
goto errout;
|
||||
}
|
||||
|
||||
nllinfo(" MCR: %04x\n", mcr);
|
||||
ninfo(" MCR: %04x\n", mcr);
|
||||
|
||||
/* Check AutoNegotiate complete */
|
||||
|
||||
@ -3128,7 +3128,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
|
||||
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: Failed to read MSR\n");
|
||||
nerr("ERROR: Failed to read MSR\n");
|
||||
goto errout;
|
||||
}
|
||||
|
||||
@ -3138,7 +3138,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
|
||||
{
|
||||
/* Yes.. break out of the loop */
|
||||
|
||||
nllinfo("AutoNegotiate complete\n");
|
||||
ninfo("AutoNegotiate complete\n");
|
||||
break;
|
||||
}
|
||||
|
||||
@ -3146,7 +3146,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
|
||||
|
||||
if (++timeout >= PHY_RETRY_MAX)
|
||||
{
|
||||
nllerr("ERROR: TimeOut\n");
|
||||
nerr("ERROR: TimeOut\n");
|
||||
sam_phydump(priv);
|
||||
ret = -ETIMEDOUT;
|
||||
goto errout;
|
||||
@ -3158,7 +3158,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
|
||||
ret = sam_phyread(priv, priv->phyaddr, MII_LPA, &lpa);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: Failed to read ANLPAR\n");
|
||||
nerr("ERROR: Failed to read ANLPAR\n");
|
||||
goto errout;
|
||||
}
|
||||
|
||||
@ -3244,13 +3244,13 @@ static bool sam_linkup(struct sam_emac_s *priv)
|
||||
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: Failed to read MSR: %d\n", ret);
|
||||
nerr("ERROR: Failed to read MSR: %d\n", ret);
|
||||
goto errout;
|
||||
}
|
||||
|
||||
if ((msr & MII_MSR_LINKSTATUS) == 0)
|
||||
{
|
||||
nllerr("ERROR: MSR LinkStatus: %04x\n", msr);
|
||||
nerr("ERROR: MSR LinkStatus: %04x\n", msr);
|
||||
goto errout;
|
||||
}
|
||||
|
||||
@ -3259,7 +3259,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
|
||||
ret = sam_phyread(priv, priv->phyaddr, CONFIG_SAM34_EMAC_PHYSR, &physr);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: Failed to read PHYSR: %d\n", ret);
|
||||
nerr("ERROR: Failed to read PHYSR: %d\n", ret);
|
||||
goto errout;
|
||||
}
|
||||
|
||||
@ -3297,7 +3297,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
|
||||
|
||||
/* Start the EMAC transfers */
|
||||
|
||||
nllinfo("Link is up\n");
|
||||
ninfo("Link is up\n");
|
||||
linkup = true;
|
||||
|
||||
errout:
|
||||
@ -3354,7 +3354,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
|
||||
ret = sam_phyfind(priv, &priv->phyaddr);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: sam_phyfind failed: %d\n", ret);
|
||||
nerr("ERROR: sam_phyfind failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -3598,11 +3598,11 @@ static void sam_macaddress(struct sam_emac_s *priv)
|
||||
struct net_driver_s *dev = &priv->dev;
|
||||
uint32_t regval;
|
||||
|
||||
nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
|
||||
dev->d_ifname,
|
||||
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
|
||||
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
|
||||
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
|
||||
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
|
||||
dev->d_ifname,
|
||||
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
|
||||
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
|
||||
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
|
||||
|
||||
/* Set the MAC address */
|
||||
|
||||
@ -3710,7 +3710,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
nllinfo("Entry\n");
|
||||
ninfo("Entry\n");
|
||||
|
||||
/* Enable clocking to the EMAC peripheral */
|
||||
|
||||
@ -3823,14 +3823,14 @@ void up_netinitialize(void)
|
||||
priv->txpoll = wd_create();
|
||||
if (!priv->txpoll)
|
||||
{
|
||||
nllerr("ERROR: Failed to create periodic poll timer\n");
|
||||
nerr("ERROR: Failed to create periodic poll timer\n");
|
||||
return;
|
||||
}
|
||||
|
||||
priv->txtimeout = wd_create(); /* Create TX timeout timer */
|
||||
if (!priv->txtimeout)
|
||||
{
|
||||
nllerr("ERROR: Failed to create periodic poll timer\n");
|
||||
nerr("ERROR: Failed to create periodic poll timer\n");
|
||||
goto errout_with_txpoll;
|
||||
}
|
||||
|
||||
@ -3843,7 +3843,7 @@ void up_netinitialize(void)
|
||||
ret = sam_buffer_initialize(priv);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
|
||||
nerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
|
||||
goto errout_with_txtimeout;
|
||||
}
|
||||
|
||||
@ -3854,7 +3854,7 @@ void up_netinitialize(void)
|
||||
ret = irq_attach(SAM_IRQ_EMAC, sam_emac_interrupt);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC);
|
||||
nerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC);
|
||||
goto errout_with_buffers;
|
||||
}
|
||||
|
||||
@ -3867,7 +3867,7 @@ void up_netinitialize(void)
|
||||
ret = sam_ifdown(&priv->dev);
|
||||
if (ret < 0)
|
||||
{
|
||||
nllerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
|
||||
nerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
|
||||
goto errout_with_buffers;
|
||||
}
|
||||
|
||||
@ -3879,7 +3879,7 @@ void up_netinitialize(void)
|
||||
return;
|
||||
}
|
||||
|
||||
nllerr("ERROR: netdev_register() failed: %d\n", ret);
|
||||
nerr("ERROR: netdev_register() failed: %d\n", ret);
|
||||
|
||||
errout_with_buffers:
|
||||
sam_buffer_free(priv);
|
||||
|
||||
@ -104,7 +104,7 @@
|
||||
|
||||
#define SAM34_HSMCI_PRIO NVIC_SYSH_PRIORITY_DEFAULT
|
||||
|
||||
#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_INFO)
|
||||
#ifndef CONFIG_DEBUG_MEMCARD_INFO
|
||||
# undef CONFIG_SAM34_HSMCI_CMDDEBUG
|
||||
# undef CONFIG_SAM34_HSMCI_XFRDEBUG
|
||||
#endif
|
||||
@ -831,38 +831,38 @@ static void sam_hsmcisample(struct sam_hsmciregs_s *regs)
|
||||
#if defined(CONFIG_SAM34_HSMCI_XFRDEBUG) || defined(CONFIG_SAM34_HSMCI_CMDDEBUG)
|
||||
static void sam_hsmcidump(struct sam_hsmciregs_s *regs, const char *msg)
|
||||
{
|
||||
ferr("HSMCI Registers: %s\n", msg);
|
||||
ferr(" MR[%08x]: %08x\n", SAM_HSMCI_MR, regs->mr);
|
||||
ferr(" DTOR[%08x]: %08x\n", SAM_HSMCI_DTOR, regs->dtor);
|
||||
ferr(" SDCR[%08x]: %08x\n", SAM_HSMCI_SDCR, regs->sdcr);
|
||||
ferr(" ARGR[%08x]: %08x\n", SAM_HSMCI_ARGR, regs->argr);
|
||||
ferr(" BLKR[%08x]: %08x\n", SAM_HSMCI_BLKR, regs->blkr);
|
||||
ferr(" CSTOR[%08x]: %08x\n", SAM_HSMCI_CSTOR, regs->cstor);
|
||||
ferr(" RSPR0[%08x]: %08x\n", SAM_HSMCI_RSPR0, regs->rsp0);
|
||||
ferr(" RSPR1[%08x]: %08x\n", SAM_HSMCI_RSPR1, regs->rsp1);
|
||||
ferr(" RSPR2[%08x]: %08x\n", SAM_HSMCI_RSPR2, regs->rsp2);
|
||||
ferr(" RSPR3[%08x]: %08x\n", SAM_HSMCI_RSPR3, regs->rsp3);
|
||||
ferr(" SR[%08x]: %08x\n", SAM_HSMCI_SR, regs->sr);
|
||||
ferr(" IMR[%08x]: %08x\n", SAM_HSMCI_IMR, regs->imr);
|
||||
mcinfo("HSMCI Registers: %s\n", msg);
|
||||
mcinfo(" MR[%08x]: %08x\n", SAM_HSMCI_MR, regs->mr);
|
||||
mcinfo(" DTOR[%08x]: %08x\n", SAM_HSMCI_DTOR, regs->dtor);
|
||||
mcinfo(" SDCR[%08x]: %08x\n", SAM_HSMCI_SDCR, regs->sdcr);
|
||||
mcinfo(" ARGR[%08x]: %08x\n", SAM_HSMCI_ARGR, regs->argr);
|
||||
mcinfo(" BLKR[%08x]: %08x\n", SAM_HSMCI_BLKR, regs->blkr);
|
||||
mcinfo(" CSTOR[%08x]: %08x\n", SAM_HSMCI_CSTOR, regs->cstor);
|
||||
mcinfo(" RSPR0[%08x]: %08x\n", SAM_HSMCI_RSPR0, regs->rsp0);
|
||||
mcinfo(" RSPR1[%08x]: %08x\n", SAM_HSMCI_RSPR1, regs->rsp1);
|
||||
mcinfo(" RSPR2[%08x]: %08x\n", SAM_HSMCI_RSPR2, regs->rsp2);
|
||||
mcinfo(" RSPR3[%08x]: %08x\n", SAM_HSMCI_RSPR3, regs->rsp3);
|
||||
mcinfo(" SR[%08x]: %08x\n", SAM_HSMCI_SR, regs->sr);
|
||||
mcinfo(" IMR[%08x]: %08x\n", SAM_HSMCI_IMR, regs->imr);
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
ferr(" DMA[%08x]: %08x\n", SAM_HSMCI_DMA, regs->dma);
|
||||
mcinfo(" DMA[%08x]: %08x\n", SAM_HSMCI_DMA, regs->dma);
|
||||
#endif
|
||||
ferr(" CFG[%08x]: %08x\n", SAM_HSMCI_CFG, regs->cfg);
|
||||
ferr(" WPMR[%08x]: %08x\n", SAM_HSMCI_WPMR, regs->wpmr);
|
||||
ferr(" WPSR[%08x]: %08x\n", SAM_HSMCI_WPSR, regs->wpsr);
|
||||
mcinfo(" CFG[%08x]: %08x\n", SAM_HSMCI_CFG, regs->cfg);
|
||||
mcinfo(" WPMR[%08x]: %08x\n", SAM_HSMCI_WPMR, regs->wpmr);
|
||||
mcinfo(" WPSR[%08x]: %08x\n", SAM_HSMCI_WPSR, regs->wpsr);
|
||||
|
||||
#ifdef CONFIG_SAM34_PDCA
|
||||
ferr("HSMCI PDC Registers:\n");
|
||||
ferr(" RPR[%08x]: %08x\n", SAM_HSMCI_PDC_RPR, regs->pdc_rpr);
|
||||
ferr(" RCR[%08x]: %08x\n", SAM_HSMCI_PDC_RCR, regs->pdc_rcr);
|
||||
ferr(" TPR[%08x]: %08x\n", SAM_HSMCI_PDC_TPR, regs->pdc_tpr);
|
||||
ferr(" TCR[%08x]: %08x\n", SAM_HSMCI_PDC_TCR, regs->pdc_tcr);
|
||||
ferr(" RNPR[%08x]: %08x\n", SAM_HSMCI_PDC_RNPR, regs->pdc_rnpr);
|
||||
ferr(" RNCR[%08x]: %08x\n", SAM_HSMCI_PDC_RNCR, regs->pdc_rncr);
|
||||
ferr(" TNPR[%08x]: %08x\n", SAM_HSMCI_PDC_TNPR, regs->pdc_tnpr);
|
||||
ferr(" TNCR[%08x]: %08x\n", SAM_HSMCI_PDC_TNCR, regs->pdc_tncr);
|
||||
//ferr(" TCR[%08x]: %08x\n", SAM_HSMCI_PDC_PTCR, regs->pdc_ptcr);
|
||||
ferr(" PTSR[%08x]: %08x\n", SAM_HSMCI_PDC_PTSR, regs->pdc_ptsr);
|
||||
mcinfo("HSMCI PDC Registers:\n");
|
||||
mcinfo(" RPR[%08x]: %08x\n", SAM_HSMCI_PDC_RPR, regs->pdc_rpr);
|
||||
mcinfo(" RCR[%08x]: %08x\n", SAM_HSMCI_PDC_RCR, regs->pdc_rcr);
|
||||
mcinfo(" TPR[%08x]: %08x\n", SAM_HSMCI_PDC_TPR, regs->pdc_tpr);
|
||||
mcinfo(" TCR[%08x]: %08x\n", SAM_HSMCI_PDC_TCR, regs->pdc_tcr);
|
||||
mcinfo(" RNPR[%08x]: %08x\n", SAM_HSMCI_PDC_RNPR, regs->pdc_rnpr);
|
||||
mcinfo(" RNCR[%08x]: %08x\n", SAM_HSMCI_PDC_RNCR, regs->pdc_rncr);
|
||||
mcinfo(" TNPR[%08x]: %08x\n", SAM_HSMCI_PDC_TNPR, regs->pdc_tnpr);
|
||||
mcinfo(" TNCR[%08x]: %08x\n", SAM_HSMCI_PDC_TNCR, regs->pdc_tncr);
|
||||
//mcinfo(" TCR[%08x]: %08x\n", SAM_HSMCI_PDC_PTCR, regs->pdc_ptcr);
|
||||
mcinfo(" PTSR[%08x]: %08x\n", SAM_HSMCI_PDC_PTSR, regs->pdc_ptsr);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
@ -1083,7 +1083,7 @@ static void sam_eventtimeout(int argc, uint32_t arg)
|
||||
/* Yes.. wake up any waiting threads */
|
||||
|
||||
sam_endwait(priv, SDIOWAIT_TIMEOUT);
|
||||
fllerr("Timeout\n");
|
||||
mcllerr("ERROR: Timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
@ -1278,7 +1278,7 @@ static int sam_interrupt(int irq, void *context)
|
||||
{
|
||||
/* Yes.. Was it some kind of timeout error? */
|
||||
|
||||
fllerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
|
||||
mcllerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
|
||||
if ((pending & HSMCI_DATA_TIMEOUT_ERRORS) != 0)
|
||||
{
|
||||
/* Yes.. Terminate with a timeout. */
|
||||
@ -1320,7 +1320,7 @@ static int sam_interrupt(int irq, void *context)
|
||||
{
|
||||
/* Yes.. Was the error some kind of timeout? */
|
||||
|
||||
fllinfo("ERROR: events: %08x SR: %08x\n",
|
||||
mcllinfo("ERROR: events: %08x SR: %08x\n",
|
||||
priv->cmdrmask, enabled);
|
||||
|
||||
if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
|
||||
@ -1754,7 +1754,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev,
|
||||
|
||||
/* Write the fully decorated command to CMDR */
|
||||
|
||||
finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
|
||||
mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
|
||||
putreg32(regval, SAM_HSMCI_CMDR);
|
||||
sam_cmdsample1(SAMPLENDX_AFTER_CMDR);
|
||||
return OK;
|
||||
@ -1933,7 +1933,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
|
||||
{
|
||||
/* Yes.. Was the error some kind of timeout? */
|
||||
|
||||
ferr("ERROR: cmd: %08x events: %08x SR: %08x\n",
|
||||
mcerr("ERROR: cmd: %08x events: %08x SR: %08x\n",
|
||||
cmd, priv->cmdrmask, sr);
|
||||
|
||||
if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
|
||||
@ -1963,7 +1963,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
|
||||
}
|
||||
else if (--timeout <= 0)
|
||||
{
|
||||
ferr("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n",
|
||||
mcerr("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n",
|
||||
cmd, priv->cmdrmask, sr);
|
||||
|
||||
priv->wkupevent = SDIOWAIT_TIMEOUT;
|
||||
@ -2038,7 +2038,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev,
|
||||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
if (!rshort)
|
||||
{
|
||||
ferr("ERROR: rshort=NULL\n");
|
||||
mcerr("ERROR: rshort=NULL\n");
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
@ -2050,7 +2050,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev,
|
||||
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE &&
|
||||
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
|
||||
{
|
||||
ferr("ERROR: Wrong response CMD=%08x\n", cmd);
|
||||
mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
else
|
||||
@ -2100,7 +2100,7 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong
|
||||
|
||||
if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE)
|
||||
{
|
||||
ferr("ERROR: Wrong response CMD=%08x\n", cmd);
|
||||
mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
else
|
||||
@ -2282,7 +2282,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
|
||||
1, (uint32_t)priv);
|
||||
if (ret != OK)
|
||||
{
|
||||
ferr("ERROR: wd_start failed: %d\n", ret);
|
||||
mcerr("ERROR: wd_start failed: %d\n", ret);
|
||||
}
|
||||
}
|
||||
|
||||
@ -2348,7 +2348,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev,
|
||||
{
|
||||
struct sam_dev_s *priv = (struct sam_dev_s *)dev;
|
||||
|
||||
finfo("eventset: %02x\n", eventset);
|
||||
mcinfo("eventset: %02x\n", eventset);
|
||||
DEBUGASSERT(priv != NULL);
|
||||
|
||||
priv->cbevents = eventset;
|
||||
@ -2384,7 +2384,7 @@ static int sam_registercallback(FAR struct sdio_dev_s *dev,
|
||||
|
||||
/* Disable callbacks and register this callback and is argument */
|
||||
|
||||
finfo("Register %p(%p)\n", callback, arg);
|
||||
mcinfo("Register %p(%p)\n", callback, arg);
|
||||
DEBUGASSERT(priv != NULL);
|
||||
|
||||
priv->cbevents = 0;
|
||||
@ -2472,7 +2472,8 @@ static int sam_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
|
||||
|
||||
#ifdef CONFIG_SAM34_PDCA
|
||||
modifyreg32(SAM_HSMCI_MR, 0, HSMCI_MR_PDCMODE);
|
||||
ferr("SAM_HSMCI_MR = 0x%08X\n", getreg32(SAM_HSMCI_MR));
|
||||
mcinfo("SAM_HSMCI_MR = 0x%08X\n", getreg32(SAM_HSMCI_MR));
|
||||
|
||||
putreg32((uint32_t)buffer, SAM_HSMCI_PDC_RPR);
|
||||
putreg32(buflen/4, SAM_HSMCI_PDC_RCR);
|
||||
putreg32(PDC_PTCR_RXTEN, SAM_HSMCI_PDC_PTCR);
|
||||
@ -2541,7 +2542,8 @@ static int sam_dmasendsetup(FAR struct sdio_dev_s *dev,
|
||||
|
||||
#ifdef CONFIG_SAM34_PDCA
|
||||
modifyreg32(SAM_HSMCI_MR, 0, HSMCI_MR_PDCMODE);
|
||||
ferr("SAM_HSMCI_MR = 0x%08X\n", getreg32(SAM_HSMCI_MR));
|
||||
mcinfo("SAM_HSMCI_MR = 0x%08X\n", getreg32(SAM_HSMCI_MR));
|
||||
|
||||
putreg32((uint32_t)buffer, SAM_HSMCI_PDC_TPR);
|
||||
putreg32(buflen/4, SAM_HSMCI_PDC_TCR);
|
||||
putreg32(PDC_PTCR_TXTEN, SAM_HSMCI_PDC_PTCR);
|
||||
@ -2581,7 +2583,7 @@ static void sam_callback(void *arg)
|
||||
/* Is a callback registered? */
|
||||
|
||||
DEBUGASSERT(priv != NULL);
|
||||
finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
|
||||
mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
|
||||
priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
|
||||
|
||||
if (priv->callback)
|
||||
@ -2626,14 +2628,14 @@ static void sam_callback(void *arg)
|
||||
{
|
||||
/* Yes.. queue it */
|
||||
|
||||
fllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
|
||||
mcllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
|
||||
(void)work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No.. then just call the callback here */
|
||||
|
||||
finfo("Callback to %p(%p)\n", priv->callback, priv->cbarg);
|
||||
mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg);
|
||||
priv->callback(priv->cbarg);
|
||||
}
|
||||
}
|
||||
@ -2663,7 +2665,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
|
||||
|
||||
struct sam_dev_s *priv = &g_sdiodev;
|
||||
|
||||
ferr("slotno: %d\n", slotno);
|
||||
mcinfo("slotno: %d\n", slotno);
|
||||
|
||||
/* Initialize the HSMCI slot structure */
|
||||
|
||||
@ -2741,7 +2743,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
|
||||
priv->cdstatus &= ~SDIO_STATUS_PRESENT;
|
||||
}
|
||||
|
||||
fllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
|
||||
mcllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
|
||||
|
||||
/* Perform any requested callback if the status has changed */
|
||||
|
||||
@ -2786,7 +2788,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
|
||||
priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
|
||||
}
|
||||
|
||||
finfo("cdstatus: %02x\n", priv->cdstatus);
|
||||
mcinfo("cdstatus: %02x\n", priv->cdstatus);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
#endif /* CONFIG_SAM34_HSMCI */
|
||||
|
||||
@ -274,7 +274,7 @@ static int rtc_interrupt(int irq, void *context)
|
||||
ret = work_queue(LPWORK, &g_alarmwork, rtc_worker, NULL, 0);
|
||||
if (ret < 0)
|
||||
{
|
||||
rtcllerr("ERR0R: work_queue failed: %d\n", ret);
|
||||
rtcllerr("ERROR: work_queue failed: %d\n", ret);
|
||||
}
|
||||
|
||||
/* Disable any further alarm interrupts */
|
||||
|
||||
@ -74,18 +74,8 @@
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
/* Debug ********************************************************************/
|
||||
/* Non-standard debug that may be enabled just for testing the timer
|
||||
* driver. NOTE: that only llerr types are used so that the output is
|
||||
* immediately available.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_DEBUG_RTT
|
||||
# define rtterr _llerr
|
||||
# define rttinfo _llinfo
|
||||
#else
|
||||
# define rtterr(x...)
|
||||
# define rttinfo(x...)
|
||||
#ifndef CONFIG_DEBUG_TIMER_INFO
|
||||
# undef CONFIG_SAM34_RTT_REGDEBUG
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
@ -115,7 +105,7 @@ struct sam34_lowerhalf_s
|
||||
****************************************************************************/
|
||||
/* Register operations ******************************************************/
|
||||
|
||||
#if defined(CONFIG_SAM34_RTT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
|
||||
#ifdef CONFIG_SAM34_RTT_REGDEBUG
|
||||
static uint32_t sam34_getreg(uint32_t addr);
|
||||
static void sam34_putreg(uint32_t val, uint32_t addr);
|
||||
#else
|
||||
@ -193,7 +183,7 @@ static inline uint32_t sam34_readvr(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SAM34_RTT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
|
||||
#ifdef CONFIG_SAM34_RTT_REGDEBUG
|
||||
static uint32_t sam34_getreg(uint32_t addr)
|
||||
{
|
||||
static uint32_t prevaddr = 0;
|
||||
@ -214,7 +204,7 @@ static uint32_t sam34_getreg(uint32_t addr)
|
||||
{
|
||||
if (count == 4)
|
||||
{
|
||||
_llerr("...\n");
|
||||
tmrinfo("...\n");
|
||||
}
|
||||
|
||||
return val;
|
||||
@ -231,7 +221,7 @@ static uint32_t sam34_getreg(uint32_t addr)
|
||||
{
|
||||
/* Yes.. then show how many times the value repeated */
|
||||
|
||||
_llerr("[repeats %d more times]\n", count-3);
|
||||
tmrinfo("[repeats %d more times]\n", count-3);
|
||||
}
|
||||
|
||||
/* Save the new address, value, and count */
|
||||
@ -243,7 +233,7 @@ static uint32_t sam34_getreg(uint32_t addr)
|
||||
|
||||
/* Show the register value read */
|
||||
|
||||
_llerr("%08lx->%08lx\n", addr, val);
|
||||
tmrinfo("%08lx->%08lx\n", addr, val);
|
||||
return val;
|
||||
}
|
||||
#endif
|
||||
@ -256,12 +246,12 @@ static uint32_t sam34_getreg(uint32_t addr)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SAM34_RTT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
|
||||
#ifdef CONFIG_SAM34_RTT_REGDEBUG
|
||||
static void sam34_putreg(uint32_t val, uint32_t addr)
|
||||
{
|
||||
/* Show the register value being written */
|
||||
|
||||
_llerr("%08lx<-%08lx\n", addr, val);
|
||||
tmrinfo("%08lx<-%08lx\n", addr, val);
|
||||
|
||||
/* Write the value */
|
||||
|
||||
@ -287,7 +277,7 @@ static int sam34_interrupt(int irq, FAR void *context)
|
||||
{
|
||||
FAR struct sam34_lowerhalf_s *priv = &g_tcdev;
|
||||
|
||||
rttinfo("Entry\n");
|
||||
tmrinfo("Entry\n");
|
||||
DEBUGASSERT(irq == SAM_IRQ_RTT);
|
||||
|
||||
/* Check if the interrupt is really pending */
|
||||
@ -373,7 +363,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower)
|
||||
uint32_t mr;
|
||||
uint32_t vr;
|
||||
|
||||
rttinfo("Entry\n");
|
||||
tmrinfo("Entry\n");
|
||||
DEBUGASSERT(priv);
|
||||
|
||||
if (priv->started)
|
||||
@ -433,7 +423,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower)
|
||||
static int sam34_stop(FAR struct timer_lowerhalf_s *lower)
|
||||
{
|
||||
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
|
||||
rttinfo("Entry\n");
|
||||
tmrinfo("Entry\n");
|
||||
DEBUGASSERT(priv);
|
||||
|
||||
if (!priv->started)
|
||||
@ -474,7 +464,7 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower,
|
||||
{
|
||||
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
|
||||
|
||||
rttinfo("Entry\n");
|
||||
tmrinfo("Entry\n");
|
||||
DEBUGASSERT(priv);
|
||||
|
||||
/* Return the status bit */
|
||||
@ -498,9 +488,9 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower,
|
||||
|
||||
status->timeleft = 1000000ULL*(sam34_getreg(SAM_RTT_AR) - sam34_readvr())/RTT_FCLK;
|
||||
|
||||
rttinfo(" flags : %08x\n", status->flags);
|
||||
rttinfo(" timeout : %d\n", status->timeout);
|
||||
rttinfo(" timeleft : %d\n", status->timeleft);
|
||||
tmrinfo(" flags : %08x\n", status->flags);
|
||||
tmrinfo(" timeout : %d\n", status->timeout);
|
||||
tmrinfo(" timeleft : %d\n", status->timeleft);
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -526,7 +516,7 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower,
|
||||
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
|
||||
|
||||
DEBUGASSERT(priv);
|
||||
rttinfo("Entry: timeout=%d\n", timeout);
|
||||
tmrinfo("Entry: timeout=%d\n", timeout);
|
||||
|
||||
if (priv->started)
|
||||
{
|
||||
@ -537,7 +527,7 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower,
|
||||
|
||||
if (timeout < 1 || timeout > RTT_MAXTIMEOUT)
|
||||
{
|
||||
rtterr("Cannot represent timeout=%lu > %lu\n",
|
||||
tmrerr("ERROR: Cannot represent timeout=%lu > %lu\n",
|
||||
timeout, RTT_MAXTIMEOUT);
|
||||
return -ERANGE;
|
||||
}
|
||||
@ -547,7 +537,7 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower,
|
||||
timeout = (1000000ULL * priv->clkticks) / RTT_FCLK; /* Truncated timeout */
|
||||
priv->adjustment = priv->timeout - timeout; /* Truncated time to be added to next interval (dither) */
|
||||
|
||||
rttinfo("fclk=%d clkticks=%d timout=%d, adjustment=%d\n",
|
||||
tmrinfo("fclk=%d clkticks=%d timout=%d, adjustment=%d\n",
|
||||
RTT_FCLK, priv->clkticks, priv->timeout, priv->adjustment);
|
||||
|
||||
return OK;
|
||||
@ -582,7 +572,7 @@ static tccb_t sam34_sethandler(FAR struct timer_lowerhalf_s *lower,
|
||||
flags = enter_critical_section();
|
||||
|
||||
DEBUGASSERT(priv);
|
||||
rttinfo("Entry: handler=%p\n", handler);
|
||||
tmrinfo("Entry: handler=%p\n", handler);
|
||||
|
||||
/* Get the old handler return value */
|
||||
|
||||
@ -623,7 +613,7 @@ static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd,
|
||||
int ret = -ENOTTY;
|
||||
|
||||
DEBUGASSERT(priv);
|
||||
rttinfo("Entry: cmd=%d arg=%ld\n", cmd, arg);
|
||||
tmrinfo("Entry: cmd=%d arg=%ld\n", cmd, arg);
|
||||
UNUSED(priv);
|
||||
|
||||
return ret;
|
||||
@ -653,7 +643,7 @@ void sam_rttinitialize(FAR const char *devpath)
|
||||
{
|
||||
FAR struct sam34_lowerhalf_s *priv = &g_tcdev;
|
||||
|
||||
rttinfo("Entry: devpath=%s\n", devpath);
|
||||
tmrinfo("Entry: devpath=%s\n", devpath);
|
||||
|
||||
/* Initialize the driver state structure. Here we assume: (1) the state
|
||||
* structure lies in .bss and was zeroed at reset time. (2) This function
|
||||
|
||||
@ -102,7 +102,11 @@
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SAM34_SPI_DMA
|
||||
#ifndef CONFIG_DEBUG_SPI_INFO
|
||||
# undef CONFIG_SAM34_SPI_REGDEBUG
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_DEBUG_DMA_INFO
|
||||
# undef CONFIG_SAM34_SPI_DMADEBUG
|
||||
#endif
|
||||
|
||||
@ -134,7 +138,7 @@
|
||||
/* Debug *******************************************************************/
|
||||
/* Check if SPI debut is enabled */
|
||||
|
||||
#ifndef CONFIG_DEBUG_DMA
|
||||
#ifndef CONFIG_DEBUG_DMA_INFO
|
||||
# undef CONFIG_SAM34_SPI_DMADEBUG
|
||||
#endif
|
||||
|
||||
@ -420,7 +424,7 @@ static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value,
|
||||
{
|
||||
/* Yes... show how many times we did it */
|
||||
|
||||
_llerr("...[Repeats %d times]...\n", spi->ntimes);
|
||||
spiinfo("...[Repeats %d times]...\n", spi->ntimes);
|
||||
}
|
||||
|
||||
/* Save information about the new access */
|
||||
@ -454,7 +458,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi,
|
||||
#ifdef CONFIG_SAM34_SPI_REGDEBUG
|
||||
if (spi_checkreg(spi, false, value, address))
|
||||
{
|
||||
_llerr("%08x->%08x\n", address, value);
|
||||
spiinfo("%08x->%08x\n", address, value);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -477,7 +481,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value,
|
||||
#ifdef CONFIG_SAM34_SPI_REGDEBUG
|
||||
if (spi_checkreg(spi, true, value, address))
|
||||
{
|
||||
_llerr("%08x<-%08x\n", address, value);
|
||||
spiinfo("%08x<-%08x\n", address, value);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1055,7 +1059,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
|
||||
spics->frequency = frequency;
|
||||
spics->actual = actual;
|
||||
|
||||
spierr("Frequency %d->%d\n", frequency, actual);
|
||||
spiinfo("Frequency %d->%d\n", frequency, actual);
|
||||
return actual;
|
||||
}
|
||||
|
||||
|
||||
@ -63,6 +63,12 @@
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
#ifndef CONFIG_DEBUG_TIMER_INFO
|
||||
# undef CONFIG_SAM34_TC_REGDEBUG
|
||||
#endif
|
||||
|
||||
/* Clocking *****************************************************************/
|
||||
|
||||
/* TODO: Allow selection of any of the input clocks */
|
||||
@ -98,7 +104,7 @@ struct sam34_lowerhalf_s
|
||||
****************************************************************************/
|
||||
/* Register operations ******************************************************/
|
||||
|
||||
#if defined(CONFIG_SAM34_TC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
|
||||
#ifdef CONFIG_SAM34_TC_REGDEBUG
|
||||
static uint32_t sam34_getreg(uint32_t addr);
|
||||
static void sam34_putreg(uint32_t val, uint32_t addr);
|
||||
#else
|
||||
@ -158,7 +164,7 @@ static struct sam34_lowerhalf_s g_tcdevs[6];
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SAM34_TC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
|
||||
#ifdef CONFIG_SAM34_TC_REGDEBUG
|
||||
static uint32_t sam34_getreg(uint32_t addr)
|
||||
{
|
||||
static uint32_t prevaddr = 0;
|
||||
@ -179,7 +185,7 @@ static uint32_t sam34_getreg(uint32_t addr)
|
||||
{
|
||||
if (count == 4)
|
||||
{
|
||||
_llerr("...\n");
|
||||
tmrinfo("...\n");
|
||||
}
|
||||
|
||||
return val;
|
||||
@ -196,7 +202,7 @@ static uint32_t sam34_getreg(uint32_t addr)
|
||||
{
|
||||
/* Yes.. then show how many times the value repeated */
|
||||
|
||||
_llerr("[repeats %d more times]\n", count-3);
|
||||
tmrinfo("[repeats %d more times]\n", count-3);
|
||||
}
|
||||
|
||||
/* Save the new address, value, and count */
|
||||
@ -208,7 +214,7 @@ static uint32_t sam34_getreg(uint32_t addr)
|
||||
|
||||
/* Show the register value read */
|
||||
|
||||
_llerr("%08lx->%08lx\n", addr, val);
|
||||
tmrinfo("%08lx->%08lx\n", addr, val);
|
||||
return val;
|
||||
}
|
||||
#endif
|
||||
@ -221,12 +227,12 @@ static uint32_t sam34_getreg(uint32_t addr)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SAM34_TC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
|
||||
#ifdef CONFIG_SAM34_TC_REGDEBUG
|
||||
static void sam34_putreg(uint32_t val, uint32_t addr)
|
||||
{
|
||||
/* Show the register value being written */
|
||||
|
||||
_llerr("%08lx<-%08lx\n", addr, val);
|
||||
tmrinfo("%08lx<-%08lx\n", addr, val);
|
||||
|
||||
/* Write the value */
|
||||
|
||||
|
||||
@ -85,6 +85,10 @@
|
||||
# define CONFIG_SAM34_TWI1_FREQUENCY 100000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_DEBUG_I2C_INFO
|
||||
# undef CONFIG_SAM34_TWI_REGDEBUG
|
||||
#endif
|
||||
|
||||
/* Driver internal definitions *************************************************/
|
||||
|
||||
#define TWI_TIMEOUT ((100 * CLK_TCK) / 1000) /* 100 mS */
|
||||
@ -273,7 +277,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value,
|
||||
{
|
||||
/* Yes... show how many times we did it */
|
||||
|
||||
_llerr("...[Repeats %d times]...\n", priv->ntimes);
|
||||
i2cinfo("...[Repeats %d times]...\n", priv->ntimes);
|
||||
}
|
||||
|
||||
/* Save information about the new access */
|
||||
@ -305,7 +309,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address)
|
||||
|
||||
if (twi_checkreg(priv, false, value, address))
|
||||
{
|
||||
_llerr("%08x->%08x\n", address, value);
|
||||
i2cinfo("%08x->%08x\n", address, value);
|
||||
}
|
||||
|
||||
return value;
|
||||
@ -326,7 +330,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address,
|
||||
{
|
||||
if (twi_checkreg(priv, true, value, address))
|
||||
{
|
||||
_llerr("%08x<-%08x\n", address, value);
|
||||
i2cinfo("%08x<-%08x\n", address, value);
|
||||
}
|
||||
|
||||
putreg32(value, address);
|
||||
@ -386,9 +390,9 @@ static int twi_wait(struct twi_dev_s *priv)
|
||||
|
||||
do
|
||||
{
|
||||
i2cllerr("TWI%d Waiting...\n", priv->twi);
|
||||
i2cllinfo("TWI%d Waiting...\n", priv->twi);
|
||||
twi_takesem(&priv->waitsem);
|
||||
i2cllerr("TWI%d Awakened with result: %d\n", priv->twi, priv->result);
|
||||
i2cllinfo("TWI%d Awakened with result: %d\n", priv->twi, priv->result);
|
||||
}
|
||||
while (priv->result == -EBUSY);
|
||||
|
||||
@ -578,7 +582,7 @@ static void twi_timeout(int argc, uint32_t arg, ...)
|
||||
{
|
||||
struct twi_dev_s *priv = (struct twi_dev_s *)arg;
|
||||
|
||||
i2cllerr("TWI%d Timeout!\n", priv->twi);
|
||||
i2cllerr("ERROR: TWI%d Timeout!\n", priv->twi);
|
||||
twi_wakeup(priv, -ETIMEDOUT);
|
||||
}
|
||||
|
||||
|
||||
@ -3115,11 +3115,11 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
|
||||
|
||||
if (privep->stalled || privep->pending)
|
||||
{
|
||||
/* Yes.. in this case, save the new they will get in a special
|
||||
* "pending" they will get queue until the stall is cleared.
|
||||
/* Yes.. in this case, save the request in a special "pending"
|
||||
* queue. They will stay queuee until the stall is cleared.
|
||||
*/
|
||||
|
||||
ullerr("Pending stall clear\n");
|
||||
ullinfo("Pending stall clear\n");
|
||||
sam_req_enqueue(&privep->pendq, privreq);
|
||||
usbtrace(TRACE_INREQQUEUED(epno), req->len);
|
||||
ret = OK;
|
||||
|
||||
@ -81,6 +81,10 @@
|
||||
# define CONFIG_SAM34_WDT_DEFTIMOUT WDT_MAXTIMEOUT
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_DEBUG_WATCHDOG_INFO
|
||||
# undef CONFIG_SAM34_WDT_REGDEBUG
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
@ -104,7 +108,7 @@ struct sam34_lowerhalf_s
|
||||
****************************************************************************/
|
||||
/* Register operations ******************************************************/
|
||||
|
||||
#if defined(CONFIG_SAM34_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
|
||||
#ifdef CONFIG_SAM34_WDT_REGDEBUG
|
||||
static uint32_t sam34_getreg(uint32_t addr);
|
||||
static void sam34_putreg(uint32_t val, uint32_t addr);
|
||||
#else
|
||||
@ -162,7 +166,7 @@ static struct sam34_lowerhalf_s g_wdgdev;
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SAM34_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
|
||||
#ifdef CONFIG_SAM34_WDT_REGDEBUG
|
||||
static uint32_t sam34_getreg(uint32_t addr)
|
||||
{
|
||||
static uint32_t prevaddr = 0;
|
||||
@ -183,7 +187,7 @@ static uint32_t sam34_getreg(uint32_t addr)
|
||||
{
|
||||
if (count == 4)
|
||||
{
|
||||
_llerr("...\n");
|
||||
wdinfo("...\n");
|
||||
}
|
||||
|
||||
return val;
|
||||
@ -200,7 +204,7 @@ static uint32_t sam34_getreg(uint32_t addr)
|
||||
{
|
||||
/* Yes.. then show how many times the value repeated */
|
||||
|
||||
_llerr("[repeats %d more times]\n", count-3);
|
||||
wdinfo("[repeats %d more times]\n", count-3);
|
||||
}
|
||||
|
||||
/* Save the new address, value, and count */
|
||||
@ -212,7 +216,7 @@ static uint32_t sam34_getreg(uint32_t addr)
|
||||
|
||||
/* Show the register value read */
|
||||
|
||||
_llerr("%08x->%08x\n", addr, val);
|
||||
wdinfo("%08x->%08x\n", addr, val);
|
||||
return val;
|
||||
}
|
||||
#endif
|
||||
@ -225,12 +229,12 @@ static uint32_t sam34_getreg(uint32_t addr)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SAM34_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
|
||||
#ifdef CONFIG_SAM34_WDT_REGDEBUG
|
||||
static void sam34_putreg(uint32_t val, uint32_t addr)
|
||||
{
|
||||
/* Show the register value being written */
|
||||
|
||||
_llerr("%08x<-%08x\n", addr, val);
|
||||
wdinfo("%08x<-%08x\n", addr, val);
|
||||
|
||||
/* Write the value */
|
||||
|
||||
@ -463,7 +467,7 @@ static int sam34_settimeout(FAR struct watchdog_lowerhalf_s *lower,
|
||||
|
||||
if (timeout < 1 || timeout > WDT_MAXTIMEOUT)
|
||||
{
|
||||
wderr("Cannot represent timeout=%d > %d\n",
|
||||
wderr("ERROR: Cannot represent timeout=%d > %d\n",
|
||||
timeout, WDT_MAXTIMEOUT);
|
||||
return -ERANGE;
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user