SAMA5 EHCI: No complete for bulk and control endpoints
This commit is contained in:
Gregory Nutt
parent
577b19920e
commit
f356586fd3
@ -5424,4 +5424,7 @@
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* nuttx/arch/arm/src/sama5/sam_ehci.c and other files: Create a skeleton
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environment for development of an EHCI driver. Not much in place yet
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(2013-8-20).
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* nuttx/arch/arm/src/sama5/sam_ehci.c: Now code complete for all
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asynchronous endpoints (control and bulk); nothing yet in place
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for periodic endponts (interrupt and isochronous) (2013-8-22).
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@ -108,7 +108,7 @@
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#define CONFIG_USBHOST_INT_DISABLE 1
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#undef CONFIG_USBHOST_ISOC_DISABLE
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#define CONFIG_USBHOST_INT_DISABLE 1
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#define CONFIG_USBHOST_ISOC_DISABLE 1
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/* Driver-private Definitions **************************************************/
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@ -178,11 +178,14 @@ struct sam_epinfo_s
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uint8_t dirin:1; /* 1:IN endpoint 0:OUT endpoint */
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uint8_t devaddr:7; /* Device address */
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uint8_t toggle:1; /* Next data toggle */
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uint8_t xfrtype:2; /* See USB_EP_ATTR_XFER_* definitions in usb.h */
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uint8_t speed:2; /* See USB_*_SPEED definitions in ehci.h */
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#ifndef CONFIG_USBHOST_INT_DISABLE
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uint8_t interval; /* Polling interval */
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#endif
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uint8_t status; /* Retained token status bits (for debug purposes) */
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volatile bool iocwait; /* TRUE: Thread is waiting for transfer completion */
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uint16_t maxpacket; /* Maximum packet size */
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uint16_t maxpacket:11; /* Maximum packet size */
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uint16_t xfrtype:2; /* See USB_EP_ATTR_XFER_* definitions in usb.h */
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uint16_t speed:2; /* See USB_*_SPEED definitions in ehci.h */
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int result; /* The result of the transfer */
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sem_t iocsem; /* Semaphore used to wait for transfer completion */
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};
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@ -236,8 +239,10 @@ struct sam_ehci_s
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static uint16_t sam_read16(const uint8_t *addr);
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static uint32_t sam_read32(const uint8_t *addr);
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#if 0 /* Not used */
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static void sam_write16(uint16_t memval, uint8_t *addr);
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static void sam_write32(uint32_t memval, uint8_t *addr);
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#endif
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#ifdef CONFIG_ENDIAN_BIG
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static uint16_t sam_swap16(uint16_t value);
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@ -285,8 +290,10 @@ static int sam_qh_discard(struct sam_qh_s *qh);
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/* Cache Operations ************************************************************/
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#if 0 /* Not used */
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static int sam_qtd_invalidate(struct sam_qtd_s *qtd, uint32_t **bp, void *arg);
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static int sam_qh_invalidate(struct sam_qh_s *qh);
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#endif
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static int sam_qtd_flush(struct sam_qtd_s *qtd, uint32_t **bp, void *arg);
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static int sam_qh_flush(struct sam_qh_s *qh);
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@ -311,7 +318,6 @@ static int sam_async_transfer(struct sam_rhport_s *rhport,
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static int sam_qtd_ioccheck(struct sam_qtd_s *qtd, uint32_t **bp, void *arg);
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static int sam_qh_ioccheck(struct sam_qh_s *qh, uint32_t **bp, void *arg);
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static inline void sam_ioc_bottomhalf(void);
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static inline void sam_err_bottomhalf(void);
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static inline void sam_portsc_bottomhalf(void);
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static inline void sam_syserr_bottomhalf(void);
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static inline void sam_async_advance_bottomhalf(void);
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@ -439,6 +445,7 @@ static inline uint32_t sam_read32(const uint8_t *addr)
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*
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*******************************************************************************/
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#if 0 /* Not used */
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static void sam_write16(uint16_t memval, uint8_t *addr)
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{
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#ifdef CONFIG_ENDIAN_BIG
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@ -449,6 +456,7 @@ static void sam_write16(uint16_t memval, uint8_t *addr)
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addr[1] = memval & 0xff;
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#endif
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}
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#endif
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/*******************************************************************************
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* Name: sam_write32
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@ -458,6 +466,7 @@ static void sam_write16(uint16_t memval, uint8_t *addr)
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*
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*******************************************************************************/
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#if 0 /* Not used */
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static void sam_write32(uint32_t memval, uint8_t *addr)
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{
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#ifdef CONFIG_ENDIAN_BIG
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@ -468,6 +477,7 @@ static void sam_write32(uint32_t memval, uint8_t *addr)
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sam_write16(memval >> 16, &addr[2]);
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#endif
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}
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#endif
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/*******************************************************************************
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* Name: sam_swap16
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@ -1053,6 +1063,7 @@ static int sam_qh_discard(struct sam_qh_s *qh)
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*
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*******************************************************************************/
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#if 0 /* Not used */
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static int sam_qtd_invalidate(struct sam_qtd_s *qtd, uint32_t **bp, void *arg)
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{
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/* Invalidate the D-Cache, i.e., force reloading of the D-Cache from memory
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@ -1063,6 +1074,7 @@ static int sam_qtd_invalidate(struct sam_qtd_s *qtd, uint32_t **bp, void *arg)
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(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
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return OK;
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}
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#endif
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/*******************************************************************************
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* Name: sam_qh_invalidate
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@ -1072,6 +1084,7 @@ static int sam_qtd_invalidate(struct sam_qtd_s *qtd, uint32_t **bp, void *arg)
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*
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*******************************************************************************/
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#if 0 /* Not used */
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static int sam_qh_invalidate(struct sam_qh_s *qh)
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{
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/* Invalidate the QH first so that we reload the qTD list head */
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@ -1081,8 +1094,9 @@ static int sam_qh_invalidate(struct sam_qh_s *qh)
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/* Then invalidate all of the qTD entries in the queue */
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return sam_qtd_foreach(qh, NULL, NULL);
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return sam_qtd_foreach(qh, sam_qtd_invalidate, NULL);
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}
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#endif
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/*******************************************************************************
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* Name: sam_qtd_flush
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@ -1121,7 +1135,7 @@ static int sam_qh_flush(struct sam_qh_s *qh)
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/* Then flush all of the qTD entries in the queue */
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return sam_qtd_foreach(qh, NULL, NULL);
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return sam_qtd_foreach(qh, sam_qtd_flush, NULL);
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}
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/*******************************************************************************
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@ -1922,8 +1936,6 @@ static inline void sam_ioc_bottomhalf(void)
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{
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int ret;
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uvdbg("USB Interrupt (USBINT) Interrupt\n");
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/* Make sure that the head of the asynchronous queue is invalidated */
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cp15_invalidate_dcache((uintptr_t)&g_asynchead.hw,
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@ -1938,27 +1950,6 @@ static inline void sam_ioc_bottomhalf(void)
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}
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}
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/*******************************************************************************
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* Name: sam_err_bottomhalf
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*
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* Description:
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* EHCI USB Error Interrupt (USBERRINT) "Bottom Half" interrupt handler
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*
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* "The Host Controller sets this bit to 1 when completion of a USB transaction
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* results in an error condition (e.g., error counter underflow). If the TD on
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* which the error interrupt occurred also had its IOC bit set, both this bit
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* and USBINT bit are set. ..."
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*
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*******************************************************************************/
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static inline void sam_err_bottomhalf(void)
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{
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udbg("USB Error Interrupt (USBERRINT) Interrupt\n");
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/* Remove all queued transfers */
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#warning Missing logic
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}
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/*******************************************************************************
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* Name: sam_portsc_bottomhalf
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*
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@ -2114,8 +2105,7 @@ static inline void sam_async_advance_bottomhalf(void)
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{
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udbg("Async Advance Interrupt\n");
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/* Remove all tagged QH entries */
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#warning Missing logic
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/* REVISIT: Could remove all tagged QH entries here */
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}
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/*******************************************************************************
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@ -2147,24 +2137,30 @@ static void sam_ehci_bottomhalf(FAR void *arg)
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* "The Host Controller also sets this bit to 1 when a short packet is
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* detected (actual number of bytes received was less than the expected
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* number of bytes)."
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*/
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if ((pending & EHCI_INT_USBINT) != 0)
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{
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sam_ioc_bottomhalf();
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}
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/* USB Error Interrupt (USBERRINT)
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*
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* USB Error Interrupt (USBERRINT)
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*
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* "The Host Controller sets this bit to 1 when completion of a USB
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* transaction results in an error condition (e.g., error counter
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* underflow). If the TD on which the error interrupt occurred also
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* had its IOC bit set, both this bit and USBINT bit are set. ..."
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*
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* We do the same thing in either case: Traverse the asynchonous queue
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* and remove all of the transfers that are no longer active.
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*/
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if ((pending & EHCI_INT_USBERRINT) != 0)
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if ((pending & (EHCI_INT_USBINT | EHCI_INT_USBERRINT)) != 0)
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{
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sam_err_bottomhalf();
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if ((pending & EHCI_INT_USBERRINT) != 0)
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{
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udbg("USB Error Interrupt (USBERRINT) Interrupt\n");
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}
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else
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{
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uvdbg("USB Interrupt (USBINT) Interrupt\n");
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}
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sam_ioc_bottomhalf();
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}
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/* Port Change Detect
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@ -2403,6 +2399,8 @@ static int sam_wait(FAR struct usbhost_connection_s *conn,
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static int sam_enumerate(FAR struct usbhost_connection_s *conn, int rhpndx)
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{
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struct sam_rhport_s *rhport;
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volatile uint32_t *regaddr;
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uint32_t regval;
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DEBUGASSERT(rhpndx >= 0 && rhpndx < SAM_EHCI_NRHPORT);
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rhport = &g_ehci.rhport[rhpndx];
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@ -2419,26 +2417,74 @@ static int sam_enumerate(FAR struct usbhost_connection_s *conn, int rhpndx)
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return -ENODEV;
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}
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/* Add EP0 to the control list */
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#warning Missing logic
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/* USB 2.0 spec says at least 50ms delay before port reset.
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* REVISIT: I think this is wrong. It needs to hold the port in
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* reset for 50Msec, not wait 50Msec before resetting.
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*/
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/* USB 2.0 spec says at least 50ms delay before port reset */
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usleep(100*1000);
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up_mdelay(100);
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/* Put the root hub port in reset.
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*
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* Paragraph 2.3.9:
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*
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* "The HCHalted bit in the USBSTS register should be a zero before
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* software attempts to use [the Port Reset] bit. The host controller
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* may hold Port Reset asserted to a one when the HCHalted bit is a one.
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*/
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/* Put the root hub port in reset (the SAMA5 supports three downstream ports) */
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#warning Missing logic
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DEBUGASSERT((sam_getreg(&HCOR->usbsts) & EHCI_USBSTS_HALTED) == 0);
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/* Wait for the port reset to complete */
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#warning Missing logic
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/* paragraph 2.3.9:
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*
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* "When software writes a one to [the Port Reset] bit (from a zero), the
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* bus reset sequence as defined in the USB Specification Revision 2.0 is
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* started. Software writes a zero to this bit to terminate the bus reset
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* sequence. Software must keep this bit at a one long enough to ensure
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* the reset sequence, as specified in the USB Specification Revision 2.0,
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* completes. Note: when software writes this bit to a one, it must also
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* write a zero to the Port Enable bit."
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*/
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/* Release RH port 1 from reset and wait a bit */
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#warning Missing logic
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regaddr = &HCOR->portsc[rhport->rhpndx];
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regval = sam_getreg(regaddr);
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regval &= ~EHCI_PORTSC_PE;
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regval &= EHCI_PORTSC_RESET;
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sam_putreg(regval, regaddr);
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up_mdelay(200);
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/* USB 2.0 "Root hubs must provide an aggregate reset period of at least
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* 50 ms."
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*/
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usleep(50*1000);
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regval = sam_getreg(regaddr);
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regval &= ~EHCI_PORTSC_RESET;
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sam_putreg(regval, regaddr);
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/* Wait for the port reset to complete
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*
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* Paragraph 2.3.9:
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*
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* "Note that when software writes a zero to this bit there may be a
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* delay before the bit status changes to a zero. The bit status will
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* not read as a zero until after the reset has completed. If the port
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* is in high-speed mode after reset is complete, the host controller
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* will automatically enable this port (e.g. set the Port Enable bit
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* to a one). A host controller must terminate the reset and stabilize
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* the state of the port within 2 milliseconds of software transitioning
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* this bit from a one to a zero ..."
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*/
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while ((sam_getreg(regaddr) & EHCI_PORTSC_RESET) != 0);
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usleep(200*1000);
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/* Let the common usbhost_enumerate do all of the real work. Note that the
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* FunctionAddress (USB address) is set to the root hub port number for now.
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* FunctionAddress (USB address) is set to the root hub port number + 1
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* for now.
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*
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* REVISIT: Hub support will require better device address assignment.
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* See include/nuttx/usb/usbhost_devaddr.h.
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*/
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uvdbg("Enumerate the device\n");
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@ -2475,19 +2521,25 @@ static int sam_ep0configure(FAR struct usbhost_driver_s *drvr, uint8_t funcaddr,
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uint16_t maxpacketsize)
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{
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struct sam_rhport_s *rhport = (struct sam_rhport_s *)drvr;
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struct sam_epinfo_s *epinfo;
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DEBUGASSERT(rhport &&
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funcaddr >= 0 && funcaddr <= SAM_EHCI_NRHPORT &&
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maxpacketsize < 2048);
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epinfo = &rhport->ep0;
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/* We must have exclusive access to the EHCI data structures. */
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sam_takesem(&g_ehci.exclsem);
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#warning Missing logic
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/* Remember the new device address and max packet size */
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epinfo->devaddr = funcaddr;
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epinfo->maxpacket = maxpacketsize;
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sam_givesem(&g_ehci.exclsem);
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return -ENOSYS;
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return OK;
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}
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/************************************************************************************
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@ -2515,46 +2567,48 @@ static int sam_ep0configure(FAR struct usbhost_driver_s *drvr, uint8_t funcaddr,
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static int sam_epalloc(FAR struct usbhost_driver_s *drvr,
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const FAR struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep)
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{
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struct sam_rhport_s *rhport = (struct sam_rhport_s *)drvr;
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struct sam_epinfo_s *epinfo;
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int ret = -ENOMEM;
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/* Sanity check. NOTE that this method should only be called if a device is
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* connected (because we need a valid low speed indication).
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*/
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DEBUGASSERT(rhport && epdesc && ep && rhport->connected);
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DEBUGASSERT(drvr && epdesc && ep);
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uvdbg("EP%d DIR=%s FA=%08x TYPE=%d Interval=%d Max Packet Size=%d\n",
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epdesc->addr, epdesc->in ? "IN" : "OUT", epdesc->funcaddr,
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epdesc->xfrtype, epdesc->interval, epdesc->mxpacketsize);
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/* Allocate a container for the endpoint data */
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/* Allocate a endpoint information structure */
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epinfo = (struct sam_epinfo_s *)kzalloc(sizeof(struct sam_epinfo_s));
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if (!epinfo)
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{
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udbg("ERROR: Failed to allocate EP info structure\n");
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goto errout;
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return -ENOMEM;
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}
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/* Initialize the endpoint container */
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/* Initialize the endpoint container (which is really just another form of
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* 'struct usbhost_epdesc_s', packed differently and with additional
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* information. A cleaner design might just embed struct usbhost_epdesc_s
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* inside of struct sam_epinfo_s and just memcpy here.
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*/
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epinfo->epno = epdesc->addr;
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epinfo->dirin = epdesc->in;
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epinfo->devaddr = epdesc->funcaddr;
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epinfo->xfrtype = epdesc->xfrtype;
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#ifndef CONFIG_USBHOST_INT_DISABLE
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epinfo->interval = epdesc->interval;
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#endif
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epinfo->maxpacket = epdesc->mxpacketsize;
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sem_init(&epinfo->iocsem, 0, 0);
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/* We must have exclusive access to the EHCI data structures. */
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sam_takesem(&g_ehci.exclsem);
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#warning Missing logic
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/* Success.. return an opaque reference to the endpoint list container */
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/* Success.. return an opaque reference to the endpoint information structure
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* instance
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*/
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*ep = (usbhost_ep_t)epinfo;
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sam_givesem(&g_ehci.exclsem);
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return OK;
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errout_with_semaphore:
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sam_givesem(&g_ehci.exclsem);
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kfree(epinfo);
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errout:
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return ret;
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}
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/************************************************************************************
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@ -2579,28 +2633,16 @@ errout:
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static int sam_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
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{
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struct sam_rhport_s *rhport = (struct sam_rhport_s *)drvr;
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struct sam_epinfo_s *epinfo = (struct sam_epinfo_s *)ep;
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int ret;
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DEBUGASSERT(rhport && epinfo);
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/* There should not be any pending, transfers */
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#warning Missing logic
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/* We must have exclusive access to the EHCI data structures. */
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DEBUGASSERT(drvr && epinfo && epinfo->iocwait == 0);
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sam_takesem(&g_ehci.exclsem);
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/* Free the container */
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#warning Missing logic
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ret = -ENOSYS;
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/* And free the container */
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sem_destroy(&epinfo->iocsem);
|
||||
kfree(epinfo);
|
||||
sam_givesem(&g_ehci.exclsem);
|
||||
return ret;
|
||||
return OK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
@ -2877,7 +2919,6 @@ static int sam_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
|
||||
int ret;
|
||||
|
||||
DEBUGASSERT(rhport && epinfo && buffer && buflen > 0);
|
||||
#warning Missing logic
|
||||
|
||||
/* We must have exclusive access to the EHCI hardware and data structures. */
|
||||
|
||||
@ -2891,10 +2932,16 @@ static int sam_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
|
||||
ret = sam_async_transfer(rhport, epinfo, NULL, buffer, buflen);
|
||||
break;
|
||||
|
||||
default:
|
||||
case USB_EP_ATTR_XFER_CONTROL:
|
||||
case USB_EP_ATTR_XFER_ISOC:
|
||||
#ifndef CONFIG_USBHOST_INT_DISABLE
|
||||
case USB_EP_ATTR_XFER_INT:
|
||||
# warning "Interrupt endpoint support not emplemented"
|
||||
#endif
|
||||
#ifndef CONFIG_USBHOST_ISOC_DISABLE
|
||||
case USB_EP_ATTR_XFER_ISOC:
|
||||
# warning "Isochronous endpoint support not emplemented"
|
||||
#endif
|
||||
case USB_EP_ATTR_XFER_CONTROL:
|
||||
default:
|
||||
udbg("ERROR: Support for transfer type %d not implemented\n");
|
||||
ret = -ENOSYS;
|
||||
break;
|
||||
@ -2932,10 +2979,8 @@ static void sam_disconnect(FAR struct usbhost_driver_s *drvr)
|
||||
struct sam_rhport_s *rhport = (struct sam_rhport_s *)drvr;
|
||||
DEBUGASSERT(rhport);
|
||||
|
||||
/* Remove the disconnected port */
|
||||
#warning Missing logic
|
||||
|
||||
/* Unbind the class */
|
||||
/* REVISIT: Is there more that needs to be done? */
|
||||
|
||||
rhport->class = NULL;
|
||||
}
|
||||
@ -3397,7 +3442,8 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
|
||||
|
||||
for (i = 0; i < SAM_EHCI_NRHPORT; i++)
|
||||
{
|
||||
#warning Missing logic
|
||||
g_ehci.rhport[i].connected =
|
||||
((sam_getreg(&HCOR->portsc[i]) & EHCI_PORTSC_CCS) != 0);
|
||||
}
|
||||
|
||||
/* Enable interrupts at the interrupt controller */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user