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SAMA5 OHCI: Fix some problems with D-Cache coherency and physical addressing related to interrupt endpoints

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This commit is contained in:
Gregory Nutt 2013-09-20 15:22:09 -06:00
parent f72ad05d0f
commit f3d56e8695
1 changed files with 6 additions and 1 deletions
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7
arch/arm/src/sama5/sam_ohci.c
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@ -3108,6 +3108,7 @@ static void sam_disconnect(FAR struct usbhost_driver_s *drvr)
FAR struct usbhost_connection_s *sam_ohci_initialize(int controller)
{
uintptr_t physaddr;
uint32_t regval;
uint8_t *buffer;
irqstate_t flags;
@ -3192,6 +3193,9 @@ FAR struct usbhost_connection_s *sam_ohci_initialize(int controller)
memset((void*)&g_hcca, 0, sizeof(struct ohci_hcca_s));
cp15_clean_dcache((uint32_t)&g_hcca,
(uint32_t)&g_hcca + sizeof(struct ohci_hcca_s));
/* Initialize user-configurable EDs */
for (i = 0; i < SAMA5_OHCI_NEDS; i++)
@ -3274,7 +3278,8 @@ FAR struct usbhost_connection_s *sam_ohci_initialize(int controller)
/* Set HCCA base address */
sam_putreg((uint32_t)&g_hcca, SAM_USBHOST_HCCA);
physaddr = sam_physramaddr((uintptr_t)&g_hcca);
sam_putreg(physaddr, SAM_USBHOST_HCCA);
/* Clear pending interrupts */