arch/stm32h7: Add FDCAN SocketCAN driver
Adds an FDCAN driver for STM32H7 MCUs using the SocketCAN interface
This commit is contained in:
JacobCrabill
Mateusz Szafoni
parent
4fa21c4719
commit
f406afdc42
@ -17,6 +17,8 @@ config ARCH_CHIP_STM32H743AG
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_G
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select STM32H7_IO_CONFIG_A
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
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UFBGA169
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@ -35,6 +37,8 @@ config ARCH_CHIP_STM32H743BG
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_G
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select STM32H7_IO_CONFIG_B
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
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LQFP208
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@ -44,6 +48,8 @@ config ARCH_CHIP_STM32H743BI
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_B
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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LQFP208
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@ -53,6 +59,8 @@ config ARCH_CHIP_STM32H743IG
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_G
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select STM32H7_IO_CONFIG_I
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
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LQFP176 or UFBGA176
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@ -62,6 +70,8 @@ config ARCH_CHIP_STM32H743II
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_I
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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LQFP176 or UFBGA176
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@ -71,6 +81,8 @@ config ARCH_CHIP_STM32H743VG
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_G
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select STM32H7_IO_CONFIG_V
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
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LQFP100 or TFBGA100
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@ -80,6 +92,8 @@ config ARCH_CHIP_STM32H743VI
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_V
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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LQFP100 or TFBGA100
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@ -89,6 +103,8 @@ config ARCH_CHIP_STM32H743XG
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_G
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select STM32H7_IO_CONFIG_X
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
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TFBGA240
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@ -98,6 +114,8 @@ config ARCH_CHIP_STM32H743XI
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_X
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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TFBGA240
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@ -107,6 +125,8 @@ config ARCH_CHIP_STM32H743ZG
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_G
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select STM32H7_IO_CONFIG_Z
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
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LQFP144
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@ -116,6 +136,8 @@ config ARCH_CHIP_STM32H743ZI
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_Z
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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LQFP144
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@ -125,6 +147,8 @@ config ARCH_CHIP_STM32H747XI
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select STM32H7_STM32H7X7XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_X
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM
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TFBGA240
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@ -134,6 +158,8 @@ config ARCH_CHIP_STM32H753AI
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_A
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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with cryptographic accelerator, UFBGA169
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@ -152,6 +178,8 @@ config ARCH_CHIP_STM32H753II
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_I
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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with cryptographic accelerator, LQFP176/UFBGA176
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@ -161,6 +189,8 @@ config ARCH_CHIP_STM32H753VI
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_V
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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with cryptographic accelerator, LQFP100/TFBGA100
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@ -179,6 +209,8 @@ config ARCH_CHIP_STM32H753ZI
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select STM32H7_STM32H7X3XX
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select STM32H7_FLASH_CONFIG_I
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select STM32H7_IO_CONFIG_Z
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select STM32H7_HAVE_FDCAN1
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select STM32H7_HAVE_FDCAN2
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---help---
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STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
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with cryptographic accelerator, LQFP144
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@ -365,6 +397,14 @@ config STM32H7_HAVE_SPI6
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bool
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default n
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config STM32H7_HAVE_FDCAN1
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bool
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default n
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config STM32H7_HAVE_FDCAN2
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bool
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default n
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# These "hidden" settings are the OR of individual peripheral selections
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# indicating that the general capability is required.
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@ -372,8 +412,11 @@ config STM32H7_ADC
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bool
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default n
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config STM32H7_CAN
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config STM32H7_FDCAN
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bool
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select NET_CAN_HAVE_CANFD
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select NET_CAN_EXTID
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select NET_CAN_HAVE_TX_DEADLINE
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default n
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config STM32H7_DAC
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@ -566,6 +609,18 @@ config STM32H7_WWDG
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default n
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select WATCHDOG
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config STM32H7_FDCAN1
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bool "FDCAN1"
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select STM32H7_FDCAN
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default n
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depends on STM32H7_HAVE_FDCAN1
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config STM32H7_FDCAN2
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bool "FDCAN2"
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select STM32H7_FDCAN
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default n
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depends on STM32H7_HAVE_FDCAN2
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menu "STM32H7 I2C Selection"
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config STM32H7_I2C1
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@ -1832,7 +1887,7 @@ config STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED
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This option configures the stm32_dmacapable to not disqualify
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DMA operations on memory that is not dcache aligned based solely
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on the starting address and byte count.
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Use this when ALL buffer extents are known to be aligned, but the
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the count does not use the complete buffer.
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@ -5326,6 +5381,114 @@ config STM32H7_QENCODER_SAMPLE_EVENT_8
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endchoice
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endmenu
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endmenu # QEncoder Driver
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menu "FDCAN Driver Configuration"
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depends on STM32H7_FDCAN1 || STM32H7_FDCAN2
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menu "FDCAN1 Configuration"
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depends on STM32H7_FDCAN1
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config FDCAN1_BITRATE
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int "CAN bitrate"
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depends on !NET_CAN_CANFD
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default 1000000
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config FDCAN1_ARBI_BITRATE
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int "CAN FD Arbitration phase bitrate"
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depends on NET_CAN_CANFD
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default 1000000
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config FDCAN1_DATA_BITRATE
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int "CAN FD Data phase bitrate"
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depends on NET_CAN_CANFD
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default 4000000
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endmenu # STM32H7_FDCAN1
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menu "FDCAN2 Configuration"
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depends on STM32H7_FDCAN2
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config FDCAN2_BITRATE
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int "CAN bitrate"
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depends on !NET_CAN_CANFD
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default 1000000
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config FDCAN2_ARBI_BITRATE
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int "CAN FD Arbitration phase bitrate"
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depends on NET_CAN_CANFD
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default 1000000
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config FDCAN2_DATA_BITRATE
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int "CAN FD Data phase bitrate"
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depends on NET_CAN_CANFD
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default 4000000
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endmenu # STM32H7_FDCAN2
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config STM32H7_FDCAN_REGDEBUG
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bool "Enable register dump debugging"
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depends on DEBUG_CAN_INFO
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depends on DEBUG_NET_INFO
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default n
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---help---
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Output detailed register-level CAN device debug information.
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Requires also CONFIG_DEBUG_CAN_INFO and CONFIG_DEBUG_NET_INFO.
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config STM32H7_FDCAN_LOOPBACK
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bool "Enable FDCAN loopback mode"
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default n
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---help---
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Enable the FDCAN local loopback mode for testing purposes.
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Requires a further choice of internal or external loopback mode.
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TODO: Enable separately for FDCAN1 and FDCAN2
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choice
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prompt "FDCAN Loopback Mode"
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depends on STM32H7_FDCAN_LOOPBACK
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default STM32H7_FDCAN_LOOPBACK_INTERNAL
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config STM32H7_FDCAN_LOOPBACK_INTERNAL
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bool "Internal loopback mode"
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---help---
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Enable internal loopback mode, where both Tx and Rx are
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disconnected from the CAN bus. This can be used for a "Hot Selftest",
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meaning the FDCAN can be used without affecting a running CAN bus.
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All transmitted frames are treated as received frames and processed
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accordingly.
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config STM32H7_FDCAN_LOOPBACK_EXTERNAL
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bool "External loopback mode"
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---help---
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Enable external loopback mode, where the Rx pin is disconnected from
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the CAN bus but the Tx pin remains connected.
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All transmitted frames are treated as received frames and processed
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accordingly.
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endchoice # CAN Loopback Mode
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choice
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prompt "FDCAN WorkQueue Selection"
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default STM32H7_FDCAN_LPWORK
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config STM32H7_FDCAN_LPWORK
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bool "Use LP work queue"
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---help---
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Use the low-priority (LP) work queue for reception and transmission
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of new frames and for processing of transmission timeouts.
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config STM32H7_FDCAN_HPWORK
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bool "Use HP work queue"
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---help---
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Use the high-priority (HP) work queue for reception and transmission
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of new frames and for processing of transmission timeouts.
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endchoice
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endmenu # FDCAN Driver
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endif # ARCH_CHIP_STM32H7
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@ -57,6 +57,10 @@ ifeq ($(CONFIG_STM32H7_ADC),y)
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CHIP_CSRCS += stm32_adc.c
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endif
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ifeq ($(CONFIG_STM32H7_FDCAN),y)
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CHIP_CSRCS += stm32_fdcan_sock.c
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endif
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ifeq ($(CONFIG_STM32H7_BBSRAM),y)
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CHIP_CSRCS += stm32_bbsram.c
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endif
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1579
arch/arm/src/stm32h7/hardware/stm32_fdcan.h
Normal file
1579
arch/arm/src/stm32h7/hardware/stm32_fdcan.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -36,6 +36,7 @@
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#include "chip.h"
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#include "stm32_gpio.h"
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#include "stm32_fdcan_sock.h"
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#include "stm32_fmc.h"
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#include "stm32_i2c.h"
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#include "stm32_spi.h"
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2529
arch/arm/src/stm32h7/stm32_fdcan_sock.c
Normal file
2529
arch/arm/src/stm32h7/stm32_fdcan_sock.c
Normal file
File diff suppressed because it is too large
Load Diff
107
arch/arm/src/stm32h7/stm32_fdcan_sock.h
Normal file
107
arch/arm/src/stm32h7/stm32_fdcan_sock.h
Normal file
@ -0,0 +1,107 @@
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/****************************************************************************
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* arch/arm/src/stm32h7/stm32_fdcan_sock.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H7_STM32_FDCAN_SOCK_H
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#define __ARCH_ARM_SRC_STM32H7_STM32_FDCAN_SOCK_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/stm32_fdcan.h"
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#ifdef CONFIG_STM32H7_FDCAN
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#ifndef CONFIG_NETDEV_LATEINIT
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/****************************************************************************
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* Function: arm_netinitialize
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*
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* Description:
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* Initialize the first network interface. If there is more than one
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* interface in the chip, then board-specific logic will have to provide
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* this function to determine which, if any, CAN interfaces should be
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* initialized. Also prototyped in up_internal.h.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* OK on success; Negated errno on failure.
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*
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* Assumptions:
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* Called very early in the initialization sequence.
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*
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****************************************************************************/
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void arm_netinitialize(void);
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#else
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/****************************************************************************
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* Function: stm32_fdcansockinitialize
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*
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* Description:
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* Initialize the CAN controller and driver
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*
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* Input Parameters:
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* intf - In the case where there are multiple CAN interfaces, this value
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* identifies which CAN interface is to be initialized.
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*
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* Returned Value:
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* OK on success; Negated errno on failure.
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*
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* Assumptions:
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*
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****************************************************************************/
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int stm32_fdcansockinitialize(int intf);
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_STM32H7_FDCAN */
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#endif /* __ARCH_ARM_SRC_STM32H7_STM32_FDCAN_SOCK_H */
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@ -432,13 +432,15 @@ static inline void rcc_enableapb1(void)
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regval |= RCC_APB1LENR_I2C3EN;
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#endif
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/* TODO: ... */
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putreg32(regval, STM32_RCC_APB1LENR); /* Enable APB1L peripherals */
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regval = getreg32(STM32_RCC_APB1HENR);
|
||||
|
||||
/* TODO: ... */
|
||||
#ifdef CONFIG_STM32H7_FDCAN
|
||||
/* FDCAN clock enable */
|
||||
|
||||
regval |= RCC_APB1HENR_FDCANEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB1HENR); /* Enable APB1H peripherals */
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user