diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index 804586bfb2..0a4f3f2ff0 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -17,6 +17,8 @@ config ARCH_CHIP_STM32H743AG select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_G select STM32H7_IO_CONFIG_A + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, UFBGA169 @@ -35,6 +37,8 @@ config ARCH_CHIP_STM32H743BG select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_G select STM32H7_IO_CONFIG_B + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, LQFP208 @@ -44,6 +48,8 @@ config ARCH_CHIP_STM32H743BI select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_B + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, LQFP208 @@ -53,6 +59,8 @@ config ARCH_CHIP_STM32H743IG select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_G select STM32H7_IO_CONFIG_I + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, LQFP176 or UFBGA176 @@ -62,6 +70,8 @@ config ARCH_CHIP_STM32H743II select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, LQFP176 or UFBGA176 @@ -71,6 +81,8 @@ config ARCH_CHIP_STM32H743VG select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_G select STM32H7_IO_CONFIG_V + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, LQFP100 or TFBGA100 @@ -80,6 +92,8 @@ config ARCH_CHIP_STM32H743VI select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_V + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, LQFP100 or TFBGA100 @@ -89,6 +103,8 @@ config ARCH_CHIP_STM32H743XG select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_G select STM32H7_IO_CONFIG_X + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, TFBGA240 @@ -98,6 +114,8 @@ config ARCH_CHIP_STM32H743XI select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, TFBGA240 @@ -107,6 +125,8 @@ config ARCH_CHIP_STM32H743ZG select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_G select STM32H7_IO_CONFIG_Z + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, LQFP144 @@ -116,6 +136,8 @@ config ARCH_CHIP_STM32H743ZI select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, LQFP144 @@ -125,6 +147,8 @@ config ARCH_CHIP_STM32H747XI select STM32H7_STM32H7X7XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM TFBGA240 @@ -134,6 +158,8 @@ config ARCH_CHIP_STM32H753AI select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_A + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, UFBGA169 @@ -152,6 +178,8 @@ config ARCH_CHIP_STM32H753II select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP176/UFBGA176 @@ -161,6 +189,8 @@ config ARCH_CHIP_STM32H753VI select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_V + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP100/TFBGA100 @@ -179,6 +209,8 @@ config ARCH_CHIP_STM32H753ZI select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP144 @@ -365,6 +397,14 @@ config STM32H7_HAVE_SPI6 bool default n +config STM32H7_HAVE_FDCAN1 + bool + default n + +config STM32H7_HAVE_FDCAN2 + bool + default n + # These "hidden" settings are the OR of individual peripheral selections # indicating that the general capability is required. @@ -372,8 +412,11 @@ config STM32H7_ADC bool default n -config STM32H7_CAN +config STM32H7_FDCAN bool + select NET_CAN_HAVE_CANFD + select NET_CAN_EXTID + select NET_CAN_HAVE_TX_DEADLINE default n config STM32H7_DAC @@ -566,6 +609,18 @@ config STM32H7_WWDG default n select WATCHDOG +config STM32H7_FDCAN1 + bool "FDCAN1" + select STM32H7_FDCAN + default n + depends on STM32H7_HAVE_FDCAN1 + +config STM32H7_FDCAN2 + bool "FDCAN2" + select STM32H7_FDCAN + default n + depends on STM32H7_HAVE_FDCAN2 + menu "STM32H7 I2C Selection" config STM32H7_I2C1 @@ -1832,7 +1887,7 @@ config STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED This option configures the stm32_dmacapable to not disqualify DMA operations on memory that is not dcache aligned based solely on the starting address and byte count. - + Use this when ALL buffer extents are known to be aligned, but the the count does not use the complete buffer. @@ -5326,6 +5381,114 @@ config STM32H7_QENCODER_SAMPLE_EVENT_8 endchoice -endmenu +endmenu # QEncoder Driver + +menu "FDCAN Driver Configuration" + depends on STM32H7_FDCAN1 || STM32H7_FDCAN2 + +menu "FDCAN1 Configuration" + depends on STM32H7_FDCAN1 + +config FDCAN1_BITRATE + int "CAN bitrate" + depends on !NET_CAN_CANFD + default 1000000 + +config FDCAN1_ARBI_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD + default 1000000 + +config FDCAN1_DATA_BITRATE + int "CAN FD Data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +endmenu # STM32H7_FDCAN1 + +menu "FDCAN2 Configuration" + depends on STM32H7_FDCAN2 + +config FDCAN2_BITRATE + int "CAN bitrate" + depends on !NET_CAN_CANFD + default 1000000 + +config FDCAN2_ARBI_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD + default 1000000 + +config FDCAN2_DATA_BITRATE + int "CAN FD Data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +endmenu # STM32H7_FDCAN2 + +config STM32H7_FDCAN_REGDEBUG + bool "Enable register dump debugging" + depends on DEBUG_CAN_INFO + depends on DEBUG_NET_INFO + default n + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO and CONFIG_DEBUG_NET_INFO. + +config STM32H7_FDCAN_LOOPBACK + bool "Enable FDCAN loopback mode" + default n + ---help--- + Enable the FDCAN local loopback mode for testing purposes. + Requires a further choice of internal or external loopback mode. + + TODO: Enable separately for FDCAN1 and FDCAN2 + +choice + prompt "FDCAN Loopback Mode" + depends on STM32H7_FDCAN_LOOPBACK + default STM32H7_FDCAN_LOOPBACK_INTERNAL + +config STM32H7_FDCAN_LOOPBACK_INTERNAL + bool "Internal loopback mode" + ---help--- + Enable internal loopback mode, where both Tx and Rx are + disconnected from the CAN bus. This can be used for a "Hot Selftest", + meaning the FDCAN can be used without affecting a running CAN bus. + + All transmitted frames are treated as received frames and processed + accordingly. + +config STM32H7_FDCAN_LOOPBACK_EXTERNAL + bool "External loopback mode" + ---help--- + Enable external loopback mode, where the Rx pin is disconnected from + the CAN bus but the Tx pin remains connected. + + All transmitted frames are treated as received frames and processed + accordingly. + +endchoice # CAN Loopback Mode + +choice + prompt "FDCAN WorkQueue Selection" + default STM32H7_FDCAN_LPWORK + +config STM32H7_FDCAN_LPWORK + bool "Use LP work queue" + ---help--- + Use the low-priority (LP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +config STM32H7_FDCAN_HPWORK + bool "Use HP work queue" + ---help--- + Use the high-priority (HP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +endchoice + +endmenu # FDCAN Driver + endif # ARCH_CHIP_STM32H7 diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index 643f8c2e15..c486877fbd 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -57,6 +57,10 @@ ifeq ($(CONFIG_STM32H7_ADC),y) CHIP_CSRCS += stm32_adc.c endif +ifeq ($(CONFIG_STM32H7_FDCAN),y) +CHIP_CSRCS += stm32_fdcan_sock.c +endif + ifeq ($(CONFIG_STM32H7_BBSRAM),y) CHIP_CSRCS += stm32_bbsram.c endif diff --git a/arch/arm/src/stm32h7/hardware/stm32_fdcan.h b/arch/arm/src/stm32h7/hardware/stm32_fdcan.h new file mode 100644 index 0000000000..e7842c0102 --- /dev/null +++ b/arch/arm/src/stm32h7/hardware/stm32_fdcan.h @@ -0,0 +1,1579 @@ +/**************************************************************************** + * arch/arm/src/stm32h7/hardware/stm32_fdcan.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FDCAN_H +#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FDCAN_H + +/* ************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/* ************************************************************************** + * * + * Flexible Datarate Controller Area Network * + * * + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_FDCAN_CREL_OFFSET 0x0000 /* FDCAN Core Release register */ +#define STM32_FDCAN_ENDN_OFFSET 0x0004 /* FDCAN Endian register */ +#define STM32_FDCAN_DBTP_OFFSET 0x000C /* FDCAN Data Bit Timing & Prescaler register */ +#define STM32_FDCAN_TEST_OFFSET 0x0010 /* FDCAN Test register */ +#define STM32_FDCAN_RWD_OFFSET 0x0014 /* FDCAN RAM Watchdog register */ +#define STM32_FDCAN_CCCR_OFFSET 0x0018 /* FDCAN CC Control register */ +#define STM32_FDCAN_NBTP_OFFSET 0x001C /* FDCAN Nominal Bit Timing & Prescaler register */ +#define STM32_FDCAN_TSCC_OFFSET 0x0020 /* FDCAN Timestamp Counter Configuration register */ +#define STM32_FDCAN_TSCV_OFFSET 0x0024 /* FDCAN Timestamp Counter Value register */ +#define STM32_FDCAN_TOCC_OFFSET 0x0028 /* FDCAN Timeout Counter Configuration register */ +#define STM32_FDCAN_TOCV_OFFSET 0x002C /* FDCAN Timeout Counter Value register */ +#define STM32_FDCAN_ECR_OFFSET 0x0040 /* FDCAN Error Counter register */ +#define STM32_FDCAN_PSR_OFFSET 0x0044 /* FDCAN Protocol Status register */ +#define STM32_FDCAN_TDCR_OFFSET 0x0048 /* FDCAN Transmitter Delay Compensation register */ +#define STM32_FDCAN_IR_OFFSET 0x0050 /* FDCAN Interrupt register */ +#define STM32_FDCAN_IE_OFFSET 0x0054 /* FDCAN Interrupt Enable register */ +#define STM32_FDCAN_ILS_OFFSET 0x0058 /* FDCAN Interrupt Line Select register */ +#define STM32_FDCAN_ILE_OFFSET 0x005C /* FDCAN Interrupt Line Enable register */ +#define STM32_FDCAN_GFC_OFFSET 0x0080 /* FDCAN Global Filter Configuration register */ +#define STM32_FDCAN_SIDFC_OFFSET 0x0084 /* FDCAN Standard ID Filter Configuration register */ +#define STM32_FDCAN_XIDFC_OFFSET 0x0088 /* FDCAN Extended ID Filter Configuration register */ +#define STM32_FDCAN_XIDAM_OFFSET 0x0090 /* FDCAN Extended ID AND Mask register */ +#define STM32_FDCAN_HPMS_OFFSET 0x0094 /* FDCAN High Priority Message Status register */ +#define STM32_FDCAN_NDAT1_OFFSET 0x0098 /* FDCAN New Data 1 register */ +#define STM32_FDCAN_NDAT2_OFFSET 0x009C /* FDCAN New Data 2 register */ +#define STM32_FDCAN_RXF0C_OFFSET 0x00A0 /* FDCAN Rx FIFO 0 Configuration register */ +#define STM32_FDCAN_RXF0S_OFFSET 0x00A4 /* FDCAN Rx FIFO 0 Status register */ +#define STM32_FDCAN_RXF0A_OFFSET 0x00A8 /* FDCAN Rx FIFO 0 Acknowledge register */ +#define STM32_FDCAN_RXBC_OFFSET 0x00AC /* FDCAN Rx Buffer Configuration register */ +#define STM32_FDCAN_RXF1C_OFFSET 0x00B0 /* FDCAN Rx FIFO 1 Configuration register */ +#define STM32_FDCAN_RXF1S_OFFSET 0x00B4 /* FDCAN Rx FIFO 1 Status register */ +#define STM32_FDCAN_RXF1A_OFFSET 0x00B8 /* FDCAN Rx FIFO 1 Acknowledge register */ +#define STM32_FDCAN_RXESC_OFFSET 0x00BC /* FDCAN Rx Buffer/FIFO Element Size Configuration register */ +#define STM32_FDCAN_TXBC_OFFSET 0x00C0 /* FDCAN Tx Buffer Configuration register */ +#define STM32_FDCAN_TXFQS_OFFSET 0x00C4 /* FDCAN Tx FIFO/Queue Status register */ +#define STM32_FDCAN_TXESC_OFFSET 0x00C8 /* FDCAN Tx Buffer Element Size Configuration register */ +#define STM32_FDCAN_TXBRP_OFFSET 0x00CC /* FDCAN Tx Buffer Request Pending register */ +#define STM32_FDCAN_TXBAR_OFFSET 0x00D0 /* FDCAN Tx Buffer Add Request register */ +#define STM32_FDCAN_TXBCR_OFFSET 0x00D4 /* FDCAN Tx Buffer Cancellation Request register */ +#define STM32_FDCAN_TXBTO_OFFSET 0x00D8 /* FDCAN Tx Buffer Transmission Occurred register */ +#define STM32_FDCAN_TXBCF_OFFSET 0x00DC /* FDCAN Tx Buffer Cancellation Finished register */ +#define STM32_FDCAN_TXBTIE_OFFSET 0x00E0 /* FDCAN Tx Buffer Transmission Interrupt Enable register */ +#define STM32_FDCAN_TXBCIE_OFFSET 0x00E4 /* FDCAN Tx Buffer Cancellation Finished Interrupt Enable register */ +#define STM32_FDCAN_TXEFC_OFFSET 0x00F0 /* FDCAN Tx Event FIFO Configuration register */ +#define STM32_FDCAN_TXEFS_OFFSET 0x00F4 /* FDCAN Tx Event FIFO Status register */ +#define STM32_FDCAN_TXEFA_OFFSET 0x00F8 /* FDCAN Tx Event FIFO Acknowledge register */ + +/* Register Addresses *******************************************************/ + +#define STM32_FDCAN1_CREL (STM32_FDCAN1_BASE + STM32_FDCAN_CREL_OFFSET) +#define STM32_FDCAN1_ENDN (STM32_FDCAN1_BASE + STM32_FDCAN_ENDN_OFFSET) +#define STM32_FDCAN1_DBTP (STM32_FDCAN1_BASE + STM32_FDCAN_DBTP_OFFSET) +#define STM32_FDCAN1_TEST (STM32_FDCAN1_BASE + STM32_FDCAN_TEST_OFFSET) +#define STM32_FDCAN1_RWD (STM32_FDCAN1_BASE + STM32_FDCAN_RWD_OFFSET) +#define STM32_FDCAN1_CCCR (STM32_FDCAN1_BASE + STM32_FDCAN_CCCR_OFFSET) +#define STM32_FDCAN1_NBTP (STM32_FDCAN1_BASE + STM32_FDCAN_NBTP_OFFSET) +#define STM32_FDCAN1_TSCC (STM32_FDCAN1_BASE + STM32_FDCAN_TSCC_OFFSET) +#define STM32_FDCAN1_TSCV (STM32_FDCAN1_BASE + STM32_FDCAN_TSCV_OFFSET) +#define STM32_FDCAN1_TOCC (STM32_FDCAN1_BASE + STM32_FDCAN_TOCC_OFFSET) +#define STM32_FDCAN1_TOCV (STM32_FDCAN1_BASE + STM32_FDCAN_TOCV_OFFSET) +#define STM32_FDCAN1_ECR (STM32_FDCAN1_BASE + STM32_FDCAN_ECR_OFFSET) +#define STM32_FDCAN1_PSR (STM32_FDCAN1_BASE + STM32_FDCAN_PSR_OFFSET) +#define STM32_FDCAN1_TDCR (STM32_FDCAN1_BASE + STM32_FDCAN_TDCR_OFFSET) +#define STM32_FDCAN1_IR (STM32_FDCAN1_BASE + STM32_FDCAN_IR_OFFSET) +#define STM32_FDCAN1_IE (STM32_FDCAN1_BASE + STM32_FDCAN_IE_OFFSET) +#define STM32_FDCAN1_ILS (STM32_FDCAN1_BASE + STM32_FDCAN_ILS_OFFSET) +#define STM32_FDCAN1_ILE (STM32_FDCAN1_BASE + STM32_FDCAN_ILE_OFFSET) +#define STM32_FDCAN1_GFC (STM32_FDCAN1_BASE + STM32_FDCAN_GFC_OFFSET) +#define STM32_FDCAN1_SIDFC (STM32_FDCAN1_BASE + STM32_FDCAN_SIDFC_OFFSET) +#define STM32_FDCAN1_XIDFC (STM32_FDCAN1_BASE + STM32_FDCAN_XIDFC_OFFSET) +#define STM32_FDCAN1_XIDAM (STM32_FDCAN1_BASE + STM32_FDCAN_XIDAM_OFFSET) +#define STM32_FDCAN1_HPMS (STM32_FDCAN1_BASE + STM32_FDCAN_HPMS_OFFSET) +#define STM32_FDCAN1_NDAT1 (STM32_FDCAN1_BASE + STM32_FDCAN_NDAT1_OFFSET) +#define STM32_FDCAN1_NDAT2 (STM32_FDCAN1_BASE + STM32_FDCAN_NDAT2_OFFSET) +#define STM32_FDCAN1_RXF0C (STM32_FDCAN1_BASE + STM32_FDCAN_RXF0C_OFFSET) +#define STM32_FDCAN1_RXF0S (STM32_FDCAN1_BASE + STM32_FDCAN_RXF0S_OFFSET) +#define STM32_FDCAN1_RXF0A (STM32_FDCAN1_BASE + STM32_FDCAN_RXF0A_OFFSET) +#define STM32_FDCAN1_RXBC (STM32_FDCAN1_BASE + STM32_FDCAN_RXBC_OFFSET) +#define STM32_FDCAN1_RXF1C (STM32_FDCAN1_BASE + STM32_FDCAN_RXF1C_OFFSET) +#define STM32_FDCAN1_RXF1S (STM32_FDCAN1_BASE + STM32_FDCAN_RXF1S_OFFSET) +#define STM32_FDCAN1_RXF1A (STM32_FDCAN1_BASE + STM32_FDCAN_RXF1A_OFFSET) +#define STM32_FDCAN1_RXESC (STM32_FDCAN1_BASE + STM32_FDCAN_RXESC_OFFSET) +#define STM32_FDCAN1_TXBC (STM32_FDCAN1_BASE + STM32_FDCAN_TXBC_OFFSET) +#define STM32_FDCAN1_TXFQS (STM32_FDCAN1_BASE + STM32_FDCAN_TXFQS_OFFSET) +#define STM32_FDCAN1_TXESC (STM32_FDCAN1_BASE + STM32_FDCAN_TXESC_OFFSET) +#define STM32_FDCAN1_TXBRP (STM32_FDCAN1_BASE + STM32_FDCAN_TXBRP_OFFSET) +#define STM32_FDCAN1_TXBAR (STM32_FDCAN1_BASE + STM32_FDCAN_TXBAR_OFFSET) +#define STM32_FDCAN1_TXBCR (STM32_FDCAN1_BASE + STM32_FDCAN_TXBCR_OFFSET) +#define STM32_FDCAN1_TXBTO (STM32_FDCAN1_BASE + STM32_FDCAN_TXBTO_OFFSET) +#define STM32_FDCAN1_TXBCF (STM32_FDCAN1_BASE + STM32_FDCAN_TXBCF_OFFSET) +#define STM32_FDCAN1_TXBTIE (STM32_FDCAN1_BASE + STM32_FDCAN_TXBTIE_OFFSET) +#define STM32_FDCAN1_TXBCIE (STM32_FDCAN1_BASE + STM32_FDCAN_TXBCIE_OFFSET) +#define STM32_FDCAN1_TXEFC (STM32_FDCAN1_BASE + STM32_FDCAN_TXEFC_OFFSET) +#define STM32_FDCAN1_TXEFS (STM32_FDCAN1_BASE + STM32_FDCAN_TXEFS_OFFSET) +#define STM32_FDCAN1_TXEFA (STM32_FDCAN1_BASE + STM32_FDCAN_TXEFA_OFFSET) + +#define STM32_FDCAN2_CREL (STM32_FDCAN2_BASE + STM32_FDCAN_CREL_OFFSET) +#define STM32_FDCAN2_ENDN (STM32_FDCAN2_BASE + STM32_FDCAN_ENDN_OFFSET) +#define STM32_FDCAN2_DBTP (STM32_FDCAN2_BASE + STM32_FDCAN_DBTP_OFFSET) +#define STM32_FDCAN2_TEST (STM32_FDCAN2_BASE + STM32_FDCAN_TEST_OFFSET) +#define STM32_FDCAN2_RWD (STM32_FDCAN2_BASE + STM32_FDCAN_RWD_OFFSET) +#define STM32_FDCAN2_CCCR (STM32_FDCAN2_BASE + STM32_FDCAN_CCCR_OFFSET) +#define STM32_FDCAN2_NBTP (STM32_FDCAN2_BASE + STM32_FDCAN_NBTP_OFFSET) +#define STM32_FDCAN2_TSCC (STM32_FDCAN2_BASE + STM32_FDCAN_TSCC_OFFSET) +#define STM32_FDCAN2_TSCV (STM32_FDCAN2_BASE + STM32_FDCAN_TSCV_OFFSET) +#define STM32_FDCAN2_TOCC (STM32_FDCAN2_BASE + STM32_FDCAN_TOCC_OFFSET) +#define STM32_FDCAN2_TOCV (STM32_FDCAN2_BASE + STM32_FDCAN_TOCV_OFFSET) +#define STM32_FDCAN2_ECR (STM32_FDCAN2_BASE + STM32_FDCAN_ECR_OFFSET) +#define STM32_FDCAN2_PSR (STM32_FDCAN2_BASE + STM32_FDCAN_PSR_OFFSET) +#define STM32_FDCAN2_TDCR (STM32_FDCAN2_BASE + STM32_FDCAN_TDCR_OFFSET) +#define STM32_FDCAN2_IR (STM32_FDCAN2_BASE + STM32_FDCAN_IR_OFFSET) +#define STM32_FDCAN2_IE (STM32_FDCAN2_BASE + STM32_FDCAN_IE_OFFSET) +#define STM32_FDCAN2_ILS (STM32_FDCAN2_BASE + STM32_FDCAN_ILS_OFFSET) +#define STM32_FDCAN2_ILE (STM32_FDCAN2_BASE + STM32_FDCAN_ILE_OFFSET) +#define STM32_FDCAN2_GFC (STM32_FDCAN2_BASE + STM32_FDCAN_GFC_OFFSET) +#define STM32_FDCAN2_SIDFC (STM32_FDCAN2_BASE + STM32_FDCAN_SIDFC_OFFSET) +#define STM32_FDCAN2_XIDFC (STM32_FDCAN2_BASE + STM32_FDCAN_XIDFC_OFFSET) +#define STM32_FDCAN2_XIDAM (STM32_FDCAN2_BASE + STM32_FDCAN_XIDAM_OFFSET) +#define STM32_FDCAN2_HPMS (STM32_FDCAN2_BASE + STM32_FDCAN_HPMS_OFFSET) +#define STM32_FDCAN2_NDAT1 (STM32_FDCAN2_BASE + STM32_FDCAN_NDAT1_OFFSET) +#define STM32_FDCAN2_NDAT2 (STM32_FDCAN2_BASE + STM32_FDCAN_NDAT2_OFFSET) +#define STM32_FDCAN2_RXF0C (STM32_FDCAN2_BASE + STM32_FDCAN_RXF0C_OFFSET) +#define STM32_FDCAN2_RXF0S (STM32_FDCAN2_BASE + STM32_FDCAN_RXF0S_OFFSET) +#define STM32_FDCAN2_RXF0A (STM32_FDCAN2_BASE + STM32_FDCAN_RXF0A_OFFSET) +#define STM32_FDCAN2_RXBC (STM32_FDCAN2_BASE + STM32_FDCAN_RXBC_OFFSET) +#define STM32_FDCAN2_RXF1C (STM32_FDCAN2_BASE + STM32_FDCAN_RXF1C_OFFSET) +#define STM32_FDCAN2_RXF1S (STM32_FDCAN2_BASE + STM32_FDCAN_RXF1S_OFFSET) +#define STM32_FDCAN2_RXF1A (STM32_FDCAN2_BASE + STM32_FDCAN_RXF1A_OFFSET) +#define STM32_FDCAN2_RXESC (STM32_FDCAN2_BASE + STM32_FDCAN_RXESC_OFFSET) +#define STM32_FDCAN2_TXBC (STM32_FDCAN2_BASE + STM32_FDCAN_TXBC_OFFSET) +#define STM32_FDCAN2_TXFQS (STM32_FDCAN2_BASE + STM32_FDCAN_TXFQS_OFFSET) +#define STM32_FDCAN2_TXESC (STM32_FDCAN2_BASE + STM32_FDCAN_TXESC_OFFSET) +#define STM32_FDCAN2_TXBRP (STM32_FDCAN2_BASE + STM32_FDCAN_TXBRP_OFFSET) +#define STM32_FDCAN2_TXBAR (STM32_FDCAN2_BASE + STM32_FDCAN_TXBAR_OFFSET) +#define STM32_FDCAN2_TXBCR (STM32_FDCAN2_BASE + STM32_FDCAN_TXBCR_OFFSET) +#define STM32_FDCAN2_TXBTO (STM32_FDCAN2_BASE + STM32_FDCAN_TXBTO_OFFSET) +#define STM32_FDCAN2_TXBCF (STM32_FDCAN2_BASE + STM32_FDCAN_TXBCF_OFFSET) +#define STM32_FDCAN2_TXBTIE (STM32_FDCAN2_BASE + STM32_FDCAN_TXBTIE_OFFSET) +#define STM32_FDCAN2_TXBCIE (STM32_FDCAN2_BASE + STM32_FDCAN_TXBCIE_OFFSET) +#define STM32_FDCAN2_TXEFC (STM32_FDCAN2_BASE + STM32_FDCAN_TXEFC_OFFSET) +#define STM32_FDCAN2_TXEFS (STM32_FDCAN2_BASE + STM32_FDCAN_TXEFS_OFFSET) +#define STM32_FDCAN2_TXEFA (STM32_FDCAN2_BASE + STM32_FDCAN_TXEFA_OFFSET) + +/* FDCAN control and status registers */ +#define FDCAN_CREL_DAY_SHIFT (0U) +#define FDCAN_CREL_DAY_MASK (0xFFU << FDCAN_CREL_DAY_SHIFT) /* 0x000000FF */ +#define FDCAN_CREL_DAY FDCAN_CREL_DAY_MASK /* Timestamp Day */ +#define FDCAN_CREL_MON_SHIFT (8U) +#define FDCAN_CREL_MON_MASK (0xFFU << FDCAN_CREL_MON_SHIFT) /* 0x0000FF00 */ +#define FDCAN_CREL_MON FDCAN_CREL_MON_MASK /* Timestamp Month */ +#define FDCAN_CREL_YEAR_SHIFT (16U) +#define FDCAN_CREL_YEAR_MASK (0xFU << FDCAN_CREL_YEAR_SHIFT) /* 0x000F0000 */ +#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_MASK /* Timestamp Year */ +#define FDCAN_CREL_SUBSTEP_SHIFT (20U) +#define FDCAN_CREL_SUBSTEP_MASK (0xFU << FDCAN_CREL_SUBSTEP_SHIFT) /* 0x00F00000 */ +#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_MASK /* Sub-step of Core release */ +#define FDCAN_CREL_STEP_SHIFT (24U) +#define FDCAN_CREL_STEP_MASK (0xFU << FDCAN_CREL_STEP_SHIFT) /* 0x0F000000 */ +#define FDCAN_CREL_STEP FDCAN_CREL_STEP_MASK /* Step of Core release */ +#define FDCAN_CREL_REL_SHIFT (28U) +#define FDCAN_CREL_REL_MASK (0xFU << FDCAN_CREL_REL_SHIFT) /* 0xF0000000 */ +#define FDCAN_CREL_REL FDCAN_CREL_REL_MASK /* Core release */ + +/* *************** Bit definition for FDCAN_ENDN register *****************/ +#define FDCAN_ENDN_ETV_SHIFT (0U) +#define FDCAN_ENDN_ETV_MASK (0xFFFFFFFFU << FDCAN_ENDN_ETV_SHIFT) /* 0xFFFFFFFF */ +#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_MASK /* Endiannes Test Value */ + +/* *************** Bit definition for FDCAN_DBTP register *****************/ +#define FDCAN_DBTP_DSJW_SHIFT (0U) +#define FDCAN_DBTP_DSJW_MASK (0xFU << FDCAN_DBTP_DSJW_SHIFT) /* 0x0000000F */ +#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_MASK /* Synchronization Jump Width */ +#define FDCAN_DBTP_DTSEG2_SHIFT (4U) +#define FDCAN_DBTP_DTSEG2_MASK (0xFU << FDCAN_DBTP_DTSEG2_SHIFT) /* 0x000000F0 */ +#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_MASK /* Data time segment after sample point */ +#define FDCAN_DBTP_DTSEG1_SHIFT (8U) +#define FDCAN_DBTP_DTSEG1_MASK (0xFU << FDCAN_DBTP_DTSEG1_SHIFT) /* 0x00000F00 */ +#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_MASK /* Data time segment before sample point */ +#define FDCAN_DBTP_DBRP_SHIFT (16U) +#define FDCAN_DBTP_DBRP_MASK (0x1FU << FDCAN_DBTP_DBRP_SHIFT) /* 0x001F0000 */ +#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_MASK /* Data BIt Rate Prescaler */ +#define FDCAN_DBTP_TDC_SHIFT (23U) +#define FDCAN_DBTP_TDC_MASK (0x1U << FDCAN_DBTP_TDC_SHIFT) /* 0x00800000 */ +#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_MASK /* Transceiver Delay Compensation */ + +/* *************** Bit definition for FDCAN_TEST register *****************/ +#define FDCAN_TEST_LBCK_SHIFT (4U) +#define FDCAN_TEST_LBCK_MASK (0x1U << FDCAN_TEST_LBCK_SHIFT) /* 0x00000010 */ +#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_MASK /* Loop Back mode */ +#define FDCAN_TEST_TX_SHIFT (5U) +#define FDCAN_TEST_TX_MASK (0x3U << FDCAN_TEST_TX_SHIFT) /* 0x00000060 */ +#define FDCAN_TEST_TX FDCAN_TEST_TX_MASK /* Control of Transmit Pin */ +#define FDCAN_TEST_RX_SHIFT (7U) +#define FDCAN_TEST_RX_MASK (0x1U << FDCAN_TEST_RX_SHIFT) /* 0x00000080 */ +#define FDCAN_TEST_RX FDCAN_TEST_RX_MASK /* Receive Pin */ + +/* *************** Bit definition for FDCAN_RWD register ******************/ +#define FDCAN_RWD_WDC_SHIFT (0U) +#define FDCAN_RWD_WDC_MASK (0xFU << FDCAN_RWD_WDC_SHIFT) /* 0x0000000F */ +#define FDCAN_RWD_WDC FDCAN_RWD_WDC_MASK /* Watchdog configuration */ +#define FDCAN_RWD_WDV_SHIFT (4U) +#define FDCAN_RWD_WDV_MASK (0xFU << FDCAN_RWD_WDV_SHIFT) /* 0x000000F0 */ +#define FDCAN_RWD_WDV FDCAN_RWD_WDV_MASK /* Watchdog value */ + +/* *************** Bit definition for FDCAN_CCCR register *****************/ +#define FDCAN_CCCR_INIT_SHIFT (0U) +#define FDCAN_CCCR_INIT_MASK (0x1U << FDCAN_CCCR_INIT_SHIFT) /* 0x00000001 */ +#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_MASK /* Initialization */ +#define FDCAN_CCCR_CCE_SHIFT (1U) +#define FDCAN_CCCR_CCE_MASK (0x1U << FDCAN_CCCR_CCE_SHIFT) /* 0x00000002 */ +#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_MASK /* Configuration Change Enable */ +#define FDCAN_CCCR_ASM_SHIFT (2U) +#define FDCAN_CCCR_ASM_MASK (0x1U << FDCAN_CCCR_ASM_SHIFT) /* 0x00000004 */ +#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_MASK /* ASM Restricted Operation Mode */ +#define FDCAN_CCCR_CSA_SHIFT (3U) +#define FDCAN_CCCR_CSA_MASK (0x1U << FDCAN_CCCR_CSA_SHIFT) /* 0x00000008 */ +#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_MASK /* Clock Stop Acknowledge */ +#define FDCAN_CCCR_CSR_SHIFT (4U) +#define FDCAN_CCCR_CSR_MASK (0x1U << FDCAN_CCCR_CSR_SHIFT) /* 0x00000010 */ +#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_MASK /* Clock Stop Request */ +#define FDCAN_CCCR_MON_SHIFT (5U) +#define FDCAN_CCCR_MON_MASK (0x1U << FDCAN_CCCR_MON_SHIFT) /* 0x00000020 */ +#define FDCAN_CCCR_MON FDCAN_CCCR_MON_MASK /* Bus Monitoring Mode */ +#define FDCAN_CCCR_DAR_SHIFT (6U) +#define FDCAN_CCCR_DAR_MASK (0x1U << FDCAN_CCCR_DAR_SHIFT) /* 0x00000040 */ +#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_MASK /* Disable Automatic Retransmission */ +#define FDCAN_CCCR_TEST_SHIFT (7U) +#define FDCAN_CCCR_TEST_MASK (0x1U << FDCAN_CCCR_TEST_SHIFT) /* 0x00000080 */ +#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_MASK /* Test Mode Enable */ +#define FDCAN_CCCR_FDOE_SHIFT (8U) +#define FDCAN_CCCR_FDOE_MASK (0x1U << FDCAN_CCCR_FDOE_SHIFT) /* 0x00000100 */ +#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_MASK /* FD Operation Enable */ +#define FDCAN_CCCR_BRSE_SHIFT (9U) +#define FDCAN_CCCR_BRSE_MASK (0x1U << FDCAN_CCCR_BRSE_SHIFT) /* 0x00000200 */ +#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_MASK /* FDCAN Bit Rate Switching */ +#define FDCAN_CCCR_PXHD_SHIFT (12U) +#define FDCAN_CCCR_PXHD_MASK (0x1U << FDCAN_CCCR_PXHD_SHIFT) /* 0x00001000 */ +#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_MASK /* Protocol Exception Handling Disable */ +#define FDCAN_CCCR_EFBI_SHIFT (13U) +#define FDCAN_CCCR_EFBI_MASK (0x1U << FDCAN_CCCR_EFBI_SHIFT) /* 0x00002000 */ +#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_MASK /* Edge Filtering during Bus Integration */ +#define FDCAN_CCCR_TXP_SHIFT (14U) +#define FDCAN_CCCR_TXP_MASK (0x1U << FDCAN_CCCR_TXP_SHIFT) /* 0x00004000 */ +#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_MASK /* Two CAN bit times Pause */ +#define FDCAN_CCCR_NISO_SHIFT (15U) +#define FDCAN_CCCR_NISO_MASK (0x1U << FDCAN_CCCR_NISO_SHIFT) /* 0x00008000 */ +#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_MASK /* Non ISO Operation */ + +/* *************** Bit definition for FDCAN_NBTP register *****************/ +#define FDCAN_NBTP_TSEG2_SHIFT (0U) +#define FDCAN_NBTP_TSEG2_MASK (0x7FU << FDCAN_NBTP_TSEG2_SHIFT) /* 0x0000007F */ +#define FDCAN_NBTP_TSEG2 FDCAN_NBTP_TSEG2_MASK /* Nominal Time segment after sample point */ +#define FDCAN_NBTP_NTSEG1_SHIFT (8U) +#define FDCAN_NBTP_NTSEG1_MASK (0xFFU << FDCAN_NBTP_NTSEG1_SHIFT) /* 0x0000FF00 */ +#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_MASK /* Nominal Time segment before sample point */ +#define FDCAN_NBTP_NBRP_SHIFT (16U) +#define FDCAN_NBTP_NBRP_MASK (0x1FFU << FDCAN_NBTP_NBRP_SHIFT) /* 0x01FF0000 */ +#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_MASK /* Bit Rate Prescaler */ +#define FDCAN_NBTP_NSJW_SHIFT (25U) +#define FDCAN_NBTP_NSJW_MASK (0x7FU << FDCAN_NBTP_NSJW_SHIFT) /* 0xFE000000 */ +#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_MASK /* Nominal (Re)Synchronization Jump Width */ + +/* *************** Bit definition for FDCAN_TSCC register *****************/ +#define FDCAN_TSCC_TSS_SHIFT (0U) +#define FDCAN_TSCC_TSS_MASK (0x3U << FDCAN_TSCC_TSS_SHIFT) /* 0x00000003 */ +#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_MASK /* Timestamp Select */ +#define FDCAN_TSCC_TCP_SHIFT (16U) +#define FDCAN_TSCC_TCP_MASK (0xFU << FDCAN_TSCC_TCP_SHIFT) /* 0x000F0000 */ +#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_MASK /* Timestamp Counter Prescaler */ + +/* *************** Bit definition for FDCAN_TSCV register *****************/ +#define FDCAN_TSCV_TSC_SHIFT (0U) +#define FDCAN_TSCV_TSC_MASK (0xFFFFU << FDCAN_TSCV_TSC_SHIFT) /* 0x0000FFFF */ +#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_MASK /* Timestamp Counter */ + +/* *************** Bit definition for FDCAN_TOCC register *****************/ +#define FDCAN_TOCC_ETOC_SHIFT (0U) +#define FDCAN_TOCC_ETOC_MASK (0x1U << FDCAN_TOCC_ETOC_SHIFT) /* 0x00000001 */ +#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_MASK /* Enable Timeout Counter */ +#define FDCAN_TOCC_TOS_SHIFT (1U) +#define FDCAN_TOCC_TOS_MASK (0x3U << FDCAN_TOCC_TOS_SHIFT) /* 0x00000006 */ +#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_MASK /* Timeout Select */ +#define FDCAN_TOCC_TOP_SHIFT (16U) +#define FDCAN_TOCC_TOP_MASK (0xFFFFU << FDCAN_TOCC_TOP_SHIFT) /* 0xFFFF0000 */ +#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_MASK /* Timeout Period */ + +/* *************** Bit definition for FDCAN_TOCV register *****************/ +#define FDCAN_TOCV_TOC_SHIFT (0U) +#define FDCAN_TOCV_TOC_MASK (0xFFFFU << FDCAN_TOCV_TOC_SHIFT) /* 0x0000FFFF */ +#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_MASK /* Timeout Counter */ + +/* *************** Bit definition for FDCAN_ECR register ******************/ +#define FDCAN_ECR_TEC_SHIFT (0U) +#define FDCAN_ECR_TEC_MASK (0xFU << FDCAN_ECR_TEC_SHIFT) /* 0x0000000F */ +#define FDCAN_ECR_TEC FDCAN_ECR_TEC_MASK /* Transmit Error Counter */ +#define FDCAN_ECR_TREC_SHIFT (8U) +#define FDCAN_ECR_TREC_MASK (0x7FU << FDCAN_ECR_TREC_SHIFT) /* 0x00007F00 */ +#define FDCAN_ECR_TREC FDCAN_ECR_TREC_MASK /* Receive Error Counter */ +#define FDCAN_ECR_RP_SHIFT (15U) +#define FDCAN_ECR_RP_MASK (0 x1U << FDCAN_ECR_RP_SHIFT) /* 0x00008000 */ +#define FDCAN_ECR_RP FDCAN_ECR_RP_MASK /* Receive Error Passive */ +#define FDCAN_ECR_CEL_SHIFT (16U) +#define FDCAN_ECR_CEL_MASK (0xFFU << FDCAN_ECR_CEL_SHIFT) /* 0x00FF0000 */ +#define FDCAN_ECR_CEL FDCAN_ECR_CEL_MASK /* CAN Error Logging */ + +/* *************** Bit definition for FDCAN_PSR register ******************/ +#define FDCAN_PSR_LEC_SHIFT (0U) +#define FDCAN_PSR_LEC_MASK (0x7U << FDCAN_PSR_LEC_SHIFT) /* 0x00000007 */ +#define FDCAN_PSR_LEC FDCAN_PSR_LEC_MASK /* Last Error Code */ +#define FDCAN_PSR_ACT_SHIFT (3U) +#define FDCAN_PSR_ACT_MASK (0x3U << FDCAN_PSR_ACT_SHIFT) /* 0x00000018 */ +#define FDCAN_PSR_ACT FDCAN_PSR_ACT_MASK /* Activity */ +#define FDCAN_PSR_EP_SHIFT (5U) +#define FDCAN_PSR_EP_MASK (0x1U << FDCAN_PSR_EP_SHIFT) /* 0x00000020 */ +#define FDCAN_PSR_EP FDCAN_PSR_EP_MASK /* Error Passive */ +#define FDCAN_PSR_EW_SHIFT (6U) +#define FDCAN_PSR_EW_MASK (0x1U << FDCAN_PSR_EW_SHIFT) /* 0x00000040 */ +#define FDCAN_PSR_EW FDCAN_PSR_EW_MASK /* Warning Status */ +#define FDCAN_PSR_BO_SHIFT (7U) +#define FDCAN_PSR_BO_MASK (0x1U << FDCAN_PSR_BO_SHIFT) /* 0x00000080 */ +#define FDCAN_PSR_BO FDCAN_PSR_BO_MASK /* Bus_Off Status */ +#define FDCAN_PSR_DLEC_SHIFT (8U) +#define FDCAN_PSR_DLEC_MASK (0x7U << FDCAN_PSR_DLEC_SHIFT) /* 0x00000700 */ +#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_MASK /* Data Last Error Code */ +#define FDCAN_PSR_RESI_SHIFT (11U) +#define FDCAN_PSR_RESI_MASK (0x1U << FDCAN_PSR_RESI_SHIFT) /* 0x00000800 */ +#define FDCAN_PSR_RESI FDCAN_PSR_RESI_MASK /* ESI flag of last received FDCAN Message */ +#define FDCAN_PSR_RBRS_SHIFT (12U) +#define FDCAN_PSR_RBRS_MASK (0x1U << FDCAN_PSR_RBRS_SHIFT) /* 0x00001000 */ +#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_MASK /* BRS flag of last received FDCAN Message */ +#define FDCAN_PSR_REDL_SHIFT (13U) +#define FDCAN_PSR_REDL_MASK (0x1U << FDCAN_PSR_REDL_SHIFT) /* 0x00002000 */ +#define FDCAN_PSR_REDL FDCAN_PSR_REDL_MASK /* Received FDCAN Message */ +#define FDCAN_PSR_PXE_SHIFT (14U) +#define FDCAN_PSR_PXE_MASK (0x1U << FDCAN_PSR_PXE_SHIFT) /* 0x00004000 */ +#define FDCAN_PSR_PXE FDCAN_PSR_PXE_MASK /* Protocol Exception Event */ +#define FDCAN_PSR_TDCV_SHIFT (16U) +#define FDCAN_PSR_TDCV_MASK (0x7FU << FDCAN_PSR_TDCV_SHIFT) /* 0x007F0000 */ +#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_MASK /* Transmitter Delay Compensation Value */ + +/* *************** Bit definition for FDCAN_TDCR register *****************/ +#define FDCAN_TDCR_TDCF_SHIFT (0U) +#define FDCAN_TDCR_TDCF_MASK (0x7FU << FDCAN_TDCR_TDCF_SHIFT) /* 0x0000007F */ +#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_MASK /* Transmitter Delay Compensation Filter */ +#define FDCAN_TDCR_TDCO_SHIFT (8U) +#define FDCAN_TDCR_TDCO_MASK (0x7FU << FDCAN_TDCR_TDCO_SHIFT) /* 0x00007F00 */ +#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_MASK /* Transmitter Delay Compensation Offset */ + +/* *************** Bit definition for FDCAN_IR register *******************/ +#define FDCAN_IR_RF0N_SHIFT (0U) +#define FDCAN_IR_RF0N_MASK (0x1U << FDCAN_IR_RF0N_SHIFT) /* 0x00000001 */ +#define FDCAN_IR_RF0N FDCAN_IR_RF0N_MASK /* Rx FIFO 0 New Message */ +#define FDCAN_IR_RF0W_SHIFT (1U) +#define FDCAN_IR_RF0W_MASK (0x1U << FDCAN_IR_RF0W_SHIFT) /* 0x00000002 */ +#define FDCAN_IR_RF0W FDCAN_IR_RF0W_MASK /* Rx FIFO 0 Watermark Reached */ +#define FDCAN_IR_RF0F_SHIFT (2U) +#define FDCAN_IR_RF0F_MASK (0x1U << FDCAN_IR_RF0F_SHIFT) /* 0x00000004 */ +#define FDCAN_IR_RF0F FDCAN_IR_RF0F_MASK /* Rx FIFO 0 Full */ +#define FDCAN_IR_RF0L_SHIFT (3U) +#define FDCAN_IR_RF0L_MASK (0x1U << FDCAN_IR_RF0L_SHIFT) /* 0x00000008 */ +#define FDCAN_IR_RF0L FDCAN_IR_RF0L_MASK /* Rx FIFO 0 Message Lost */ +#define FDCAN_IR_RF1N_SHIFT (4U) +#define FDCAN_IR_RF1N_MASK (0x1U << FDCAN_IR_RF1N_SHIFT) /* 0x00000010 */ +#define FDCAN_IR_RF1N FDCAN_IR_RF1N_MASK /* Rx FIFO 1 New Message */ +#define FDCAN_IR_RF1W_SHIFT (5U) +#define FDCAN_IR_RF1W_MASK (0x1U << FDCAN_IR_RF1W_SHIFT) /* 0x00000020 */ +#define FDCAN_IR_RF1W FDCAN_IR_RF1W_MASK /* Rx FIFO 1 Watermark Reached */ +#define FDCAN_IR_RF1F_SHIFT (6U) +#define FDCAN_IR_RF1F_MASK (0x1U << FDCAN_IR_RF1F_SHIFT) /* 0x00000040 */ +#define FDCAN_IR_RF1F FDCAN_IR_RF1F_MASK /* Rx FIFO 1 Full */ +#define FDCAN_IR_RF1L_SHIFT (7U) +#define FDCAN_IR_RF1L_MASK (0x1U << FDCAN_IR_RF1L_SHIFT) /* 0x00000080 */ +#define FDCAN_IR_RF1L FDCAN_IR_RF1L_MASK /* Rx FIFO 1 Message Lost */ +#define FDCAN_IR_HPM_SHIFT (8U) +#define FDCAN_IR_HPM_MASK (0x1U << FDCAN_IR_HPM_SHIFT) /* 0x00000100 */ +#define FDCAN_IR_HPM FDCAN_IR_HPM_MASK /* High Priority Message */ +#define FDCAN_IR_TC_SHIFT (9U) +#define FDCAN_IR_TC_MASK (0x1U << FDCAN_IR_TC_SHIFT) /* 0x00000200 */ +#define FDCAN_IR_TC FDCAN_IR_TC_MASK /* Transmission Completed */ +#define FDCAN_IR_TCF_SHIFT (10U) +#define FDCAN_IR_TCF_MASK (0x1U << FDCAN_IR_TCF_SHIFT) /* 0x00000400 */ +#define FDCAN_IR_TCF FDCAN_IR_TCF_MASK /* Transmission Cancellation Finished */ +#define FDCAN_IR_TFE_SHIFT (11U) +#define FDCAN_IR_TFE_MASK (0x1U << FDCAN_IR_TFE_SHIFT) /* 0x00000800 */ +#define FDCAN_IR_TFE FDCAN_IR_TFE_MASK /* Tx FIFO Empty */ +#define FDCAN_IR_TEFN_SHIFT (12U) +#define FDCAN_IR_TEFN_MASK (0x1U << FDCAN_IR_TEFN_SHIFT) /* 0x00001000 */ +#define FDCAN_IR_TEFN FDCAN_IR_TEFN_MASK /* Tx Event FIFO New Entry */ +#define FDCAN_IR_TEFW_SHIFT (13U) +#define FDCAN_IR_TEFW_MASK (0x1U << FDCAN_IR_TEFW_SHIFT) /* 0x00002000 */ +#define FDCAN_IR_TEFW FDCAN_IR_TEFW_MASK /* Tx Event FIFO Watermark Reached */ +#define FDCAN_IR_TEFF_SHIFT (14U) +#define FDCAN_IR_TEFF_MASK (0x1U << FDCAN_IR_TEFF_SHIFT) /* 0x00004000 */ +#define FDCAN_IR_TEFF FDCAN_IR_TEFF_MASK /* Tx Event FIFO Full */ +#define FDCAN_IR_TEFL_SHIFT (15U) +#define FDCAN_IR_TEFL_MASK (0x1U << FDCAN_IR_TEFL_SHIFT) /* 0x00008000 */ +#define FDCAN_IR_TEFL FDCAN_IR_TEFL_MASK /* Tx Event FIFO Element Lost */ +#define FDCAN_IR_TSW_SHIFT (16U) +#define FDCAN_IR_TSW_MASK (0x1U << FDCAN_IR_TSW_SHIFT) /* 0x00010000 */ +#define FDCAN_IR_TSW FDCAN_IR_TSW_MASK /* Timestamp Wraparound */ +#define FDCAN_IR_MRAF_SHIFT (17U) +#define FDCAN_IR_MRAF_MASK (0x1U << FDCAN_IR_MRAF_SHIFT) /* 0x00020000 */ +#define FDCAN_IR_MRAF FDCAN_IR_MRAF_MASK /* Message RAM Access Failure */ +#define FDCAN_IR_TOO_SHIFT (18U) +#define FDCAN_IR_TOO_MASK (0x1U << FDCAN_IR_TOO_SHIFT) /* 0x00040000 */ +#define FDCAN_IR_TOO FDCAN_IR_TOO_MASK /* Timeout Occurred */ +#define FDCAN_IR_DRX_SHIFT (19U) +#define FDCAN_IR_DRX_MASK (0x1U << FDCAN_IR_DRX_SHIFT) /* 0x00080000 */ +#define FDCAN_IR_DRX FDCAN_IR_DRX_MASK /* Message stored to Dedicated Rx Buffer */ +#define FDCAN_IR_ELO_SHIFT (22U) +#define FDCAN_IR_ELO_MASK (0x1U << FDCAN_IR_ELO_SHIFT) /* 0x00400000 */ +#define FDCAN_IR_ELO FDCAN_IR_ELO_MASK /* Error Logging Overflow */ +#define FDCAN_IR_EP_SHIFT (23U) +#define FDCAN_IR_EP_MASK (0x1U << FDCAN_IR_EP_SHIFT) /* 0x00800000 */ +#define FDCAN_IR_EP FDCAN_IR_EP_MASK /* Error Passive */ +#define FDCAN_IR_EW_SHIFT (24U) +#define FDCAN_IR_EW_MASK (0x1U << FDCAN_IR_EW_SHIFT) /* 0x01000000 */ +#define FDCAN_IR_EW FDCAN_IR_EW_MASK /* Warning Status */ +#define FDCAN_IR_BO_SHIFT (25U) +#define FDCAN_IR_BO_MASK (0x1U << FDCAN_IR_BO_SHIFT) /* 0x02000000 */ +#define FDCAN_IR_BO FDCAN_IR_BO_MASK /* Bus_Off Status */ +#define FDCAN_IR_WDI_SHIFT (26U) +#define FDCAN_IR_WDI_MASK (0x1U << FDCAN_IR_WDI_SHIFT) /* 0x04000000 */ +#define FDCAN_IR_WDI FDCAN_IR_WDI_MASK /* Watchdog Interrupt */ +#define FDCAN_IR_PEA_SHIFT (27U) +#define FDCAN_IR_PEA_MASK (0x1U << FDCAN_IR_PEA_SHIFT) /* 0x08000000 */ +#define FDCAN_IR_PEA FDCAN_IR_PEA_MASK /* Protocol Error in Arbitration Phase */ +#define FDCAN_IR_PED_SHIFT (28U) +#define FDCAN_IR_PED_MASK (0x1U << FDCAN_IR_PED_SHIFT) /* 0x10000000 */ +#define FDCAN_IR_PED FDCAN_IR_PED_MASK /* Protocol Error in Data Phase */ +#define FDCAN_IR_ARA_SHIFT (29U) +#define FDCAN_IR_ARA_MASK (0x1U << FDCAN_IR_ARA_SHIFT) /* 0x20000000 */ +#define FDCAN_IR_ARA FDCAN_IR_ARA_MASK /* Access to Reserved Address */ + +/* *************** Bit definition for FDCAN_IE register *******************/ +#define FDCAN_IE_RF0NE_SHIFT (0U) +#define FDCAN_IE_RF0NE_MASK (0x1U << FDCAN_IE_RF0NE_SHIFT) /* 0x00000001 */ +#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_MASK /* Rx FIFO 0 New Message Enable */ +#define FDCAN_IE_RF0WE_SHIFT (1U) +#define FDCAN_IE_RF0WE_MASK (0x1U << FDCAN_IE_RF0WE_SHIFT) /* 0x00000002 */ +#define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_MASK /* Rx FIFO 0 Watermark Reached Enable */ +#define FDCAN_IE_RF0FE_SHIFT (2U) +#define FDCAN_IE_RF0FE_MASK (0x1U << FDCAN_IE_RF0FE_SHIFT) /* 0x00000004 */ +#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_MASK /* Rx FIFO 0 Full Enable */ +#define FDCAN_IE_RF0LE_SHIFT (3U) +#define FDCAN_IE_RF0LE_MASK (0x1U << FDCAN_IE_RF0LE_SHIFT) /* 0x00000008 */ +#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_MASK /* Rx FIFO 0 Message Lost Enable */ +#define FDCAN_IE_RF1NE_SHIFT (4U) +#define FDCAN_IE_RF1NE_MASK (0x1U << FDCAN_IE_RF1NE_SHIFT) /* 0x00000010 */ +#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_MASK /* Rx FIFO 1 New Message Enable */ +#define FDCAN_IE_RF1WE_SHIFT (5U) +#define FDCAN_IE_RF1WE_MASK (0x1U << FDCAN_IE_RF1WE_SHIFT) /* 0x00000020 */ +#define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_MASK /* Rx FIFO 1 Watermark Reached Enable */ +#define FDCAN_IE_RF1FE_SHIFT (6U) +#define FDCAN_IE_RF1FE_MASK (0x1U << FDCAN_IE_RF1FE_SHIFT) /* 0x00000040 */ +#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_MASK /* Rx FIFO 1 Full Enable */ +#define FDCAN_IE_RF1LE_SHIFT (7U) +#define FDCAN_IE_RF1LE_MASK (0x1U << FDCAN_IE_RF1LE_SHIFT) /* 0x00000080 */ +#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_MASK /* Rx FIFO 1 Message Lost Enable */ +#define FDCAN_IE_HPME_SHIFT (8U) +#define FDCAN_IE_HPME_MASK (0x1U << FDCAN_IE_HPME_SHIFT) /* 0x00000100 */ +#define FDCAN_IE_HPME FDCAN_IE_HPME_MASK /* High Priority Message Enable */ +#define FDCAN_IE_TCE_SHIFT (9U) +#define FDCAN_IE_TCE_MASK (0x1U << FDCAN_IE_TCE_SHIFT) /* 0x00000200 */ +#define FDCAN_IE_TCE FDCAN_IE_TCE_MASK /* Transmission Completed Enable */ +#define FDCAN_IE_TCFE_SHIFT (10U) +#define FDCAN_IE_TCFE_MASK (0x1U << FDCAN_IE_TCFE_SHIFT) /* 0x00000400 */ +#define FDCAN_IE_TCFE FDCAN_IE_TCFE_MASK /* Transmission Cancellation Finished Enable */ +#define FDCAN_IE_TFEE_SHIFT (11U) +#define FDCAN_IE_TFEE_MASK (0x1U << FDCAN_IE_TFEE_SHIFT) /* 0x00000800 */ +#define FDCAN_IE_TFEE FDCAN_IE_TFEE_MASK /* Tx FIFO Empty Enable */ +#define FDCAN_IE_TEFNE_SHIFT (12U) +#define FDCAN_IE_TEFNE_MASK (0x1U << FDCAN_IE_TEFNE_SHIFT) /* 0x00001000 */ +#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_MASK /* Tx Event FIFO New Entry Enable */ +#define FDCAN_IE_TEFWE_SHIFT (13U) +#define FDCAN_IE_TEFWE_MASK (0x1U << FDCAN_IE_TEFWE_SHIFT) /* 0x00002000 */ +#define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_MASK /* Tx Event FIFO Watermark Reached Enable */ +#define FDCAN_IE_TEFFE_SHIFT (14U) +#define FDCAN_IE_TEFFE_MASK (0x1U << FDCAN_IE_TEFFE_SHIFT) /* 0x00004000 */ +#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_MASK /* Tx Event FIFO Full Enable */ +#define FDCAN_IE_TEFLE_SHIFT (15U) +#define FDCAN_IE_TEFLE_MASK (0x1U << FDCAN_IE_TEFLE_SHIFT) /* 0x00008000 */ +#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_MASK /* Tx Event FIFO Element Lost Enable */ +#define FDCAN_IE_TSWE_SHIFT (16U) +#define FDCAN_IE_TSWE_MASK (0x1U << FDCAN_IE_TSWE_SHIFT) /* 0x00010000 */ +#define FDCAN_IE_TSWE FDCAN_IE_TSWE_MASK /* Timestamp Wraparound Enable */ +#define FDCAN_IE_MRAFE_SHIFT (17U) +#define FDCAN_IE_MRAFE_MASK (0x1U << FDCAN_IE_MRAFE_SHIFT) /* 0x00020000 */ +#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_MASK /* Message RAM Access Failure Enable */ +#define FDCAN_IE_TOOE_SHIFT (18U) +#define FDCAN_IE_TOOE_MASK (0x1U << FDCAN_IE_TOOE_SHIFT) /* 0x00040000 */ +#define FDCAN_IE_TOOE FDCAN_IE_TOOE_MASK /* Timeout Occurred Enable */ +#define FDCAN_IE_DRXE_SHIFT (19U) +#define FDCAN_IE_DRXE_MASK (0x1U << FDCAN_IE_DRXE_SHIFT) /* 0x00080000 */ +#define FDCAN_IE_DRXE FDCAN_IE_DRXE_MASK /* Message stored to Dedicated Rx Buffer Enable */ +#define FDCAN_IE_BECE_SHIFT (20U) +#define FDCAN_IE_BECE_MASK (0x1U << FDCAN_IE_BECE_SHIFT) /* 0x00100000 */ +#define FDCAN_IE_BECE FDCAN_IE_BECE_MASK /* Bit Error Corrected Interrupt Enable */ +#define FDCAN_IE_BEUE_SHIFT (21U) +#define FDCAN_IE_BEUE_MASK (0x1U << FDCAN_IE_BEUE_SHIFT) /* 0x00200000 */ +#define FDCAN_IE_BEUE FDCAN_IE_BEUE_MASK /* Bit Error Uncorrected Interrupt Enable */ +#define FDCAN_IE_ELOE_SHIFT (22U) +#define FDCAN_IE_ELOE_MASK (0x1U << FDCAN_IE_ELOE_SHIFT) /* 0x00400000 */ +#define FDCAN_IE_ELOE FDCAN_IE_ELOE_MASK /* Error Logging Overflow Enable */ +#define FDCAN_IE_EPE_SHIFT (23U) +#define FDCAN_IE_EPE_MASK (0x1U << FDCAN_IE_EPE_SHIFT) /* 0x00800000 */ +#define FDCAN_IE_EPE FDCAN_IE_EPE_MASK /* Error Passive Enable */ +#define FDCAN_IE_EWE_SHIFT (24U) +#define FDCAN_IE_EWE_MASK (0x1U << FDCAN_IE_EWE_SHIFT) /* 0x01000000 */ +#define FDCAN_IE_EWE FDCAN_IE_EWE_MASK /* Warning Status Enable */ +#define FDCAN_IE_BOE_SHIFT (25U) +#define FDCAN_IE_BOE_MASK (0x1U << FDCAN_IE_BOE_SHIFT) /* 0x02000000 */ +#define FDCAN_IE_BOE FDCAN_IE_BOE_MASK /* Bus_Off Status Enable */ +#define FDCAN_IE_WDIE_SHIFT (26U) +#define FDCAN_IE_WDIE_MASK (0x1U << FDCAN_IE_WDIE_SHIFT) /* 0x04000000 */ +#define FDCAN_IE_WDIE FDCAN_IE_WDIE_MASK /* Watchdog Interrupt Enable */ +#define FDCAN_IE_PEAE_SHIFT (27U) +#define FDCAN_IE_PEAE_MASK (0x1U << FDCAN_IE_PEAE_SHIFT) /* 0x08000000 */ +#define FDCAN_IE_PEAE FDCAN_IE_PEAE_MASK /* Protocol Error in Arbitration Phase Enable */ +#define FDCAN_IE_PEDE_SHIFT (28U) +#define FDCAN_IE_PEDE_MASK (0x1U << FDCAN_IE_PEDE_SHIFT) /* 0x10000000 */ +#define FDCAN_IE_PEDE FDCAN_IE_PEDE_MASK /* Protocol Error in Data Phase Enable */ +#define FDCAN_IE_ARAE_SHIFT (29U) +#define FDCAN_IE_ARAE_MASK (0x1U << FDCAN_IE_ARAE_SHIFT) /* 0x20000000 */ +#define FDCAN_IE_ARAE FDCAN_IE_ARAE_MASK /* Access to Reserved Address Enable */ + +/* *************** Bit definition for FDCAN_ILS register ******************/ +#define FDCAN_ILS_RF0NL_SHIFT (0U) +#define FDCAN_ILS_RF0NL_MASK (0x1U << FDCAN_ILS_RF0NL_SHIFT) /* 0x00000001 */ +#define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_MASK /* Rx FIFO 0 New Message Line */ +#define FDCAN_ILS_RF0WL_SHIFT (1U) +#define FDCAN_ILS_RF0WL_MASK (0x1U << FDCAN_ILS_RF0WL_SHIFT) /* 0x00000002 */ +#define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_MASK /* Rx FIFO 0 Watermark Reached Line */ +#define FDCAN_ILS_RF0FL_SHIFT (2U) +#define FDCAN_ILS_RF0FL_MASK (0x1U << FDCAN_ILS_RF0FL_SHIFT) /* 0x00000004 */ +#define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_MASK /* Rx FIFO 0 Full Line */ +#define FDCAN_ILS_RF0LL_SHIFT (3U) +#define FDCAN_ILS_RF0LL_MASK (0x1U << FDCAN_ILS_RF0LL_SHIFT) /* 0x00000008 */ +#define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_MASK /* Rx FIFO 0 Message Lost Line */ +#define FDCAN_ILS_RF1NL_SHIFT (4U) +#define FDCAN_ILS_RF1NL_MASK (0x1U << FDCAN_ILS_RF1NL_SHIFT) /* 0x00000010 */ +#define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_MASK /* Rx FIFO 1 New Message Line */ +#define FDCAN_ILS_RF1WL_SHIFT (5U) +#define FDCAN_ILS_RF1WL_MASK (0x1U << FDCAN_ILS_RF1WL_SHIFT) /* 0x00000020 */ +#define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_MASK /* Rx FIFO 1 Watermark Reached Line */ +#define FDCAN_ILS_RF1FL_SHIFT (6U) +#define FDCAN_ILS_RF1FL_MASK (0x1U << FDCAN_ILS_RF1FL_SHIFT) /* 0x00000040 */ +#define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_MASK /* Rx FIFO 1 Full Line */ +#define FDCAN_ILS_RF1LL_SHIFT (7U) +#define FDCAN_ILS_RF1LL_MASK (0x1U << FDCAN_ILS_RF1LL_SHIFT) /* 0x00000080 */ +#define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_MASK /* Rx FIFO 1 Message Lost Line */ +#define FDCAN_ILS_HPML_SHIFT (8U) +#define FDCAN_ILS_HPML_MASK (0x1U << FDCAN_ILS_HPML_SHIFT) /* 0x00000100 */ +#define FDCAN_ILS_HPML FDCAN_ILS_HPML_MASK /* High Priority Message Line */ +#define FDCAN_ILS_TCL_SHIFT (9U) +#define FDCAN_ILS_TCL_MASK (0x1U << FDCAN_ILS_TCL_SHIFT) /* 0x00000200 */ +#define FDCAN_ILS_TCL FDCAN_ILS_TCL_MASK /* Transmission Completed Line */ +#define FDCAN_ILS_TCFL_SHIFT (10U) +#define FDCAN_ILS_TCFL_MASK (0x1U << FDCAN_ILS_TCFL_SHIFT) /* 0x00000400 */ +#define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_MASK /* Transmission Cancellation Finished Line */ +#define FDCAN_ILS_TFEL_SHIFT (11U) +#define FDCAN_ILS_TFEL_MASK (0x1U << FDCAN_ILS_TFEL_SHIFT) /* 0x00000800 */ +#define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_MASK /* Tx FIFO Empty Line */ +#define FDCAN_ILS_TEFNL_SHIFT (12U) +#define FDCAN_ILS_TEFNL_MASK (0x1U << FDCAN_ILS_TEFNL_SHIFT) /* 0x00001000 */ +#define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_MASK /* Tx Event FIFO New Entry Line */ +#define FDCAN_ILS_TEFWL_SHIFT (13U) +#define FDCAN_ILS_TEFWL_MASK (0x1U << FDCAN_ILS_TEFWL_SHIFT) /* 0x00002000 */ +#define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_MASK /* Tx Event FIFO Watermark Reached Line */ +#define FDCAN_ILS_TEFFL_SHIFT (14U) +#define FDCAN_ILS_TEFFL_MASK (0x1U << FDCAN_ILS_TEFFL_SHIFT) /* 0x00004000 */ +#define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_MASK /* Tx Event FIFO Full Line */ +#define FDCAN_ILS_TEFLL_SHIFT (15U) +#define FDCAN_ILS_TEFLL_MASK (0x1U << FDCAN_ILS_TEFLL_SHIFT) /* 0x00008000 */ +#define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_MASK /* Tx Event FIFO Element Lost Line */ +#define FDCAN_ILS_TSWL_SHIFT (16U) +#define FDCAN_ILS_TSWL_MASK (0x1U << FDCAN_ILS_TSWL_SHIFT) /* 0x00010000 */ +#define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_MASK /* Timestamp Wraparound Line */ +#define FDCAN_ILS_MRAFE_SHIFT (17U) +#define FDCAN_ILS_MRAFE_MASK (0x1U << FDCAN_ILS_MRAFE_SHIFT) /* 0x00020000 */ +#define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_MASK /* Message RAM Access Failure Line */ +#define FDCAN_ILS_TOOE_SHIFT (18U) +#define FDCAN_ILS_TOOE_MASK (0x1U << FDCAN_ILS_TOOE_SHIFT) /* 0x00040000 */ +#define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_MASK /* Timeout Occurred Line */ +#define FDCAN_ILS_DRXE_SHIFT (19U) +#define FDCAN_ILS_DRXE_MASK (0x1U << FDCAN_ILS_DRXE_SHIFT) /* 0x00080000 */ +#define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_MASK /* Message stored to Dedicated Rx Buffer Line */ +#define FDCAN_ILS_BECE_SHIFT (20U) +#define FDCAN_ILS_BECE_MASK (0x1U << FDCAN_ILS_BECE_SHIFT) /* 0x00100000 */ +#define FDCAN_ILS_BECE FDCAN_ILS_BECE_MASK /* Bit Error Corrected Interrupt Line */ +#define FDCAN_ILS_BEUE_SHIFT (21U) +#define FDCAN_ILS_BEUE_MASK (0x1U << FDCAN_ILS_BEUE_SHIFT) /* 0x00200000 */ +#define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_MASK /* Bit Error Uncorrected Interrupt Line */ +#define FDCAN_ILS_ELOE_SHIFT (22U) +#define FDCAN_ILS_ELOE_MASK (0x1U << FDCAN_ILS_ELOE_SHIFT) /* 0x00400000 */ +#define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_MASK /* Error Logging Overflow Line */ +#define FDCAN_ILS_EPE_SHIFT (23U) +#define FDCAN_ILS_EPE_MASK (0x1U << FDCAN_ILS_EPE_SHIFT) /* 0x00800000 */ +#define FDCAN_ILS_EPE FDCAN_ILS_EPE_MASK /* Error Passive Line */ +#define FDCAN_ILS_EWE_SHIFT (24U) +#define FDCAN_ILS_EWE_MASK (0x1U << FDCAN_ILS_EWE_SHIFT) /* 0x01000000 */ +#define FDCAN_ILS_EWE FDCAN_ILS_EWE_MASK /* Warning Status Line */ +#define FDCAN_ILS_BOE_SHIFT (25U) +#define FDCAN_ILS_BOE_MASK (0x1U << FDCAN_ILS_BOE_SHIFT) /* 0x02000000 */ +#define FDCAN_ILS_BOE FDCAN_ILS_BOE_MASK /* Bus_Off Status Line */ +#define FDCAN_ILS_WDIE_SHIFT (26U) +#define FDCAN_ILS_WDIE_MASK (0x1U << FDCAN_ILS_WDIE_SHIFT) /* 0x04000000 */ +#define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_MASK /* Watchdog Interrupt Line */ +#define FDCAN_ILS_PEAE_SHIFT (27U) +#define FDCAN_ILS_PEAE_MASK (0x1U << FDCAN_ILS_PEAE_SHIFT) /* 0x08000000 */ +#define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_MASK /* Protocol Error in Arbitration Phase Line */ +#define FDCAN_ILS_PEDE_SHIFT (28U) +#define FDCAN_ILS_PEDE_MASK (0x1U << FDCAN_ILS_PEDE_SHIFT) /* 0x10000000 */ +#define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_MASK /* Protocol Error in Data Phase Line */ +#define FDCAN_ILS_ARAE_SHIFT (29U) +#define FDCAN_ILS_ARAE_MASK (0x1U << FDCAN_ILS_ARAE_SHIFT) /* 0x20000000 */ +#define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_MASK /* Access to Reserved Address Line */ + +/* *************** Bit definition for FDCAN_ILE register ******************/ +#define FDCAN_ILE_EINT0_SHIFT (0U) +#define FDCAN_ILE_EINT0_MASK (0x1U << FDCAN_ILE_EINT0_SHIFT) /* 0x00000001 */ +#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_MASK /* Enable Interrupt Line 0 */ +#define FDCAN_ILE_EINT1_SHIFT (1U) +#define FDCAN_ILE_EINT1_MASK (0x1U << FDCAN_ILE_EINT1_SHIFT) /* 0x00000002 */ +#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_MASK /* Enable Interrupt Line 1 */ + +/* *************** Bit definition for FDCAN_GFC register ******************/ +#define FDCAN_GFC_RRFE_SHIFT (0U) +#define FDCAN_GFC_RRFE_MASK (0x1U << FDCAN_GFC_RRFE_SHIFT) /* 0x00000001 */ +#define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_MASK /* Reject Remote Frames Extended */ +#define FDCAN_GFC_RRFS_SHIFT (1U) +#define FDCAN_GFC_RRFS_MASK (0x1U << FDCAN_GFC_RRFS_SHIFT) /* 0x00000002 */ +#define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_MASK /* Reject Remote Frames Standard */ +#define FDCAN_GFC_ANFE_SHIFT (2U) +#define FDCAN_GFC_ANFE_MASK (0x3U << FDCAN_GFC_ANFE_SHIFT) /* 0x0000000C */ +#define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_MASK /* Accept Non-matching Frames Extended */ +#define FDCAN_GFC_ANFS_SHIFT (4U) +#define FDCAN_GFC_ANFS_MASK (0x3U << FDCAN_GFC_ANFS_SHIFT) /* 0x00000030 */ +#define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_MASK /* Accept Non-matching Frames Standard */ + +/* *************** Bit definition for FDCAN_SIDFC register ****************/ +#define FDCAN_SIDFC_FLSSA_SHIFT (2U) +#define FDCAN_SIDFC_FLSSA_MASK (0x3FFFU << FDCAN_SIDFC_FLSSA_SHIFT) /* 0x0000FFFC */ +#define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_MASK /* Filter List Standard Start Address */ +#define FDCAN_SIDFC_LSS_SHIFT (16U) +#define FDCAN_SIDFC_LSS_MASK (0xFFU << FDCAN_SIDFC_LSS_SHIFT) /* 0x00FF0000 */ +#define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_MASK /* List Size Standard */ + +/* *************** Bit definition for FDCAN_XIDFC register ****************/ +#define FDCAN_XIDFC_FLESA_SHIFT (2U) +#define FDCAN_XIDFC_FLESA_MASK (0x3FFFU << FDCAN_XIDFC_FLESA_SHIFT) /* 0x0000FFFC */ +#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_MASK /* Filter List Standard Start Address */ +#define FDCAN_XIDFC_LSE_SHIFT (16U) +#define FDCAN_XIDFC_LSE_MASK (0xFFU << FDCAN_XIDFC_LSE_SHIFT) /* 0x00FF0000 */ +#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_MASK /* List Size Extended */ + +/* *************** Bit definition for FDCAN_XIDAM register ****************/ +#define FDCAN_XIDAM_EIDM_SHIFT (0U) +#define FDCAN_XIDAM_EIDM_MASK (0x1FFFFFFFU << FDCAN_XIDAM_EIDM_SHIFT) /* 0x1FFFFFFF */ +#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_MASK /* Extended ID Mask */ + +/* *************** Bit definition for FDCAN_HPMS register *****************/ +#define FDCAN_HPMS_BIDX_SHIFT (0U) +#define FDCAN_HPMS_BIDX_MASK (0x3FU << FDCAN_HPMS_BIDX_SHIFT) /* 0x0000003F */ +#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_MASK /* Buffer Index */ +#define FDCAN_HPMS_MSI_SHIFT (6U) +#define FDCAN_HPMS_MSI_MASK (0x3U << FDCAN_HPMS_MSI_SHIFT) /* 0x000000C0 */ +#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_MASK /* Message Storage Indicator */ +#define FDCAN_HPMS_FIDX_SHIFT (8U) +#define FDCAN_HPMS_FIDX_MASK (0x7FU << FDCAN_HPMS_FIDX_SHIFT) /* 0x00007F00 */ +#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_MASK /* Filter Index */ +#define FDCAN_HPMS_FLST_SHIFT (15U) +#define FDCAN_HPMS_FLST_MASK (0x1U << FDCAN_HPMS_FLST_SHIFT) /* 0x00008000 */ +#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_MASK /* Filter List */ + +/* *************** Bit definition for FDCAN_NDAT1 register ****************/ +#define FDCAN_NDAT1_ND0_SHIFT (0U) +#define FDCAN_NDAT1_ND0_MASK (0x1U << FDCAN_NDAT1_ND0_SHIFT) /* 0x00000001 */ +#define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_MASK /* New Data flag of Rx Buffer 0 */ +#define FDCAN_NDAT1_ND1_SHIFT (1U) +#define FDCAN_NDAT1_ND1_MASK (0x1U << FDCAN_NDAT1_ND1_SHIFT) /* 0x00000002 */ +#define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_MASK /* New Data flag of Rx Buffer 1 */ +#define FDCAN_NDAT1_ND2_SHIFT (2U) +#define FDCAN_NDAT1_ND2_MASK (0x1U << FDCAN_NDAT1_ND2_SHIFT) /* 0x00000004 */ +#define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_MASK /* New Data flag of Rx Buffer 2 */ +#define FDCAN_NDAT1_ND3_SHIFT (3U) +#define FDCAN_NDAT1_ND3_MASK (0x1U << FDCAN_NDAT1_ND3_SHIFT) /* 0x00000008 */ +#define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_MASK /* New Data flag of Rx Buffer 3 */ +#define FDCAN_NDAT1_ND4_SHIFT (4U) +#define FDCAN_NDAT1_ND4_MASK (0x1U << FDCAN_NDAT1_ND4_SHIFT) /* 0x00000010 */ +#define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_MASK /* New Data flag of Rx Buffer 4 */ +#define FDCAN_NDAT1_ND5_SHIFT (5U) +#define FDCAN_NDAT1_ND5_MASK (0x1U << FDCAN_NDAT1_ND5_SHIFT) /* 0x00000020 */ +#define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_MASK /* New Data flag of Rx Buffer 5 */ +#define FDCAN_NDAT1_ND6_SHIFT (6U) +#define FDCAN_NDAT1_ND6_MASK (0x1U << FDCAN_NDAT1_ND6_SHIFT) /* 0x00000040 */ +#define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_MASK /* New Data flag of Rx Buffer 6 */ +#define FDCAN_NDAT1_ND7_SHIFT (7U) +#define FDCAN_NDAT1_ND7_MASK (0x1U << FDCAN_NDAT1_ND7_SHIFT) /* 0x00000080 */ +#define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_MASK /* New Data flag of Rx Buffer 7 */ +#define FDCAN_NDAT1_ND8_SHIFT (8U) +#define FDCAN_NDAT1_ND8_MASK (0x1U << FDCAN_NDAT1_ND8_SHIFT) /* 0x00000100 */ +#define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_MASK /* New Data flag of Rx Buffer 8 */ +#define FDCAN_NDAT1_ND9_SHIFT (9U) +#define FDCAN_NDAT1_ND9_MASK (0x1U << FDCAN_NDAT1_ND9_SHIFT) /* 0x00000200 */ +#define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_MASK /* New Data flag of Rx Buffer 9 */ +#define FDCAN_NDAT1_ND10_SHIFT (10U) +#define FDCAN_NDAT1_ND10_MASK (0x1U << FDCAN_NDAT1_ND10_SHIFT) /* 0x00000400 */ +#define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_MASK /* New Data flag of Rx Buffer 10 */ +#define FDCAN_NDAT1_ND11_SHIFT (11U) +#define FDCAN_NDAT1_ND11_MASK (0x1U << FDCAN_NDAT1_ND11_SHIFT) /* 0x00000800 */ +#define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_MASK /* New Data flag of Rx Buffer 11 */ +#define FDCAN_NDAT1_ND12_SHIFT (12U) +#define FDCAN_NDAT1_ND12_MASK (0x1U << FDCAN_NDAT1_ND12_SHIFT) /* 0x00001000 */ +#define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_MASK /* New Data flag of Rx Buffer 12 */ +#define FDCAN_NDAT1_ND13_SHIFT (13U) +#define FDCAN_NDAT1_ND13_MASK (0x1U << FDCAN_NDAT1_ND13_SHIFT) /* 0x00002000 */ +#define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_MASK /* New Data flag of Rx Buffer 13 */ +#define FDCAN_NDAT1_ND14_SHIFT (14U) +#define FDCAN_NDAT1_ND14_MASK (0x1U << FDCAN_NDAT1_ND14_SHIFT) /* 0x00004000 */ +#define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_MASK /* New Data flag of Rx Buffer 14 */ +#define FDCAN_NDAT1_ND15_SHIFT (15U) +#define FDCAN_NDAT1_ND15_MASK (0x1U << FDCAN_NDAT1_ND15_SHIFT) /* 0x00008000 */ +#define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_MASK /* New Data flag of Rx Buffer 15 */ +#define FDCAN_NDAT1_ND16_SHIFT (16U) +#define FDCAN_NDAT1_ND16_MASK (0x1U << FDCAN_NDAT1_ND16_SHIFT) /* 0x00010000 */ +#define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_MASK /* New Data flag of Rx Buffer 16 */ +#define FDCAN_NDAT1_ND17_SHIFT (17U) +#define FDCAN_NDAT1_ND17_MASK (0x1U << FDCAN_NDAT1_ND17_SHIFT) /* 0x00020000 */ +#define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_MASK /* New Data flag of Rx Buffer 17 */ +#define FDCAN_NDAT1_ND18_SHIFT (18U) +#define FDCAN_NDAT1_ND18_MASK (0x1U << FDCAN_NDAT1_ND18_SHIFT) /* 0x00040000 */ +#define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_MASK /* New Data flag of Rx Buffer 18 */ +#define FDCAN_NDAT1_ND19_SHIFT (19U) +#define FDCAN_NDAT1_ND19_MASK (0x1U << FDCAN_NDAT1_ND19_SHIFT) /* 0x00080000 */ +#define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_MASK /* New Data flag of Rx Buffer 19 */ +#define FDCAN_NDAT1_ND20_SHIFT (20U) +#define FDCAN_NDAT1_ND20_MASK (0x1U << FDCAN_NDAT1_ND20_SHIFT) /* 0x00100000 */ +#define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_MASK /* New Data flag of Rx Buffer 20 */ +#define FDCAN_NDAT1_ND21_SHIFT (21U) +#define FDCAN_NDAT1_ND21_MASK (0x1U << FDCAN_NDAT1_ND21_SHIFT) /* 0x00200000 */ +#define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_MASK /* New Data flag of Rx Buffer 21 */ +#define FDCAN_NDAT1_ND22_SHIFT (22U) +#define FDCAN_NDAT1_ND22_MASK (0x1U << FDCAN_NDAT1_ND22_SHIFT) /* 0x00400000 */ +#define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_MASK /* New Data flag of Rx Buffer 22 */ +#define FDCAN_NDAT1_ND23_SHIFT (23U) +#define FDCAN_NDAT1_ND23_MASK (0x1U << FDCAN_NDAT1_ND23_SHIFT) /* 0x00800000 */ +#define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_MASK /* New Data flag of Rx Buffer 23 */ +#define FDCAN_NDAT1_ND24_SHIFT (24U) +#define FDCAN_NDAT1_ND24_MASK (0x1U << FDCAN_NDAT1_ND24_SHIFT) /* 0x01000000 */ +#define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_MASK /* New Data flag of Rx Buffer 24 */ +#define FDCAN_NDAT1_ND25_SHIFT (25U) +#define FDCAN_NDAT1_ND25_MASK (0x1U << FDCAN_NDAT1_ND25_SHIFT) /* 0x02000000 */ +#define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_MASK /* New Data flag of Rx Buffer 25 */ +#define FDCAN_NDAT1_ND26_SHIFT (26U) +#define FDCAN_NDAT1_ND26_MASK (0x1U << FDCAN_NDAT1_ND26_SHIFT) /* 0x04000000 */ +#define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_MASK /* New Data flag of Rx Buffer 26 */ +#define FDCAN_NDAT1_ND27_SHIFT (27U) +#define FDCAN_NDAT1_ND27_MASK (0x1U << FDCAN_NDAT1_ND27_SHIFT) /* 0x08000000 */ +#define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_MASK /* New Data flag of Rx Buffer 27 */ +#define FDCAN_NDAT1_ND28_SHIFT (28U) +#define FDCAN_NDAT1_ND28_MASK (0x1U << FDCAN_NDAT1_ND28_SHIFT) /* 0x10000000 */ +#define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_MASK /* New Data flag of Rx Buffer 28 */ +#define FDCAN_NDAT1_ND29_SHIFT (29U) +#define FDCAN_NDAT1_ND29_MASK (0x1U << FDCAN_NDAT1_ND29_SHIFT) /* 0x20000000 */ +#define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_MASK /* New Data flag of Rx Buffer 29 */ +#define FDCAN_NDAT1_ND30_SHIFT (30U) +#define FDCAN_NDAT1_ND30_MASK (0x1U << FDCAN_NDAT1_ND30_SHIFT) /* 0x40000000 */ +#define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_MASK /* New Data flag of Rx Buffer 30 */ +#define FDCAN_NDAT1_ND31_SHIFT (31U) +#define FDCAN_NDAT1_ND31_MASK (0x1U << FDCAN_NDAT1_ND31_SHIFT) /* 0x80000000 */ +#define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_MASK /* New Data flag of Rx Buffer 31 */ + +/* *************** Bit definition for FDCAN_NDAT2 register ****************/ +#define FDCAN_NDAT2_ND32_SHIFT (0U) +#define FDCAN_NDAT2_ND32_MASK (0x1U << FDCAN_NDAT2_ND32_SHIFT) /* 0x00000001 */ +#define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_MASK /* New Data flag of Rx Buffer 32 */ +#define FDCAN_NDAT2_ND33_SHIFT (1U) +#define FDCAN_NDAT2_ND33_MASK (0x1U << FDCAN_NDAT2_ND33_SHIFT) /* 0x00000002 */ +#define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_MASK /* New Data flag of Rx Buffer 33 */ +#define FDCAN_NDAT2_ND34_SHIFT (2U) +#define FDCAN_NDAT2_ND34_MASK (0x1U << FDCAN_NDAT2_ND34_SHIFT) /* 0x00000004 */ +#define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_MASK /* New Data flag of Rx Buffer 34 */ +#define FDCAN_NDAT2_ND35_SHIFT (3U) +#define FDCAN_NDAT2_ND35_MASK (0x1U << FDCAN_NDAT2_ND35_SHIFT) /* 0x00000008 */ +#define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_MASK /* New Data flag of Rx Buffer 35 */ +#define FDCAN_NDAT2_ND36_SHIFT (4U) +#define FDCAN_NDAT2_ND36_MASK (0x1U << FDCAN_NDAT2_ND36_SHIFT) /* 0x00000010 */ +#define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_MASK /* New Data flag of Rx Buffer 36 */ +#define FDCAN_NDAT2_ND37_SHIFT (5U) +#define FDCAN_NDAT2_ND37_MASK (0x1U << FDCAN_NDAT2_ND37_SHIFT) /* 0x00000020 */ +#define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_MASK /* New Data flag of Rx Buffer 37 */ +#define FDCAN_NDAT2_ND38_SHIFT (6U) +#define FDCAN_NDAT2_ND38_MASK (0x1U << FDCAN_NDAT2_ND38_SHIFT) /* 0x00000040 */ +#define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_MASK /* New Data flag of Rx Buffer 38 */ +#define FDCAN_NDAT2_ND39_SHIFT (7U) +#define FDCAN_NDAT2_ND39_MASK (0x1U << FDCAN_NDAT2_ND39_SHIFT) /* 0x00000080 */ +#define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_MASK /* New Data flag of Rx Buffer 39 */ +#define FDCAN_NDAT2_ND40_SHIFT (8U) +#define FDCAN_NDAT2_ND40_MASK (0x1U << FDCAN_NDAT2_ND40_SHIFT) /* 0x00000100 */ +#define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_MASK /* New Data flag of Rx Buffer 40 */ +#define FDCAN_NDAT2_ND41_SHIFT (9U) +#define FDCAN_NDAT2_ND41_MASK (0x1U << FDCAN_NDAT2_ND41_SHIFT) /* 0x00000200 */ +#define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_MASK /* New Data flag of Rx Buffer 41 */ +#define FDCAN_NDAT2_ND42_SHIFT (10U) +#define FDCAN_NDAT2_ND42_MASK (0x1U << FDCAN_NDAT2_ND42_SHIFT) /* 0x00000400 */ +#define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_MASK /* New Data flag of Rx Buffer 42 */ +#define FDCAN_NDAT2_ND43_SHIFT (11U) +#define FDCAN_NDAT2_ND43_MASK (0x1U << FDCAN_NDAT2_ND43_SHIFT) /* 0x00000800 */ +#define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_MASK /* New Data flag of Rx Buffer 43 */ +#define FDCAN_NDAT2_ND44_SHIFT (12U) +#define FDCAN_NDAT2_ND44_MASK (0x1U << FDCAN_NDAT2_ND44_SHIFT) /* 0x00001000 */ +#define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_MASK /* New Data flag of Rx Buffer 44 */ +#define FDCAN_NDAT2_ND45_SHIFT (13U) +#define FDCAN_NDAT2_ND45_MASK (0x1U << FDCAN_NDAT2_ND45_SHIFT) /* 0x00002000 */ +#define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_MASK /* New Data flag of Rx Buffer 45 */ +#define FDCAN_NDAT2_ND46_SHIFT (14U) +#define FDCAN_NDAT2_ND46_MASK (0x1U << FDCAN_NDAT2_ND46_SHIFT) /* 0x00004000 */ +#define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_MASK /* New Data flag of Rx Buffer 46 */ +#define FDCAN_NDAT2_ND47_SHIFT (15U) +#define FDCAN_NDAT2_ND47_MASK (0x1U << FDCAN_NDAT2_ND47_SHIFT) /* 0x00008000 */ +#define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_MASK /* New Data flag of Rx Buffer 47 */ +#define FDCAN_NDAT2_ND48_SHIFT (16U) +#define FDCAN_NDAT2_ND48_MASK (0x1U << FDCAN_NDAT2_ND48_SHIFT) /* 0x00010000 */ +#define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_MASK /* New Data flag of Rx Buffer 48 */ +#define FDCAN_NDAT2_ND49_SHIFT (17U) +#define FDCAN_NDAT2_ND49_MASK (0x1U << FDCAN_NDAT2_ND49_SHIFT) /* 0x00020000 */ +#define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_MASK /* New Data flag of Rx Buffer 49 */ +#define FDCAN_NDAT2_ND50_SHIFT (18U) +#define FDCAN_NDAT2_ND50_MASK (0x1U << FDCAN_NDAT2_ND50_SHIFT) /* 0x00040000 */ +#define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_MASK /* New Data flag of Rx Buffer 50 */ +#define FDCAN_NDAT2_ND51_SHIFT (19U) +#define FDCAN_NDAT2_ND51_MASK (0x1U << FDCAN_NDAT2_ND51_SHIFT) /* 0x00080000 */ +#define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_MASK /* New Data flag of Rx Buffer 51 */ +#define FDCAN_NDAT2_ND52_SHIFT (20U) +#define FDCAN_NDAT2_ND52_MASK (0x1U << FDCAN_NDAT2_ND52_SHIFT) /* 0x00100000 */ +#define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_MASK /* New Data flag of Rx Buffer 52 */ +#define FDCAN_NDAT2_ND53_SHIFT (21U) +#define FDCAN_NDAT2_ND53_MASK (0x1U << FDCAN_NDAT2_ND53_SHIFT) /* 0x00200000 */ +#define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_MASK /* New Data flag of Rx Buffer 53 */ +#define FDCAN_NDAT2_ND54_SHIFT (22U) +#define FDCAN_NDAT2_ND54_MASK (0x1U << FDCAN_NDAT2_ND54_SHIFT) /* 0x00400000 */ +#define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_MASK /* New Data flag of Rx Buffer 54 */ +#define FDCAN_NDAT2_ND55_SHIFT (23U) +#define FDCAN_NDAT2_ND55_MASK (0x1U << FDCAN_NDAT2_ND55_SHIFT) /* 0x00800000 */ +#define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_MASK /* New Data flag of Rx Buffer 55 */ +#define FDCAN_NDAT2_ND56_SHIFT (24U) +#define FDCAN_NDAT2_ND56_MASK (0x1U << FDCAN_NDAT2_ND56_SHIFT) /* 0x01000000 */ +#define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_MASK /* New Data flag of Rx Buffer 56 */ +#define FDCAN_NDAT2_ND57_SHIFT (25U) +#define FDCAN_NDAT2_ND57_MASK (0x1U << FDCAN_NDAT2_ND57_SHIFT) /* 0x02000000 */ +#define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_MASK /* New Data flag of Rx Buffer 57 */ +#define FDCAN_NDAT2_ND58_SHIFT (26U) +#define FDCAN_NDAT2_ND58_MASK (0x1U << FDCAN_NDAT2_ND58_SHIFT) /* 0x04000000 */ +#define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_MASK /* New Data flag of Rx Buffer 58 */ +#define FDCAN_NDAT2_ND59_SHIFT (27U) +#define FDCAN_NDAT2_ND59_MASK (0x1U << FDCAN_NDAT2_ND59_SHIFT) /* 0x08000000 */ +#define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_MASK /* New Data flag of Rx Buffer 59 */ +#define FDCAN_NDAT2_ND60_SHIFT (28U) +#define FDCAN_NDAT2_ND60_MASK (0x1U << FDCAN_NDAT2_ND60_SHIFT) /* 0x10000000 */ +#define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_MASK /* New Data flag of Rx Buffer 60 */ +#define FDCAN_NDAT2_ND61_SHIFT (29U) +#define FDCAN_NDAT2_ND61_MASK (0x1U << FDCAN_NDAT2_ND61_SHIFT) /* 0x20000000 */ +#define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_MASK /* New Data flag of Rx Buffer 61 */ +#define FDCAN_NDAT2_ND62_SHIFT (30U) +#define FDCAN_NDAT2_ND62_MASK (0x1U << FDCAN_NDAT2_ND62_SHIFT) /* 0x40000000 */ +#define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_MASK /* New Data flag of Rx Buffer 62 */ +#define FDCAN_NDAT2_ND63_SHIFT (31U) +#define FDCAN_NDAT2_ND63_MASK (0x1U << FDCAN_NDAT2_ND63_SHIFT) /* 0x80000000 */ +#define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_MASK /* New Data flag of Rx Buffer 63 */ + +/* *************** Bit definition for FDCAN_RXF0C register ****************/ +#define FDCAN_RXF0C_F0SA_SHIFT (2U) +#define FDCAN_RXF0C_F0SA_MASK (0x3FFFU << FDCAN_RXF0C_F0SA_SHIFT) /* 0x0000FFFC */ +#define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_MASK /* Rx FIFO 0 Start Address */ +#define FDCAN_RXF0C_F0S_SHIFT (16U) +#define FDCAN_RXF0C_F0S_MASK (0x7FU << FDCAN_RXF0C_F0S_SHIFT) /* 0x007F0000 */ +#define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_MASK /* Number of Rx FIFO 0 elements */ +#define FDCAN_RXF0C_F0WM_SHIFT (24U) +#define FDCAN_RXF0C_F0WM_MASK (0x7FU << FDCAN_RXF0C_F0WM_SHIFT) /* 0x7F000000 */ +#define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_MASK /* FIFO 0 Watermark */ +#define FDCAN_RXF0C_F0OM_SHIFT (31U) +#define FDCAN_RXF0C_F0OM_MASK (0x1U << FDCAN_RXF0C_F0OM_SHIFT) /* 0x80000000 */ +#define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_MASK /* FIFO 0 Operation Mode */ + +/* *************** Bit definition for FDCAN_RXF0S register ****************/ +#define FDCAN_RXF0S_F0FL_SHIFT (0U) +#define FDCAN_RXF0S_F0FL_MASK (0x7FU << FDCAN_RXF0S_F0FL_SHIFT) /* 0x0000007F */ +#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_MASK /* Rx FIFO 0 Fill Level */ +#define FDCAN_RXF0S_F0GI_SHIFT (8U) +#define FDCAN_RXF0S_F0GI_MASK (0x3FU << FDCAN_RXF0S_F0GI_SHIFT) /* 0x00003F00 */ +#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_MASK /* Rx FIFO 0 Get Index */ +#define FDCAN_RXF0S_F0PI_SHIFT (16U) +#define FDCAN_RXF0S_F0PI_MASK (0x3FU << FDCAN_RXF0S_F0PI_SHIFT) /* 0x003F0000 */ +#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_MASK /* Rx FIFO 0 Put Index */ +#define FDCAN_RXF0S_F0F_SHIFT (24U) +#define FDCAN_RXF0S_F0F_MASK (0x1U << FDCAN_RXF0S_F0F_SHIFT) /* 0x01000000 */ +#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_MASK /* Rx FIFO 0 Full */ +#define FDCAN_RXF0S_RF0L_SHIFT (25U) +#define FDCAN_RXF0S_RF0L_MASK (0x1U << FDCAN_RXF0S_RF0L_SHIFT) /* 0x02000000 */ +#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_MASK /* Rx FIFO 0 Message Lost */ + +/* *************** Bit definition for FDCAN_RXF0A register ****************/ +#define FDCAN_RXF0A_F0AI_SHIFT (0U) +#define FDCAN_RXF0A_F0AI_MASK (0x3FU << FDCAN_RXF0A_F0AI_SHIFT) /* 0x0000003F */ +#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_MASK /* Rx FIFO 0 Acknowledge Index */ + +/* *************** Bit definition for FDCAN_RXBC register *****************/ +#define FDCAN_RXBC_RBSA_SHIFT (2U) +#define FDCAN_RXBC_RBSA_MASK (0x3FU << FDCAN_RXBC_RBSA_SHIFT) /* 0x000000FC */ +#define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_MASK /* Rx Buffer Start Address */ + +/* *************** Bit definition for FDCAN_RXF1C register ****************/ +#define FDCAN_RXF1C_F1SA_SHIFT (2U) +#define FDCAN_RXF1C_F1SA_MASK (0x3FU << FDCAN_RXF1C_F1SA_SHIFT) /* 0x000000FC */ +#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_MASK /* Rx FIFO 1 Start Address */ +#define FDCAN_RXF1C_F1S_SHIFT (16U) +#define FDCAN_RXF1C_F1S_MASK (0x7FU << FDCAN_RXF1C_F1S_SHIFT) /* 0x007F0000 */ +#define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_MASK /* Number of Rx FIFO 1 elements */ +#define FDCAN_RXF1C_F1WM_SHIFT (24U) +#define FDCAN_RXF1C_F1WM_MASK (0x7FU << FDCAN_RXF1C_F1WM_SHIFT) /* 0x7F000000 */ +#define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_MASK /* Rx FIFO 1 Watermark */ +#define FDCAN_RXF1C_F1OM_SHIFT (31U) +#define FDCAN_RXF1C_F1OM_MASK (0x1U << FDCAN_RXF1C_F1OM_SHIFT) /* 0x80000000 */ +#define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_MASK /* FIFO 1 Operation Mode */ + +/* *************** Bit definition for FDCAN_RXF1S register ****************/ +#define FDCAN_RXF1S_F1FL_SHIFT (0U) +#define FDCAN_RXF1S_F1FL_MASK (0x7FU << FDCAN_RXF1S_F1FL_SHIFT) /* 0x0000007F */ +#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_MASK /* Rx FIFO 1 Fill Level */ +#define FDCAN_RXF1S_F1GI_SHIFT (8U) +#define FDCAN_RXF1S_F1GI_MASK (0x3FU << FDCAN_RXF1S_F1GI_SHIFT) /* 0x00003F00 */ +#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_MASK /* Rx FIFO 1 Get Index */ +#define FDCAN_RXF1S_F1PI_SHIFT (16U) +#define FDCAN_RXF1S_F1PI_MASK (0x3FU << FDCAN_RXF1S_F1PI_SHIFT) /* 0x003F0000 */ +#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_MASK /* Rx FIFO 1 Put Index */ +#define FDCAN_RXF1S_F1F_SHIFT (24U) +#define FDCAN_RXF1S_F1F_MASK (0x1U << FDCAN_RXF1S_F1F_SHIFT) /* 0x01000000 */ +#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_MASK /* Rx FIFO 1 Full */ +#define FDCAN_RXF1S_RF1L_SHIFT (25U) +#define FDCAN_RXF1S_RF1L_MASK (0x1U << FDCAN_RXF1S_RF1L_SHIFT) /* 0x02000000 */ +#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_MASK /* Rx FIFO 1 Message Lost */ + +/* *************** Bit definition for FDCAN_RXF1A register ****************/ +#define FDCAN_RXF1A_F1AI_SHIFT (0U) +#define FDCAN_RXF1A_F1AI_MASK (0x3FU << FDCAN_RXF1A_F1AI_SHIFT) /* 0x0000003F */ +#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_MASK /* Rx FIFO 1 Acknowledge Index */ + +/* *************** Bit definition for FDCAN_RXESC register ****************/ +#define FDCAN_RXESC_F0DS_SHIFT (0U) +#define FDCAN_RXESC_F0DS_MASK (0x7U << FDCAN_RXESC_F0DS_SHIFT) /* 0x00000007 */ +#define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_MASK /* Rx FIFO 1 Data Field Size */ +#define FDCAN_RXESC_F1DS_SHIFT (4U) +#define FDCAN_RXESC_F1DS_MASK (0x7U << FDCAN_RXESC_F1DS_SHIFT) /* 0x00000070 */ +#define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_MASK /* Rx FIFO 0 Data Field Size */ +#define FDCAN_RXESC_RBDS_SHIFT (8U) +#define FDCAN_RXESC_RBDS_MASK (0x7U << FDCAN_RXESC_RBDS_SHIFT) /* 0x00000700 */ +#define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_MASK /* Rx Buffer Data Field Size */ + +/* *************** Bit definition for FDCAN_TXBC register *****************/ +#define FDCAN_TXBC_TBSA_SHIFT (2U) +#define FDCAN_TXBC_TBSA_MASK (0x3FFFU << FDCAN_TXBC_TBSA_SHIFT) /* 0x0000FFFC */ +#define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_MASK /* Tx Buffers Start Address */ +#define FDCAN_TXBC_NDTB_SHIFT (16U) +#define FDCAN_TXBC_NDTB_MASK (0x3FU << FDCAN_TXBC_NDTB_SHIFT) /* 0x003F0000 */ +#define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_MASK /* Number of Dedicated Transmit Buffers */ +#define FDCAN_TXBC_TFQS_SHIFT (24U) +#define FDCAN_TXBC_TFQS_MASK (0x3FU << FDCAN_TXBC_TFQS_SHIFT) /* 0x3F000000 */ +#define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_MASK /* Transmit FIFO/Queue Size */ +#define FDCAN_TXBC_TFQM_SHIFT (30U) +#define FDCAN_TXBC_TFQM_MASK (0x1U << FDCAN_TXBC_TFQM_SHIFT) /* 0x40000000 */ +#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_MASK /* Tx FIFO/Queue Mode */ + +/* *************** Bit definition for FDCAN_TXFQS register ****************/ +#define FDCAN_TXFQS_TFFL_SHIFT (0U) +#define FDCAN_TXFQS_TFFL_MASK (0x3FU << FDCAN_TXFQS_TFFL_SHIFT) /* 0x0000003F */ +#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_MASK /* Tx FIFO Free Level */ +#define FDCAN_TXFQS_TFGI_SHIFT (8U) +#define FDCAN_TXFQS_TFGI_MASK (0x1FU << FDCAN_TXFQS_TFGI_SHIFT) /* 0x00001F00 */ +#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_MASK /* Tx FIFO Get Index */ +#define FDCAN_TXFQS_TFQPI_SHIFT (16U) +#define FDCAN_TXFQS_TFQPI_MASK (0x1FU << FDCAN_TXFQS_TFQPI_SHIFT) /* 0x001F0000 */ +#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_MASK /* Tx FIFO/Queue Put Index */ +#define FDCAN_TXFQS_TFQF_SHIFT (21U) +#define FDCAN_TXFQS_TFQF_MASK (0x1U << FDCAN_TXFQS_TFQF_SHIFT) /* 0x00200000 */ +#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_MASK /* Tx FIFO/Queue Full */ + +/* *************** Bit definition for FDCAN_TXESC register ****************/ +#define FDCAN_TXESC_TBDS_SHIFT (0U) +#define FDCAN_TXESC_TBDS_MASK (0x7U << FDCAN_TXESC_TBDS_SHIFT) /* 0x00000007 */ +#define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_MASK /* Tx Buffer Data Field Size */ + +/* *************** Bit definition for FDCAN_TXBRP register ****************/ +#define FDCAN_TXBRP_TRP_SHIFT (0U) +#define FDCAN_TXBRP_TRP_MASK (0xFFFFFFFFU << FDCAN_TXBRP_TRP_SHIFT) /* 0xFFFFFFFF */ +#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_MASK /* Transmission Request Pending */ + +/* *************** Bit definition for FDCAN_TXBAR register ****************/ +#define FDCAN_TXBAR_AR_SHIFT (0U) +#define FDCAN_TXBAR_AR_MASK (0xFFFFFFFFU << FDCAN_TXBAR_AR_SHIFT) /* 0xFFFFFFFF */ +#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_MASK /* Add Request */ + +/* *************** Bit definition for FDCAN_TXBCR register ****************/ +#define FDCAN_TXBCR_CR_SHIFT (0U) +#define FDCAN_TXBCR_CR_MASK (0xFFFFFFFFU << FDCAN_TXBCR_CR_SHIFT) /* 0xFFFFFFFF */ +#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_MASK /* Cancellation Request */ + +/* *************** Bit definition for FDCAN_TXBTO register ****************/ +#define FDCAN_TXBTO_TO_SHIFT (0U) +#define FDCAN_TXBTO_TO_MASK (0xFFFFFFFFU << FDCAN_TXBTO_TO_SHIFT) /* 0xFFFFFFFF */ +#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_MASK /* Transmission Occurred */ + +/* *************** Bit definition for FDCAN_TXBCF register ****************/ +#define FDCAN_TXBCF_CF_SHIFT (0U) +#define FDCAN_TXBCF_CF_MASK (0xFFFFFFFFU << FDCAN_TXBCF_CF_SHIFT) /* 0xFFFFFFFF */ +#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_MASK /* Cancellation Finished */ + +/* *************** Bit definition for FDCAN_TXBTIE register ***************/ +#define FDCAN_TXBTIE_TIE_SHIFT (0U) +#define FDCAN_TXBTIE_TIE_MASK (0xFFFFFFFFU << FDCAN_TXBTIE_TIE_SHIFT) /* 0xFFFFFFFF */ +#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_MASK /* Transmission Interrupt Enable */ + +/* *************** Bit definition for FDCAN_ TXBCIE register **************/ +#define FDCAN_TXBCIE_CF_SHIFT (0U) +#define FDCAN_TXBCIE_CF_MASK (0xFFFFFFFFU << FDCAN_TXBCIE_CF_SHIFT) /* 0xFFFFFFFF */ +#define FDCAN_TXBCIE_CF FDCAN_TXBCIE_CF_MASK /* Cancellation Finished Interrupt Enable */ + +/* *************** Bit definition for FDCAN_TXEFC register ****************/ +#define FDCAN_TXEFC_EFSA_SHIFT (2U) +#define FDCAN_TXEFC_EFSA_MASK (0x3FU << FDCAN_TXEFC_EFSA_SHIFT) /* 0x000000FC */ +#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_MASK /* Event FIFO Start Address */ +#define FDCAN_TXEFC_EFS_SHIFT (8U) +#define FDCAN_TXEFC_EFS_MASK (0x3FU << FDCAN_TXEFC_EFS_SHIFT) /* 0x00003F00 */ +#define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_MASK /* Event FIFO Size */ +#define FDCAN_TXEFC_EFWM_SHIFT (24U) +#define FDCAN_TXEFC_EFWM_MASK (0x3FU << FDCAN_TXEFC_EFWM_SHIFT) /* 0x3F000000 */ +#define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_MASK /* Event FIFO Watermark */ + +/* *************** Bit definition for FDCAN_TXEFS register ****************/ +#define FDCAN_TXEFS_EFFL_SHIFT (0U) +#define FDCAN_TXEFS_EFFL_MASK (0x3FU << FDCAN_TXEFS_EFFL_SHIFT) /* 0x0000003F */ +#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_MASK /* Event FIFO Fill Level */ +#define FDCAN_TXEFS_EFGI_SHIFT (8U) +#define FDCAN_TXEFS_EFGI_MASK (0x1FU << FDCAN_TXEFS_EFGI_SHIFT) /* 0x00001F00 */ +#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_MASK /* Event FIFO Get Index */ +#define FDCAN_TXEFS_EFPI_SHIFT (16U) +#define FDCAN_TXEFS_EFPI_MASK (0x1FU << FDCAN_TXEFS_EFPI_SHIFT) /* 0x001F0000 */ +#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_MASK /* Event FIFO Put Index */ +#define FDCAN_TXEFS_EFF_SHIFT (24U) +#define FDCAN_TXEFS_EFF_MASK (0x1U << FDCAN_TXEFS_EFF_SHIFT) /* 0x01000000 */ +#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_MASK /* Event FIFO Full */ +#define FDCAN_TXEFS_TEFL_SHIFT (25U) +#define FDCAN_TXEFS_TEFL_MASK (0x1U << FDCAN_TXEFS_TEFL_SHIFT) /* 0x02000000 */ +#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_MASK /* Tx Event FIFO Element Lost */ + +/* *************** Bit definition for FDCAN_TXEFA register ****************/ +#define FDCAN_TXEFA_EFAI_SHIFT (0U) +#define FDCAN_TXEFA_EFAI_MASK (0x1FU << FDCAN_TXEFA_EFAI_SHIFT) /* 0x0000001F */ +#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_MASK /* Event FIFO Acknowledge Index */ + +/* *************** Bit definition for FDCAN_TTTMC register ****************/ +#define FDCAN_TTTMC_TMSA_SHIFT (2U) +#define FDCAN_TTTMC_TMSA_MASK (0x3FFFU << FDCAN_TTTMC_TMSA_SHIFT) /* 0x0000FFFC */ +#define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_MASK /* Trigger Memory Start Address */ +#define FDCAN_TTTMC_TME_SHIFT (16U) +#define FDCAN_TTTMC_TME_MASK (0x7FU << FDCAN_TTTMC_TME_SHIFT) /* 0x007F0000 */ +#define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_MASK /* Trigger Memory Elements */ + +/* *************** Bit definition for FDCAN_TTRMC register ****************/ +#define FDCAN_TTRMC_RID_SHIFT (0U) +#define FDCAN_TTRMC_RID_MASK (0x1FFFFFFFU << FDCAN_TTRMC_RID_SHIFT) /* 0x1FFFFFFF */ +#define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_MASK /* Reference Identifier */ +#define FDCAN_TTRMC_XTD_SHIFT (30U) +#define FDCAN_TTRMC_XTD_MASK (0x1U << FDCAN_TTRMC_XTD_SHIFT) /* 0x40000000 */ +#define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_MASK /* Extended Identifier */ +#define FDCAN_TTRMC_RMPS_SHIFT (31U) +#define FDCAN_TTRMC_RMPS_MASK (0x1U << FDCAN_TTRMC_RMPS_SHIFT) /* 0x80000000 */ +#define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_MASK /* Reference Message Payload Select */ + +/* *************** Bit definition for FDCAN_TTOCF register ****************/ +#define FDCAN_TTOCF_OM_SHIFT (0U) +#define FDCAN_TTOCF_OM_MASK (0x3U << FDCAN_TTOCF_OM_SHIFT) /* 0x00000003 */ +#define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_MASK /* Operation Mode */ +#define FDCAN_TTOCF_GEN_SHIFT (3U) +#define FDCAN_TTOCF_GEN_MASK (0x1U << FDCAN_TTOCF_GEN_SHIFT) /* 0x00000008 */ +#define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_MASK /* Gap Enable */ +#define FDCAN_TTOCF_TM_SHIFT (4U) +#define FDCAN_TTOCF_TM_MASK (0x1U << FDCAN_TTOCF_TM_SHIFT) /* 0x00000010 */ +#define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_MASK /* Time Master */ +#define FDCAN_TTOCF_LDSDL_SHIFT (5U) +#define FDCAN_TTOCF_LDSDL_MASK (0x7U << FDCAN_TTOCF_LDSDL_SHIFT) /* 0x000000E0 */ +#define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_MASK /* LD of Synchronization Deviation Limit */ +#define FDCAN_TTOCF_IRTO_SHIFT (8U) +#define FDCAN_TTOCF_IRTO_MASK (0x7FU << FDCAN_TTOCF_IRTO_SHIFT) /* 0x00007F00 */ +#define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_MASK /* Initial Reference Trigger Offset */ +#define FDCAN_TTOCF_EECS_SHIFT (15U) +#define FDCAN_TTOCF_EECS_MASK (0x1U << FDCAN_TTOCF_EECS_SHIFT) /* 0x00008000 */ +#define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_MASK /* Enable External Clock Synchronization */ +#define FDCAN_TTOCF_AWL_SHIFT (16U) +#define FDCAN_TTOCF_AWL_MASK (0xFFU << FDCAN_TTOCF_AWL_SHIFT) /* 0x00FF0000 */ +#define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_MASK /* Application Watchdog Limit */ +#define FDCAN_TTOCF_EGTF_SHIFT (24U) +#define FDCAN_TTOCF_EGTF_MASK (0x1U << FDCAN_TTOCF_EGTF_SHIFT) /* 0x01000000 */ +#define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_MASK /* Enable Global Time Filtering */ +#define FDCAN_TTOCF_ECC_SHIFT (25U) +#define FDCAN_TTOCF_ECC_MASK (0x1U << FDCAN_TTOCF_ECC_SHIFT) /* 0x02000000 */ +#define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_MASK /* Enable Clock Calibration */ +#define FDCAN_TTOCF_EVTP_SHIFT (26U) +#define FDCAN_TTOCF_EVTP_MASK (0x1U << FDCAN_TTOCF_EVTP_SHIFT) /* 0x04000000 */ +#define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_MASK /* Event Trigger Polarity */ + +/* *************** Bit definition for FDCAN_TTMLM register ****************/ +#define FDCAN_TTMLM_CCM_SHIFT (0U) +#define FDCAN_TTMLM_CCM_MASK (0x3FU << FDCAN_TTMLM_CCM_SHIFT) /* 0x0000003F */ +#define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_MASK /* Cycle Count Max */ +#define FDCAN_TTMLM_CSS_SHIFT (6U) +#define FDCAN_TTMLM_CSS_MASK (0x3U << FDCAN_TTMLM_CSS_SHIFT) /* 0x000000C0 */ +#define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_MASK /* Cycle Start Synchronization */ +#define FDCAN_TTMLM_TXEW_SHIFT (8U) +#define FDCAN_TTMLM_TXEW_MASK (0xFU << FDCAN_TTMLM_TXEW_SHIFT) /* 0x00000F00 */ +#define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_MASK /* Tx Enable Window */ +#define FDCAN_TTMLM_ENTT_SHIFT (16U) +#define FDCAN_TTMLM_ENTT_MASK (0xFFFU << FDCAN_TTMLM_ENTT_SHIFT) /* 0x0FFF0000 */ +#define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_MASK /* Expected Number of Tx Triggers */ + +/* *************** Bit definition for FDCAN_TURCF register ****************/ +#define FDCAN_TURCF_NCL_SHIFT (0U) +#define FDCAN_TURCF_NCL_MASK (0xFFFFU << FDCAN_TURCF_NCL_SHIFT) /* 0x0000FFFF */ +#define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_MASK /* Numerator Configuration Low */ +#define FDCAN_TURCF_DC_SHIFT (16U) +#define FDCAN_TURCF_DC_MASK (0x3FFFU << FDCAN_TURCF_DC_SHIFT) /* 0x3FFF0000 */ +#define FDCAN_TURCF_DC FDCAN_TURCF_DC_MASK /* Denominator Configuration */ +#define FDCAN_TURCF_ELT_SHIFT (31U) +#define FDCAN_TURCF_ELT_MASK (0x1U << FDCAN_TURCF_ELT_SHIFT) /* 0x80000000 */ +#define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_MASK /* Enable Local Time */ + +/* *************** Bit definition for FDCAN_TTOCN register ****************/ +#define FDCAN_TTOCN_SGT_SHIFT (0U) +#define FDCAN_TTOCN_SGT_MASK (0x1U << FDCAN_TTOCN_SGT_SHIFT) /* 0x00000001 */ +#define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_MASK /* Set Global time */ +#define FDCAN_TTOCN_ECS_SHIFT (1U) +#define FDCAN_TTOCN_ECS_MASK (0x1U << FDCAN_TTOCN_ECS_SHIFT) /* 0x00000002 */ +#define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_MASK /* External Clock Synchronization */ +#define FDCAN_TTOCN_SWP_SHIFT (2U) +#define FDCAN_TTOCN_SWP_MASK (0x1U << FDCAN_TTOCN_SWP_SHIFT) /* 0x00000004 */ +#define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_MASK /* Stop Watch Polarity */ +#define FDCAN_TTOCN_SWS_SHIFT (3U) +#define FDCAN_TTOCN_SWS_MASK (0x3U << FDCAN_TTOCN_SWS_SHIFT) /* 0x00000018 */ +#define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_MASK /* Stop Watch Source */ +#define FDCAN_TTOCN_RTIE_SHIFT (5U) +#define FDCAN_TTOCN_RTIE_MASK (0x1U << FDCAN_TTOCN_RTIE_SHIFT) /* 0x00000020 */ +#define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_MASK /* Register Time Mark Interrupt Pulse Enable */ +#define FDCAN_TTOCN_TMC_SHIFT (6U) +#define FDCAN_TTOCN_TMC_MASK (0x3U << FDCAN_TTOCN_TMC_SHIFT) /* 0x000000C0 */ +#define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_MASK /* Register Time Mark Compare */ +#define FDCAN_TTOCN_TTIE_SHIFT (8U) +#define FDCAN_TTOCN_TTIE_MASK (0x1U << FDCAN_TTOCN_TTIE_SHIFT) /* 0x00000100 */ +#define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_MASK /* Trigger Time Mark Interrupt Pulse Enable */ +#define FDCAN_TTOCN_GCS_SHIFT (9U) +#define FDCAN_TTOCN_GCS_MASK (0x1U << FDCAN_TTOCN_GCS_SHIFT) /* 0x00000200 */ +#define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_MASK /* Gap Control Select */ +#define FDCAN_TTOCN_FGP_SHIFT (10U) +#define FDCAN_TTOCN_FGP_MASK (0x1U << FDCAN_TTOCN_FGP_SHIFT) /* 0x00000400 */ +#define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_MASK /* Finish Gap */ +#define FDCAN_TTOCN_TMG_SHIFT (11U) +#define FDCAN_TTOCN_TMG_MASK (0x1U << FDCAN_TTOCN_TMG_SHIFT) /* 0x00000800 */ +#define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_MASK /* Time Mark Gap */ +#define FDCAN_TTOCN_NIG_SHIFT (12U) +#define FDCAN_TTOCN_NIG_MASK (0x1U << FDCAN_TTOCN_NIG_SHIFT) /* 0x00001000 */ +#define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_MASK /* Next is Gap */ +#define FDCAN_TTOCN_ESCN_SHIFT (13U) +#define FDCAN_TTOCN_ESCN_MASK (0x1U << FDCAN_TTOCN_ESCN_SHIFT) /* 0x00002000 */ +#define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_MASK /* External Synchronization Control */ +#define FDCAN_TTOCN_LCKC_SHIFT (15U) +#define FDCAN_TTOCN_LCKC_MASK (0x1U << FDCAN_TTOCN_LCKC_SHIFT) /* 0x00008000 */ +#define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_MASK /* TT Operation Control Register Locked */ + +/* *************** Bit definition for FDCAN_TTGTP register ****************/ +#define FDCAN_TTGTP_TP_SHIFT (0U) +#define FDCAN_TTGTP_TP_MASK (0xFFFFU << FDCAN_TTGTP_TP_SHIFT) /* 0x0000FFFF */ +#define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_MASK /* Time Preset */ +#define FDCAN_TTGTP_CTP_SHIFT (16U) +#define FDCAN_TTGTP_CTP_MASK (0xFFFFU << FDCAN_TTGTP_CTP_SHIFT) /* 0xFFFF0000 */ +#define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_MASK /* Cycle Time Target Phase */ + +/* *************** Bit definition for FDCAN_TTTMK register ****************/ +#define FDCAN_TTTMK_TM_SHIFT (0U) +#define FDCAN_TTTMK_TM_MASK (0xFFFFU << FDCAN_TTTMK_TM_SHIFT) /* 0x0000FFFF */ +#define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_MASK /* Time Mark */ +#define FDCAN_TTTMK_TICC_SHIFT (16U) +#define FDCAN_TTTMK_TICC_MASK (0x7FU << FDCAN_TTTMK_TICC_SHIFT) /* 0x007F0000 */ +#define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_MASK /* Time Mark Cycle Code */ +#define FDCAN_TTTMK_LCKM_SHIFT (31U) +#define FDCAN_TTTMK_LCKM_MASK (0x1U << FDCAN_TTTMK_LCKM_SHIFT) /* 0x80000000 */ +#define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_MASK /* TT Time Mark Register Locked */ + +/* *************** Bit definition for FDCAN_TTIR register *****************/ +#define FDCAN_TTIR_SBC_SHIFT (0U) +#define FDCAN_TTIR_SBC_MASK (0x1U << FDCAN_TTIR_SBC_SHIFT) /* 0x00000001 */ +#define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_MASK /* Start of Basic Cycle */ +#define FDCAN_TTIR_SMC_SHIFT (1U) +#define FDCAN_TTIR_SMC_MASK (0x1U << FDCAN_TTIR_SMC_SHIFT) /* 0x00000002 */ +#define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_MASK /* Start of Matrix Cycle */ +#define FDCAN_TTIR_CSM_SHIFT (2U) +#define FDCAN_TTIR_CSM_MASK (0x1U << FDCAN_TTIR_CSM_SHIFT) /* 0x00000004 */ +#define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_MASK /* Change of Synchronization Mode */ +#define FDCAN_TTIR_SOG_SHIFT (3U) +#define FDCAN_TTIR_SOG_MASK (0x1U << FDCAN_TTIR_SOG_SHIFT) /* 0x00000008 */ +#define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_MASK /* Start of Gap */ +#define FDCAN_TTIR_RTMI_SHIFT (4U) +#define FDCAN_TTIR_RTMI_MASK (0x1U << FDCAN_TTIR_RTMI_SHIFT) /* 0x00000010 */ +#define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_MASK /* Register Time Mark Interrupt */ +#define FDCAN_TTIR_TTMI_SHIFT (5U) +#define FDCAN_TTIR_TTMI_MASK (0x1U << FDCAN_TTIR_TTMI_SHIFT) /* 0x00000020 */ +#define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_MASK /* Trigger Time Mark Event Internal */ +#define FDCAN_TTIR_SWE_SHIFT (6U) +#define FDCAN_TTIR_SWE_MASK (0x1U << FDCAN_TTIR_SWE_SHIFT) /* 0x00000040 */ +#define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_MASK /* Stop Watch Event */ +#define FDCAN_TTIR_GTW_SHIFT (7U) +#define FDCAN_TTIR_GTW_MASK (0x1U << FDCAN_TTIR_GTW_SHIFT) /* 0x00000080 */ +#define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_MASK /* Global Time Wrap */ +#define FDCAN_TTIR_GTD_SHIFT (8U) +#define FDCAN_TTIR_GTD_MASK (0x1U << FDCAN_TTIR_GTD_SHIFT) /* 0x00000100 */ +#define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_MASK /* Global Time Discontinuity */ +#define FDCAN_TTIR_GTE_SHIFT (9U) +#define FDCAN_TTIR_GTE_MASK (0x1U << FDCAN_TTIR_GTE_SHIFT) /* 0x00000200 */ +#define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_MASK /* Global Time Error */ +#define FDCAN_TTIR_TXU_SHIFT (10U) +#define FDCAN_TTIR_TXU_MASK (0x1U << FDCAN_TTIR_TXU_SHIFT) /* 0x00000400 */ +#define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_MASK /* Tx Count Underflow */ +#define FDCAN_TTIR_TXO_SHIFT (11U) +#define FDCAN_TTIR_TXO_MASK (0x1U << FDCAN_TTIR_TXO_SHIFT) /* 0x00000800 */ +#define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_MASK /* Tx Count Overflow */ +#define FDCAN_TTIR_SE1_SHIFT (12U) +#define FDCAN_TTIR_SE1_MASK (0x1U << FDCAN_TTIR_SE1_SHIFT) /* 0x00001000 */ +#define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_MASK /* Scheduling Error 1 */ +#define FDCAN_TTIR_SE2_SHIFT (13U) +#define FDCAN_TTIR_SE2_MASK (0x1U << FDCAN_TTIR_SE2_SHIFT) /* 0x00002000 */ +#define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_MASK /* Scheduling Error 2 */ +#define FDCAN_TTIR_ELC_SHIFT (14U) +#define FDCAN_TTIR_ELC_MASK (0x1U << FDCAN_TTIR_ELC_SHIFT) /* 0x00004000 */ +#define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_MASK /* Error Level Changed */ +#define FDCAN_TTIR_IWT_SHIFT (15U) +#define FDCAN_TTIR_IWT_MASK (0x1U << FDCAN_TTIR_IWT_SHIFT) /* 0x00008000 */ +#define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_MASK /* Initialization Watch Trigger */ +#define FDCAN_TTIR_WT_SHIFT (16U) +#define FDCAN_TTIR_WT_MASK (0x1U << FDCAN_TTIR_WT_SHIFT) /* 0x00010000 */ +#define FDCAN_TTIR_WT FDCAN_TTIR_WT_MASK /* Watch Trigger */ +#define FDCAN_TTIR_AW_SHIFT (17U) +#define FDCAN_TTIR_AW_MASK (0x1U << FDCAN_TTIR_AW_SHIFT) /* 0x00020000 */ +#define FDCAN_TTIR_AW FDCAN_TTIR_AW_MASK /* Application Watchdog */ +#define FDCAN_TTIR_CER_SHIFT (18U) +#define FDCAN_TTIR_CER_MASK (0x1U << FDCAN_TTIR_CER_SHIFT) /* 0x00040000 */ +#define FDCAN_TTIR_CER FDCAN_TTIR_CER_MASK /* Configuration Error */ + +/* *************** Bit definition for FDCAN_TTIE register *****************/ +#define FDCAN_TTIE_SBCE_SHIFT (0U) +#define FDCAN_TTIE_SBCE_MASK (0x1U << FDCAN_TTIE_SBCE_SHIFT) /* 0x00000001 */ +#define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_MASK /* Start of Basic Cycle Interrupt Enable */ +#define FDCAN_TTIE_SMCE_SHIFT (1U) +#define FDCAN_TTIE_SMCE_MASK (0x1U << FDCAN_TTIE_SMCE_SHIFT) /* 0x00000002 */ +#define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_MASK /* Start of Matrix Cycle Interrupt Enable */ +#define FDCAN_TTIE_CSME_SHIFT (2U) +#define FDCAN_TTIE_CSME_MASK (0x1U << FDCAN_TTIE_CSME_SHIFT) /* 0x00000004 */ +#define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_MASK /* Change of Synchronization Mode Interrupt Enable */ +#define FDCAN_TTIE_SOGE_SHIFT (3U) +#define FDCAN_TTIE_SOGE_MASK (0x1U << FDCAN_TTIE_SOGE_SHIFT) /* 0x00000008 */ +#define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_MASK /* Start of Gap Interrupt Enable */ +#define FDCAN_TTIE_RTMIE_SHIFT (4U) +#define FDCAN_TTIE_RTMIE_MASK (0x1U << FDCAN_TTIE_RTMIE_SHIFT) /* 0x00000010 */ +#define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_MASK /* Register Time Mark Interrupt Interrupt Enable */ +#define FDCAN_TTIE_TTMIE_SHIFT (5U) +#define FDCAN_TTIE_TTMIE_MASK (0x1U << FDCAN_TTIE_TTMIE_SHIFT) /* 0x00000020 */ +#define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_MASK /* Trigger Time Mark Event Internal Interrupt Enable */ +#define FDCAN_TTIE_SWEE_SHIFT (6U) +#define FDCAN_TTIE_SWEE_MASK (0x1U << FDCAN_TTIE_SWEE_SHIFT) /* 0x00000040 */ +#define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_MASK /* Stop Watch Event Interrupt Enable */ +#define FDCAN_TTIE_GTWE_SHIFT (7U) +#define FDCAN_TTIE_GTWE_MASK (0x1U << FDCAN_TTIE_GTWE_SHIFT) /* 0x00000080 */ +#define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_MASK /* Global Time Wrap Interrupt Enable */ +#define FDCAN_TTIE_GTDE_SHIFT (8U) +#define FDCAN_TTIE_GTDE_MASK (0x1U << FDCAN_TTIE_GTDE_SHIFT) /* 0x00000100 */ +#define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_MASK /* Global Time Discontinuity Interrupt Enable */ +#define FDCAN_TTIE_GTEE_SHIFT (9U) +#define FDCAN_TTIE_GTEE_MASK (0x1U << FDCAN_TTIE_GTEE_SHIFT) /* 0x00000200 */ +#define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_MASK /* Global Time Error Interrupt Enable */ +#define FDCAN_TTIE_TXUE_SHIFT (10U) +#define FDCAN_TTIE_TXUE_MASK (0x1U << FDCAN_TTIE_TXUE_SHIFT) /* 0x00000400 */ +#define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_MASK /* Tx Count Underflow Interrupt Enable */ +#define FDCAN_TTIE_TXOE_SHIFT (11U) +#define FDCAN_TTIE_TXOE_MASK (0x1U << FDCAN_TTIE_TXOE_SHIFT) /* 0x00000800 */ +#define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_MASK /* Tx Count Overflow Interrupt Enable */ +#define FDCAN_TTIE_SE1E_SHIFT (12U) +#define FDCAN_TTIE_SE1E_MASK (0x1U << FDCAN_TTIE_SE1E_SHIFT) /* 0x00001000 */ +#define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_MASK /* Scheduling Error 1 Interrupt Enable */ +#define FDCAN_TTIE_SE2E_SHIFT (13U) +#define FDCAN_TTIE_SE2E_MASK (0x1U << FDCAN_TTIE_SE2E_SHIFT) /* 0x00002000 */ +#define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_MASK /* Scheduling Error 2 Interrupt Enable */ +#define FDCAN_TTIE_ELCE_SHIFT (14U) +#define FDCAN_TTIE_ELCE_MASK (0x1U << FDCAN_TTIE_ELCE_SHIFT) /* 0x00004000 */ +#define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_MASK /* Error Level Changed Interrupt Enable */ +#define FDCAN_TTIE_IWTE_SHIFT (15U) +#define FDCAN_TTIE_IWTE_MASK (0x1U << FDCAN_TTIE_IWTE_SHIFT) /* 0x00008000 */ +#define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_MASK /* Initialization Watch Trigger Interrupt Enable */ +#define FDCAN_TTIE_WTE_SHIFT (16U) +#define FDCAN_TTIE_WTE_MASK (0x1U << FDCAN_TTIE_WTE_SHIFT) /* 0x00010000 */ +#define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_MASK /* Watch Trigger Interrupt Enable */ +#define FDCAN_TTIE_AWE_SHIFT (17U) +#define FDCAN_TTIE_AWE_MASK (0x1U << FDCAN_TTIE_AWE_SHIFT) /* 0x00020000 */ +#define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_MASK /* Application Watchdog Interrupt Enable */ +#define FDCAN_TTIE_CERE_SHIFT (18U) +#define FDCAN_TTIE_CERE_MASK (0x1U << FDCAN_TTIE_CERE_SHIFT) /* 0x00040000 */ +#define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_MASK /* Configuration Error Interrupt Enable */ + +/* *************** Bit definition for FDCAN_TTILS register ****************/ +#define FDCAN_TTILS_SBCS_SHIFT (0U) +#define FDCAN_TTILS_SBCS_MASK (0x1U << FDCAN_TTILS_SBCS_SHIFT) /* 0x00000001 */ +#define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_MASK /* Start of Basic Cycle Interrupt Line */ +#define FDCAN_TTILS_SMCS_SHIFT (1U) +#define FDCAN_TTILS_SMCS_MASK (0x1U << FDCAN_TTILS_SMCS_SHIFT) /* 0x00000002 */ +#define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_MASK /* Start of Matrix Cycle Interrupt Line */ +#define FDCAN_TTILS_CSMS_SHIFT (2U) +#define FDCAN_TTILS_CSMS_MASK (0x1U << FDCAN_TTILS_CSMS_SHIFT) /* 0x00000004 */ +#define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_MASK /* Change of Synchronization Mode Interrupt Line */ +#define FDCAN_TTILS_SOGS_SHIFT (3U) +#define FDCAN_TTILS_SOGS_MASK (0x1U << FDCAN_TTILS_SOGS_SHIFT) /* 0x00000008 */ +#define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_MASK /* Start of Gap Interrupt Line */ +#define FDCAN_TTILS_RTMIS_SHIFT (4U) +#define FDCAN_TTILS_RTMIS_MASK (0x1U << FDCAN_TTILS_RTMIS_SHIFT) /* 0x00000010 */ +#define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_MASK /* Register Time Mark Interrupt Interrupt Line */ +#define FDCAN_TTILS_TTMIS_SHIFT (5U) +#define FDCAN_TTILS_TTMIS_MASK (0x1U << FDCAN_TTILS_TTMIS_SHIFT) /* 0x00000020 */ +#define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_MASK /* Trigger Time Mark Event Internal Interrupt Line */ +#define FDCAN_TTILS_SWES_SHIFT (6U) +#define FDCAN_TTILS_SWES_MASK (0x1U << FDCAN_TTILS_SWES_SHIFT) /* 0x00000040 */ +#define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_MASK /* Stop Watch Event Interrupt Line */ +#define FDCAN_TTILS_GTWS_SHIFT (7U) +#define FDCAN_TTILS_GTWS_MASK (0x1U << FDCAN_TTILS_GTWS_SHIFT) /* 0x00000080 */ +#define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_MASK /* Global Time Wrap Interrupt Line */ +#define FDCAN_TTILS_GTDS_SHIFT (8U) +#define FDCAN_TTILS_GTDS_MASK (0x1U << FDCAN_TTILS_GTDS_SHIFT) /* 0x00000100 */ +#define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_MASK /* Global Time Discontinuity Interrupt Line */ +#define FDCAN_TTILS_GTES_SHIFT (9U) +#define FDCAN_TTILS_GTES_MASK (0x1U << FDCAN_TTILS_GTES_SHIFT) /* 0x00000200 */ +#define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_MASK /* Global Time Error Interrupt Line */ +#define FDCAN_TTILS_TXUS_SHIFT (10U) +#define FDCAN_TTILS_TXUS_MASK (0x1U << FDCAN_TTILS_TXUS_SHIFT) /* 0x00000400 */ +#define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_MASK /* Tx Count Underflow Interrupt Line */ +#define FDCAN_TTILS_TXOS_SHIFT (11U) +#define FDCAN_TTILS_TXOS_MASK (0x1U << FDCAN_TTILS_TXOS_SHIFT) /* 0x00000800 */ +#define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_MASK /* Tx Count Overflow Interrupt Line */ +#define FDCAN_TTILS_SE1S_SHIFT (12U) +#define FDCAN_TTILS_SE1S_MASK (0x1U << FDCAN_TTILS_SE1S_SHIFT) /* 0x00001000 */ +#define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_MASK /* Scheduling Error 1 Interrupt Line */ +#define FDCAN_TTILS_SE2S_SHIFT (13U) +#define FDCAN_TTILS_SE2S_MASK (0x1U << FDCAN_TTILS_SE2S_SHIFT) /* 0x00002000 */ +#define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_MASK /* Scheduling Error 2 Interrupt Line */ +#define FDCAN_TTILS_ELCS_SHIFT (14U) +#define FDCAN_TTILS_ELCS_MASK (0x1U << FDCAN_TTILS_ELCS_SHIFT) /* 0x00004000 */ +#define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_MASK /* Error Level Changed Interrupt Line */ +#define FDCAN_TTILS_IWTS_SHIFT (15U) +#define FDCAN_TTILS_IWTS_MASK (0x1U << FDCAN_TTILS_IWTS_SHIFT) /* 0x00008000 */ +#define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_MASK /* Initialization Watch Trigger Interrupt Line */ +#define FDCAN_TTILS_WTS_SHIFT (16U) +#define FDCAN_TTILS_WTS_MASK (0x1U << FDCAN_TTILS_WTS_SHIFT) /* 0x00010000 */ +#define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_MASK /* Watch Trigger Interrupt Line */ +#define FDCAN_TTILS_AWS_SHIFT (17U) +#define FDCAN_TTILS_AWS_MASK (0x1U << FDCAN_TTILS_AWS_SHIFT) /* 0x00020000 */ +#define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_MASK /* Application Watchdog Interrupt Line */ +#define FDCAN_TTILS_CERS_SHIFT (18U) +#define FDCAN_TTILS_CERS_MASK (0x1U << FDCAN_TTILS_CERS_SHIFT) /* 0x00040000 */ +#define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_MASK /* Configuration Error Interrupt Line */ + +/* *************** Bit definition for FDCAN_TTOST register ****************/ +#define FDCAN_TTOST_EL_SHIFT (0U) +#define FDCAN_TTOST_EL_MASK (0x3U << FDCAN_TTOST_EL_SHIFT) /* 0x00000003 */ +#define FDCAN_TTOST_EL FDCAN_TTOST_EL_MASK /* Error Level */ +#define FDCAN_TTOST_MS_SHIFT (2U) +#define FDCAN_TTOST_MS_MASK (0x3U << FDCAN_TTOST_MS_SHIFT) /* 0x0000000C */ +#define FDCAN_TTOST_MS FDCAN_TTOST_MS_MASK /* Master State */ +#define FDCAN_TTOST_SYS_SHIFT (4U) +#define FDCAN_TTOST_SYS_MASK (0x3U << FDCAN_TTOST_SYS_SHIFT) /* 0x00000030 */ +#define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_MASK /* Synchronization State */ +#define FDCAN_TTOST_QGTP_SHIFT (6U) +#define FDCAN_TTOST_QGTP_MASK (0x1U << FDCAN_TTOST_QGTP_SHIFT) /* 0x00000040 */ +#define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_MASK /* Quality of Global Time Phase */ +#define FDCAN_TTOST_QCS_SHIFT (7U) +#define FDCAN_TTOST_QCS_MASK (0x1U << FDCAN_TTOST_QCS_SHIFT) /* 0x00000080 */ +#define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_MASK /* Quality of Clock Speed */ +#define FDCAN_TTOST_RTO_SHIFT (8U) +#define FDCAN_TTOST_RTO_MASK (0xFFU << FDCAN_TTOST_RTO_SHIFT) /* 0x0000FF00 */ +#define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_MASK /* Reference Trigger Offset */ +#define FDCAN_TTOST_WGTD_SHIFT (22U) +#define FDCAN_TTOST_WGTD_MASK (0x1U << FDCAN_TTOST_WGTD_SHIFT) /* 0x00400000 */ +#define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_MASK /* Wait for Global Time Discontinuity */ +#define FDCAN_TTOST_GFI_SHIFT (23U) +#define FDCAN_TTOST_GFI_MASK (0x1U << FDCAN_TTOST_GFI_SHIFT) /* 0x00800000 */ +#define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_MASK /* Gap Finished Indicator */ +#define FDCAN_TTOST_TMP_SHIFT (24U) +#define FDCAN_TTOST_TMP_MASK (0x7U << FDCAN_TTOST_TMP_SHIFT) /* 0x07000000 */ +#define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_MASK /* Time Master Priority */ +#define FDCAN_TTOST_GSI_SHIFT (27U) +#define FDCAN_TTOST_GSI_MASK (0x1U << FDCAN_TTOST_GSI_SHIFT) /* 0x08000000 */ +#define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_MASK /* Gap Started Indicator */ +#define FDCAN_TTOST_WFE_SHIFT (28U) +#define FDCAN_TTOST_WFE_MASK (0x1U << FDCAN_TTOST_WFE_SHIFT) /* 0x10000000 */ +#define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_MASK /* Wait for Event */ +#define FDCAN_TTOST_AWE_SHIFT (29U) +#define FDCAN_TTOST_AWE_MASK (0x1U << FDCAN_TTOST_AWE_SHIFT) /* 0x20000000 */ +#define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_MASK /* Application Watchdog Event */ +#define FDCAN_TTOST_WECS_SHIFT (30U) +#define FDCAN_TTOST_WECS_MASK (0x1U << FDCAN_TTOST_WECS_SHIFT) /* 0x40000000 */ +#define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_MASK /* Wait for External Clock Synchronization */ +#define FDCAN_TTOST_SPL_SHIFT (31U) +#define FDCAN_TTOST_SPL_MASK (0x1U << FDCAN_TTOST_SPL_SHIFT) /* 0x80000000 */ +#define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_MASK /* Schedule Phase Lock */ + +/* *************** Bit definition for FDCAN_TURNA register ****************/ +#define FDCAN_TURNA_NAV_SHIFT (0U) +#define FDCAN_TURNA_NAV_MASK (0x3FFFFU << FDCAN_TURNA_NAV_SHIFT) /* 0x0003FFFF */ +#define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_MASK /* Numerator Actual Value */ + +/* *************** Bit definition for FDCAN_TTLGT register ****************/ +#define FDCAN_TTLGT_LT_SHIFT (0U) +#define FDCAN_TTLGT_LT_MASK (0xFFFFU << FDCAN_TTLGT_LT_SHIFT) /* 0x0000FFFF */ +#define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_MASK /* Local Time */ +#define FDCAN_TTLGT_GT_SHIFT (16U) +#define FDCAN_TTLGT_GT_MASK (0xFFFFU << FDCAN_TTLGT_GT_SHIFT) /* 0xFFFF0000 */ +#define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_MASK /* Global Time */ + +/* *************** Bit definition for FDCAN_TTCTC register ****************/ +#define FDCAN_TTCTC_CT_SHIFT (0U) +#define FDCAN_TTCTC_CT_MASK (0xFFFFU << FDCAN_TTCTC_CT_SHIFT) /* 0x0000FFFF */ +#define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_MASK /* Cycle Time */ +#define FDCAN_TTCTC_CC_SHIFT (16U) +#define FDCAN_TTCTC_CC_MASK (0x3FU << FDCAN_TTCTC_CC_SHIFT) /* 0x003F0000 */ +#define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_MASK /* Cycle Count */ + +/* *************** Bit definition for FDCAN_TTCPT register ****************/ +#define FDCAN_TTCPT_CCV_SHIFT (0U) +#define FDCAN_TTCPT_CCV_MASK (0x3FU << FDCAN_TTCPT_CCV_SHIFT) /* 0x0000003F */ +#define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_MASK /* Cycle Count Value */ +#define FDCAN_TTCPT_SWV_SHIFT (16U) +#define FDCAN_TTCPT_SWV_MASK (0xFFFFU << FDCAN_TTCPT_SWV_SHIFT) /* 0xFFFF0000 */ +#define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_MASK /* Stop Watch Value */ + +/* *************** Bit definition for FDCAN_TTCSM register ****************/ +#define FDCAN_TTCSM_CSM_SHIFT (0U) +#define FDCAN_TTCSM_CSM_MASK (0xFFFFU << FDCAN_TTCSM_CSM_SHIFT) /* 0x0000FFFF */ +#define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_MASK /* Cycle Sync Mark */ + +/* *************** Bit definition for FDCAN_TTTS register *****************/ +#define FDCAN_TTTS_SWTSEL_SHIFT (0U) +#define FDCAN_TTTS_SWTSEL_MASK (0x3U << FDCAN_TTTS_SWTSEL_SHIFT) /* 0x00000003 */ +#define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_MASK /* Stop watch trigger input selection */ +#define FDCAN_TTTS_EVTSEL_SHIFT (4U) +#define FDCAN_TTTS_EVTSEL_MASK (0x3U << FDCAN_TTTS_EVTSEL_SHIFT) /* 0x00000030 */ +#define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_MASK /* Event trigger input selection */ + +/* ************************************************************************** + * * + * FDCANCCU (Clock Calibration unit) * + * * + * **************************************************************************/ + +/* *************** Bit definition for FDCANCCU_CREL register **************/ +#define FDCANCCU_CREL_DAY_SHIFT (0U) +#define FDCANCCU_CREL_DAY_MASK (0xFFU << FDCANCCU_CREL_DAY_SHIFT) /* 0x000000FF */ +#define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_MASK /* Timestamp Day */ +#define FDCANCCU_CREL_MON_SHIFT (8U) +#define FDCANCCU_CREL_MON_MASK (0xFFU << FDCANCCU_CREL_MON_SHIFT) /* 0x0000FF00 */ +#define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_MASK /* Timestamp Month */ +#define FDCANCCU_CREL_YEAR_SHIFT (16U) +#define FDCANCCU_CREL_YEAR_MASK (0xFU << FDCANCCU_CREL_YEAR_SHIFT) /* 0x000F0000 */ +#define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_MASK /* Timestamp Year */ +#define FDCANCCU_CREL_SUBSTEP_SHIFT (20U) +#define FDCANCCU_CREL_SUBSTEP_MASK (0xFU << FDCANCCU_CREL_SUBSTEP_SHIFT) /* 0x00F00000 */ +#define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_MASK /* Sub-step of Core release */ +#define FDCANCCU_CREL_STEP_SHIFT (24U) +#define FDCANCCU_CREL_STEP_MASK (0xFU << FDCANCCU_CREL_STEP_SHIFT) /* 0x0F000000 */ +#define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_MASK /* Step of Core release */ +#define FDCANCCU_CREL_REL_SHIFT (28U) +#define FDCANCCU_CREL_REL_MASK (0xFU << FDCANCCU_CREL_REL_SHIFT) /* 0xF0000000 */ +#define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_MASK /* Core release */ + +/* *************** Bit definition for FDCANCCU_CCFG register **************/ +#define FDCANCCU_CCFG_TQBT_SHIFT (0U) +#define FDCANCCU_CCFG_TQBT_MASK (0x1FU << FDCANCCU_CCFG_TQBT_SHIFT) /* 0x0000001F */ +#define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_MASK /* Time Quanta per Bit Time */ +#define FDCANCCU_CCFG_BCC_SHIFT (6U) +#define FDCANCCU_CCFG_BCC_MASK (0x1U << FDCANCCU_CCFG_BCC_SHIFT) /* 0x00000040 */ +#define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_MASK /* Bypass Clock Calibration */ +#define FDCANCCU_CCFG_CFL_SHIFT (7U) +#define FDCANCCU_CCFG_CFL_MASK (0x1U << FDCANCCU_CCFG_CFL_SHIFT) /* 0x00000080 */ +#define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_MASK /* Calibration Field Length */ +#define FDCANCCU_CCFG_OCPM_SHIFT (8U) +#define FDCANCCU_CCFG_OCPM_MASK (0xFFU << FDCANCCU_CCFG_OCPM_SHIFT) /* 0x0000FF00 */ +#define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_MASK /* Oscillator Clock Periods Minimum */ +#define FDCANCCU_CCFG_CDIV_SHIFT (16U) +#define FDCANCCU_CCFG_CDIV_MASK (0xFU << FDCANCCU_CCFG_CDIV_SHIFT) /* 0x000F0000 */ +#define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_MASK /* Clock Divider */ +#define FDCANCCU_CCFG_SWR_SHIFT (31U) +#define FDCANCCU_CCFG_SWR_MASK (0x1U << FDCANCCU_CCFG_SWR_SHIFT) /* 0x80000000 */ +#define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_MASK /* Software Reset */ + +/* *************** Bit definition for FDCANCCU_CSTAT register *************/ +#define FDCANCCU_CSTAT_OCPC_SHIFT (0U) +#define FDCANCCU_CSTAT_OCPC_MASK (0x3FFFFU << FDCANCCU_CSTAT_OCPC_SHIFT) /* 0x0003FFFF */ +#define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_MASK /* Oscillator Clock Period Counter */ +#define FDCANCCU_CSTAT_TQC_SHIFT (18U) +#define FDCANCCU_CSTAT_TQC_MASK (0x7FFU << FDCANCCU_CSTAT_TQC_SHIFT) /* 0x1FFC0000 */ +#define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_MASK /* Time Quanta Counter */ +#define FDCANCCU_CSTAT_CALS_SHIFT (30U) +#define FDCANCCU_CSTAT_CALS_MASK (0x3U << FDCANCCU_CSTAT_CALS_SHIFT) /* 0xC0000000 */ +#define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_MASK /* Calibration State */ + +/* **************** Bit definition for FDCANCCU_CWD register **************/ +#define FDCANCCU_CWD_WDC_SHIFT (0U) +#define FDCANCCU_CWD_WDC_MASK (0xFFFFU << FDCANCCU_CWD_WDC_SHIFT) /* 0x0000FFFF */ +#define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_MASK /* Watchdog Configuration */ +#define FDCANCCU_CWD_WDV_SHIFT (16U) +#define FDCANCCU_CWD_WDV_MASK (0xFFFFU << FDCANCCU_CWD_WDV_SHIFT) /* 0xFFFF0000 */ +#define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_MASK /* Watchdog Value */ + +/* **************** Bit definition for FDCANCCU_IR register ***************/ +#define FDCANCCU_IR_CWE_SHIFT (0U) +#define FDCANCCU_IR_CWE_MASK (0x1U << FDCANCCU_IR_CWE_SHIFT) /* 0x00000001 */ +#define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_MASK /* Calibration Watchdog Event */ +#define FDCANCCU_IR_CSC_SHIFT (1U) +#define FDCANCCU_IR_CSC_MASK (0x1U << FDCANCCU_IR_CSC_SHIFT) /* 0x00000002 */ +#define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_MASK /* Calibration State Changed */ + +/* **************** Bit definition for FDCANCCU_IE register ***************/ +#define FDCANCCU_IE_CWEE_SHIFT (0U) +#define FDCANCCU_IE_CWEE_MASK (0x1U << FDCANCCU_IE_CWEE_SHIFT) /* 0x00000001 */ +#define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_MASK /* Calibration Watchdog Event Enable */ +#define FDCANCCU_IE_CSCE_SHIFT (1U) +#define FDCANCCU_IE_CSCE_MASK (0x1U << FDCANCCU_IE_CSCE_SHIFT) /* 0x00000002 */ +#define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_MASK /* Calibration State Changed Enable */ + +#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FDCAN_H */ diff --git a/arch/arm/src/stm32h7/stm32.h b/arch/arm/src/stm32h7/stm32.h index b262bef986..5d2003560d 100644 --- a/arch/arm/src/stm32h7/stm32.h +++ b/arch/arm/src/stm32h7/stm32.h @@ -36,6 +36,7 @@ #include "chip.h" #include "stm32_gpio.h" +#include "stm32_fdcan_sock.h" #include "stm32_fmc.h" #include "stm32_i2c.h" #include "stm32_spi.h" diff --git a/arch/arm/src/stm32h7/stm32_fdcan_sock.c b/arch/arm/src/stm32h7/stm32_fdcan_sock.c new file mode 100644 index 0000000000..269daaf370 --- /dev/null +++ b/arch/arm/src/stm32h7/stm32_fdcan_sock.c @@ -0,0 +1,2529 @@ +/**************************************************************************** + * arch/arm/src/stm32h7/stm32_fdcan_sock.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE +#include +#endif + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* General Configuration ****************************************************/ + +#if !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required; HPWORK is recommended +#else + +/* If processing is not done at the interrupt level, then work queue support + * is required. + * + * The high-priority work queue is suggested in order to minimize latency of + * critical Rx/Tx transactions on the CAN bus. + */ + +# if defined(CONFIG_STM32H7_FDCAN_HPWORK) +# define CANWORK HPWORK +# elif defined(CONFIG_STM32H7_FDCAN_LPWORK) +# define CANWORK LPWORK +# else +# define CANWORK LPWORK +# endif +#endif + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE +# define TX_TIMEOUT_WQ +#endif + +/* Message RAM Configuration ************************************************/ + +#define WORD_LENGTH 4U + +/* Define number of Rx / Tx elements in message RAM; note that elements are + * given sizes in number of words (4-byte chunks) + * + * Up to 64 Rx elements and 32 Tx elements may be configured per interface + * + * Note there are a total of 2560 words available shared between all FDCAN + * interfaces for Rx, Tx, and filter storage + */ + +#ifdef CONFIG_NET_CAN_CANFD +# define FIFO_ELEMENT_SIZE 18 /* size (in Words) of a FIFO element in message RAM (CANFD_MTU / 4) */ +# define NUM_RX_FIFO0 14 /* 14 elements max for RX FIFO0 */ +# define NUM_RX_FIFO1 0 /* No elements for RX FIFO1 */ +# define NUM_TX_FIFO 7 /* 7 elements max for TX FIFO */ +#else +# define FIFO_ELEMENT_SIZE 4 /* size (in Words) of a FIFO element in message RAM (CAN_MTU / 4) */ +# define NUM_RX_FIFO0 64 /* 64 elements max for RX FIFO0 */ +# define NUM_RX_FIFO1 0 /* No elements for RX FIFO1 */ +# define NUM_TX_FIFO 32 /* 32 elements max for TX FIFO */ +#endif + +/* Intermediate message buffering *******************************************/ + +#define POOL_SIZE 1 + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE +#define MSG_DATA sizeof(struct timeval) +#else +#define MSG_DATA 0 +#endif + +#ifdef CONFIG_NET_CAN_CANFD +# define FRAME_TYPE struct canfd_frame +#else +# define FRAME_TYPE struct can_frame +#endif + +/* CAN Clock Configuration **************************************************/ + +#define STM32_FDCANCLK STM32_HSE_FREQUENCY +#define CLK_FREQ STM32_FDCANCLK +#define PRESDIV_MAX 256 + +/* Interrupts ***************************************************************/ + +#define FDCAN_IR_MASK 0x3fcfffff /* Mask of all non-reserved bits in FDCAN_IR */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* CAN ID word, as defined by FDCAN device (Note xtd/rtr/esi bit positions) */ + +union can_id_u +{ + volatile uint32_t can_id; + struct + { + volatile uint32_t extid : 29; + volatile uint32_t resex : 3; + }; + struct + { + volatile uint32_t res : 18; + volatile uint32_t stdid : 11; + volatile uint32_t rtr : 1; + volatile uint32_t xtd : 1; + volatile uint32_t esi : 1; + }; +}; + +/* Union of 4 bytes as 1 register */ + +union payload_u +{ + volatile uint32_t word; + struct + { + volatile uint32_t b00 : 8; + volatile uint32_t b01 : 8; + volatile uint32_t b02 : 8; + volatile uint32_t b03 : 8; + }; +}; + +/* Message RAM Structures ***************************************************/ + +/* Rx FIFO Element Header -- RM0433 pg 2536 */ + +union rx_fifo_header_u +{ + struct + { + volatile uint32_t w0; + volatile uint32_t w1; + }; + + struct + { + /* First word */ + + union can_id_u id; + + /* Second word */ + + volatile uint32_t rxts : 16; /* Rx timestamp */ + volatile uint32_t dlc : 4; /* Data length code */ + volatile uint32_t brs : 1; /* Bitrate switching */ + volatile uint32_t fdf : 1; /* FD frame */ + volatile uint32_t res : 2; /* Reserved for Tx Event */ + volatile uint32_t fidx : 7; /* Filter index */ + volatile uint32_t anmf : 1; /* Accepted non-matching frame */ + }; +}; + +/* Tx FIFO Element Header -- RM0433 pg 2538 */ + +union tx_fifo_header_u +{ + struct + { + volatile uint32_t w0; + volatile uint32_t w1; + }; + + struct + { + /* First word */ + + union can_id_u id; + + /* Second word */ + + volatile uint32_t res1 : 16; /* Reserved for Tx Event timestamp */ + volatile uint32_t dlc : 4; /* Data length code */ + volatile uint32_t brs : 1; /* Bitrate switching */ + volatile uint32_t fdf : 1; /* FD frame */ + volatile uint32_t res2 : 1; /* Reserved for Tx Event */ + volatile uint32_t efc : 1; /* Event FIFO control */ + volatile uint32_t mm : 8; /* Message marker (user data; copied to Tx Event) */ + }; +}; + +/* Rx FIFO Element */ + +struct rx_fifo_s +{ + union rx_fifo_header_u header; +#ifdef CONFIG_NET_CAN_CANFD + union payload_u data[16]; /* 64-byte FD payload */ +#else + union payload_u data[2]; /* 8-byte Classic payload */ +#endif +}; + +/* Tx FIFO Element */ + +struct tx_fifo_s +{ + union tx_fifo_header_u header; +#ifdef CONFIG_NET_CAN_CANFD + union payload_u data[16]; /* 64-byte FD payload */ +#else + union payload_u data[2]; /* 8-byte Classic payload */ +#endif +}; + +/* Tx Mailbox Status Tracking */ + +#define TX_ABORT -1 +#define TX_FREE 0 +#define TX_BUSY 1 + +struct txmbstats +{ +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE + struct timeval deadline; + struct wdog_s txtimeout; +#endif + int8_t pending; +}; + +/* FDCAN Device hardware configuration **************************************/ + +struct fdcan_config_s +{ + uint32_t tx_pin; /* GPIO configuration for TX */ + uint32_t rx_pin; /* GPIO configuration for RX */ + uint32_t mb_irq[2]; /* FDCAN Interrupt 0, 1 (Rx, Tx) */ +}; + +struct fdcan_bitseg +{ + uint32_t bitrate; + uint8_t sjw; + uint8_t bs1; + uint8_t bs2; + uint8_t prescaler; +}; + +struct fdcan_message_ram +{ + uint32_t filt_stdid_addr; + uint32_t filt_extid_addr; + uint32_t rxfifo0_addr; + uint32_t rxfifo1_addr; + uint32_t txfifo_addr; + uint8_t n_stdfilt; + uint8_t n_extfilt; + uint8_t n_rxfifo0; + uint8_t n_rxfifo1; + uint8_t n_txfifo; +}; + +/* FDCAN device structures **************************************************/ + +#ifdef CONFIG_STM32H7_FDCAN1 +static const struct fdcan_config_s stm32_fdcan0_config = +{ + .tx_pin = GPIO_CAN1_TX, + .rx_pin = GPIO_CAN1_RX, + .mb_irq = + { + STM32_IRQ_FDCAN1_0, + STM32_IRQ_FDCAN1_1, + }, +}; +#endif + +#ifdef CONFIG_STM32H7_FDCAN2 +static const struct fdcan_config_s stm32_fdcan1_config = +{ + .tx_pin = GPIO_CAN2_TX, + .rx_pin = GPIO_CAN2_RX, + .mb_irq = + { + STM32_IRQ_FDCAN2_0, + STM32_IRQ_FDCAN2_1 , + }, +}; +#endif + +#ifdef CONFIG_STM32H7_FDCAN3 +# error "FDCAN3 support not yet added to stm32h7x3xx header files (pinmap, irq, etc.)" +static const struct fdcan_config_s stm32_fdcan2_config = +{ + .tx_pin = GPIO_CAN3_TX, + .rx_pin = GPIO_CAN3_RX, + .mb_irq = + { + STM32_IRQ_FDCAN3_0, + STM32_IRQ_FDCAN3_1 , + }, +}; +#endif + +/* The fdcan_driver_s encapsulates all state information for a single + * hardware interface + */ + +struct fdcan_driver_s +{ + const struct fdcan_config_s *config; /* Pin config */ + uint8_t iface_idx; /* FDCAN interface index (0 or 1) */ + uint32_t base; /* FDCAN base address */ + + struct fdcan_bitseg arbi_timing; /* Timing for arbitration phase */ +#ifdef CONFIG_NET_CAN_CANFD + struct fdcan_bitseg data_timing; /* Timing for data phase */ +#endif + + struct fdcan_message_ram message_ram; /* Start addresses for each reagion of Message RAM */ + struct rx_fifo_s *rx; /* Pointer to Rx FIFO0 in Message RAM */ + struct tx_fifo_s *tx; /* Pointer to Tx mailboxes in Message RAM */ + + /* Work queue configs for deferring interrupt and poll work */ + + struct work_s rxwork; + struct work_s txcwork; + struct work_s txdwork; + struct work_s pollwork; + + uint32_t irflags; /* Used to copy IR flags from IRQ context to work_queue */ + + /* Intermediate storage of Tx / Rx frames outside of Message RAM */ + + uint8_t tx_pool[(sizeof(FRAME_TYPE)+MSG_DATA)*POOL_SIZE]; + uint8_t rx_pool[(sizeof(FRAME_TYPE)+MSG_DATA)*POOL_SIZE]; + + struct net_driver_s dev; /* Interface understood by the network */ + bool bifup; /* true:ifup false:ifdown */ + + struct txmbstats txmb[NUM_TX_FIFO]; /* Track deadline and status of every Tx entry */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32H7_FDCAN1 +static struct fdcan_driver_s g_fdcan0; +#endif + +#ifdef CONFIG_STM32H7_FDCAN2 +static struct fdcan_driver_s g_fdcan1; +#endif + +#ifdef CONFIG_STM32H7_FDCAN3 +static struct fdcan_driver_s g_fdcan2; +#endif + +static bool g_apb1h_init = false; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Common TX logic */ + +static bool fdcan_txringfull(FAR struct fdcan_driver_s *priv); +static int fdcan_transmit(FAR struct fdcan_driver_s *priv); +static int fdcan_txpoll(struct net_driver_s *dev); + +/* Helper functions */ + +#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +static void fdcan_dumpregs(FAR struct fdcan_driver_s *priv); +#endif + +int32_t fdcan_bittiming(struct fdcan_bitseg *timing); + +static void fdcan_apb1hreset(void); +static void fdcan_setinit(uint32_t base, uint32_t init); +static void fdcan_setenable(uint32_t base, uint32_t enable); +static void fdcan_setconfig(uint32_t base, uint32_t config_enable); +static bool fdcan_waitccr_change(uint32_t base, + uint32_t mask, + uint32_t target_state); + +static void fdcan_enable_interrupts(struct fdcan_driver_s *priv); +static void fdcan_disable_interrupts(struct fdcan_driver_s *priv); + +/* Interrupt handling */ + +static void fdcan_receive(FAR struct fdcan_driver_s *priv); +static void fdcan_receive_work(FAR void *arg); +static void fdcan_txdone(FAR struct fdcan_driver_s *priv); +static void fdcan_txdone_work(FAR void *arg); + +static int fdcan_interrupt(int irq, FAR void *context, + FAR void *arg); + +static void fdcan_check_errors(FAR struct fdcan_driver_s *priv); + +/* Watchdog timer expirations */ + +#ifdef TX_TIMEOUT_WQ +static void fdcan_txtimeout_work(FAR void *arg); +static void fdcan_txtimeout_expiry(wdparm_t arg); +#endif + +/* NuttX networking stack callback functions */ + +static int fdcan_ifup(struct net_driver_s *dev); +static int fdcan_ifdown(struct net_driver_s *dev); + +static void fdcan_txavail_work(FAR void *arg); +static int fdcan_txavail(struct net_driver_s *dev); + +#ifdef CONFIG_NETDEV_IOCTL +static int fdcan_netdev_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg); +#endif + +/* Initialization and Reset */ + +static int fdcan_initialize(struct fdcan_driver_s *priv); +static void fdcan_reset(struct fdcan_driver_s *priv); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: fdcan_dumpregs + * + * Dump common register values to the console for debugging purposes. + ****************************************************************************/ + +#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +static void fdcan_dumpregs(FAR struct fdcan_driver_s *priv) +{ + printf("-------------- FDCAN Reg Dump ----------------\n"); + printf("CAN%d Base: 0x%lx\n", priv->iface_idx, priv->base); + + uint32_t regval; + regval = getreg32(priv->base + STM32_FDCAN_CCCR_OFFSET); + printf("CCCR = 0x%lx\n", regval); + regval = getreg32(priv->base + STM32_FDCAN_ECR_OFFSET); + printf("ECR = 0x%lx\n", regval); + + regval = getreg32(priv->base + STM32_FDCAN_NBTP_OFFSET); + printf("NBTP = 0x%lx\n", regval); + regval = getreg32(priv->base + STM32_FDCAN_DBTP_OFFSET); + printf("DBTP = 0x%lx\n", regval); + + regval = getreg32(priv->base + STM32_FDCAN_TXBC_OFFSET); + printf("TXBC = 0x%lx\n", regval); + regval = getreg32(priv->base + STM32_FDCAN_RXF0C_OFFSET); + printf("RXF0C = 0x%lx\n", regval); + + regval = getreg32(priv->base + STM32_FDCAN_TXESC_OFFSET); + printf("TXESC = 0x%lx\n", regval); + regval = getreg32(priv->base + STM32_FDCAN_RXESC_OFFSET); + printf("RXESC = 0x%lx\n", regval); + + regval = getreg32(priv->base + STM32_FDCAN_IE_OFFSET); + printf("IE = 0x%lx\n", regval); + regval = getreg32(priv->base + STM32_FDCAN_ILE_OFFSET); + printf("ILE = 0x%lx\n", regval); + regval = getreg32(priv->base + STM32_FDCAN_ILS_OFFSET); + printf("ILS = 0x%lx\n", regval); + + /* Print out some possibly interesting unhandled interrupts */ + + regval = getreg32(priv->base + STM32_FDCAN_IR_OFFSET); + printf("IR = 0x%lx\n", regval); + + if (regval & FDCAN_IR_PEA || regval & FDCAN_IR_PED) + { + /* Protocol error -- check protocol status register for details */ + + regval = getreg32(priv->base + STM32_FDCAN_PSR_OFFSET); + printf("--PSR.LEC = %d\n", regval & FDCAN_PSR_LEC); + } +} +#endif + +/**************************************************************************** + * Name: fdcan_bittiming + * + * Description: + * Convert desired bitrate to FDCAN bit segment values + * The computed values apply to both data and arbitration phases + * + * Input Parameters: + * timing - structure to store bit timing + * + * Returned Value: + * OK on success; >0 on failure. + ****************************************************************************/ + +int32_t fdcan_bittiming(struct fdcan_bitseg *timing) +{ + /* Implementation ported from PX4's uavcan_drivers/stm32[h7] + * + * Ref. "Automatic Baudrate Detection in CANopen Networks", U. Koppe + * MicroControl GmbH & Co. KG + * CAN in Automation, 2003 + * + * According to the source, optimal quanta per bit are: + * Bitrate Optimal Maximum + * 1000 kbps 8 10 + * 500 kbps 16 17 + * 250 kbps 16 17 + * 125 kbps 16 17 + */ + + const uint32_t target_bitrate = timing->bitrate; + static const int32_t max_bs1 = 16; + static const int32_t max_bs2 = 8; + const uint8_t max_quanta_per_bit = (timing->bitrate >= 1000000) ? 10 : 17; + static const int max_sp_location = 900; + + /* Computing (prescaler * BS): + * BITRATE = 1 / (PRESCALER * (1 / PCLK) * (1 + BS1 + BS2)) + * BITRATE = PCLK / (PRESCALER * (1 + BS1 + BS2)) + * let: + * BS = 1 + BS1 + BS2 + * (BS == total number of time quanta per bit) + * PRESCALER_BS = PRESCALER * BS + * ==> + * PRESCALER_BS = PCLK / BITRATE + */ + + const uint32_t prescaler_bs = CLK_FREQ / target_bitrate; + + /* Find prescaler value such that the number of quanta per bit is highest */ + + uint8_t bs1_bs2_sum = max_quanta_per_bit - 1; + + while ((prescaler_bs % (1 + bs1_bs2_sum)) != 0) + { + if (bs1_bs2_sum <= 2) + { + nerr("Target bitrate too high - no solution possible."); + return 1; /* No solution */ + } + + bs1_bs2_sum--; + } + + const uint32_t prescaler = prescaler_bs / (1 + bs1_bs2_sum); + + if ((prescaler < 1U) || (prescaler > 1024U)) + { + nerr("Target bitrate invalid - bad prescaler."); + return 2; /* No solution */ + } + + /* Now we have a constraint: (BS1 + BS2) == bs1_bs2_sum. + * We need to find the values so that the sample point is as close as + * possible to the optimal value. + * + * Solve[(1 + bs1)/(1 + bs1 + bs2) == 7/8, bs2] + * (Where 7/8 is 0.875, the recommended sample point location) + * {{bs2 -> (1 + bs1)/7}} + * + * Hence: + * bs2 = (1 + bs1) / 7 + * bs1 = (7 * bs1_bs2_sum - 1) / 8 + * + * Sample point location can be computed as follows: + * Sample point location = (1 + bs1) / (1 + bs1 + bs2) + * + * Since the optimal solution is so close to the maximum, we prepare two + * solutions, and then pick the best one: + * - With rounding to nearest + * - With rounding to zero + */ + + /* First attempt with rounding to nearest */ + + uint8_t bs1 = (uint8_t)((7 * bs1_bs2_sum - 1) + 4) / 8; + uint8_t bs2 = (uint8_t)(bs1_bs2_sum - bs1); + uint16_t sample_point_permill = + (uint16_t)(1000 * (1 + bs1) / (1 + bs1 + bs2)); + + if (sample_point_permill > max_sp_location) + { + /* Second attempt with rounding to zero */ + + bs1 = (7 * bs1_bs2_sum - 1) / 8; + bs2 = bs1_bs2_sum - bs1; + } + + bool valid = (bs1 >= 1) && (bs1 <= max_bs1) && (bs2 >= 1) && + (bs2 <= max_bs2); + + /* Final validation + * Helpful Python: + * def sample_point_from_btr(x): + * assert 0b0011110010000000111111000000000 & x == 0 + * ts2,ts1,brp = (x>>20)&7, (x>>16)&15, x&511 + * return (1+ts1+1)/(1+ts1+1+ts2+1) + */ + + if (target_bitrate != (CLK_FREQ / (prescaler * (1 + bs1 + bs2))) || !valid) + { + nerr("Target bitrate invalid - solution does not match."); + return 3; /* Solution not found */ + } + +#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + ninfo("[fdcan] CLK_FREQ %lu, target_bitrate %lu, prescaler %lu, bs1 %d" + ", bs2 %d\n", CLK_FREQ, target_bitrate, prescaler_bs, bs1 - 1, + bs2 - 1); +#endif + + timing->bs1 = (uint8_t)(bs1 - 1); + timing->bs2 = (uint8_t)(bs2 - 1); + timing->prescaler = (uint16_t)(prescaler - 1); + timing->sjw = 0; /* Which means one */ + + return 0; +} + +/**************************************************************************** + * Function: fdcan_txringfull + * + * Description: + * Check if all of the TX descriptors are in use. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * true is the TX ring is full; false if there are free slots at the + * head index. + * + ****************************************************************************/ + +static bool fdcan_txringfull(FAR struct fdcan_driver_s *priv) +{ + /* TODO: Decide if this needs to be checked every time, or just during init + * Check that we even _have_ a Tx FIFO allocated + */ + + uint32_t regval = getreg32(priv->base + STM32_FDCAN_TXBC_OFFSET); + if ((regval & FDCAN_TXBC_TFQS) == 0) + { + nerr("No Tx FIFO buffers assigned? Check your message RAM config\n"); + return true; + } + + /* Check if the Tx queue is full */ + + regval = getreg32(priv->base + STM32_FDCAN_TXFQS_OFFSET); + if ((regval & FDCAN_TXFQS_TFQF) == FDCAN_TXFQS_TFQF) + { + return true; /* Sorry, out of room, try back later */ + } + + return false; +} + +/**************************************************************************** + * Function: fdcan_transmit + * + * Description: + * Start hardware transmission of the data contained in priv->d_buf. Called + * either from the txdone interrupt handling or from watchdog based polling + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int fdcan_transmit(FAR struct fdcan_driver_s *priv) +{ + irqstate_t flags = enter_critical_section(); + + /* First, check if there are any slots available in the queue */ + + uint32_t regval = getreg32(priv->base + STM32_FDCAN_TXFQS_OFFSET); + if ((regval & FDCAN_TXFQS_TFQF) == FDCAN_TXFQS_TFQF) + { + /* Tx FIFO / Queue is full */ + + leave_critical_section(flags); + return -EBUSY; + } + + /* Next, get the next available FIFO index from the controller */ + + regval = getreg32(priv->base + STM32_FDCAN_TXFQS_OFFSET); + const uint8_t mbi = (regval & FDCAN_TXFQS_TFQPI) >> + FDCAN_TXFQS_TFQPI_SHIFT; + + /* Now, we can copy the CAN frame to the FIFO (in message RAM) */ + + if (mbi >= NUM_TX_FIFO) + { + nerr("Invalid Tx mailbox index encountered in transmit\n"); + leave_critical_section(flags); + return -EIO; + } + + struct tx_fifo_s *mb = &priv->tx[mbi]; + + /* Setup timeout deadline if enabled */ + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE + int32_t timeout = 0; + struct timespec ts; + clock_systime_timespec(&ts); + + if (priv->dev.d_sndlen > priv->dev.d_len) + { + /* Tx deadline is stored in d_buf after frame data */ + + struct timeval *tv = + (struct timeval *)(priv->dev.d_buf + priv->dev.d_len); + priv->txmb[mbi].deadline = *tv; + timeout = (tv->tv_sec - ts.tv_sec)*CLK_TCK + + ((tv->tv_usec - ts.tv_nsec / 1000)*CLK_TCK) / 1000000; + if (timeout < 0) + { + leave_critical_section(flags); + return 0; /* No transmission for you! */ + } + } + else + { + /* Default TX deadline defined in NET_CAN_RAW_DEFAULT_TX_DEADLINE */ + + if (CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE > 0) + { + timeout = ((CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE / 1000000) + *CLK_TCK); + priv->txmb[mbi].deadline.tv_sec = ts.tv_sec + + CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE / 1000000; + priv->txmb[mbi].deadline.tv_usec = (ts.tv_nsec / 1000) + + CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE % 1000000; + } + else + { + priv->txmb[mbi].deadline.tv_sec = 0; + priv->txmb[mbi].deadline.tv_usec = 0; + } + } +#endif + + /* Attempt to write frame */ + + union tx_fifo_header_u header; + + if (priv->dev.d_len == sizeof(struct can_frame)) + { + struct can_frame *frame = (struct can_frame *)priv->dev.d_buf; + + if (frame->can_id & CAN_EFF_FLAG) + { + header.id.xtd = 1; + header.id.extid = frame->can_id & CAN_EFF_MASK; + } + else + { + header.id.xtd = 0; + header.id.stdid = frame->can_id & CAN_SFF_MASK; + } + + header.id.esi = frame->can_id & CAN_ERR_FLAG ? 1 : 0; + header.id.rtr = frame->can_id & CAN_RTR_FLAG ? 1 : 0; + header.dlc = frame->can_dlc; + header.brs = 0; /* No bitrate switching */ + header.fdf = 0; /* Classic CAN frame, not CAN-FD */ + header.efc = 0; /* Don't store Tx events */ + header.mm = mbi; /* Mailbox Marker for our own use; just store FIFO index */ + + /* Store into message RAM */ + + mb->header.w0 = header.w0; + mb->header.w1 = header.w1; + mb->data[0].word = *(uint32_t *)&frame->data[0]; + mb->data[1].word = *(uint32_t *)&frame->data[4]; + } +#ifdef CONFIG_NET_CAN_CANFD + else /* CAN FD frame */ + { + struct canfd_frame *frame = (struct canfd_frame *)priv->dev.d_buf; + + if (frame->can_id & CAN_EFF_FLAG) + { + header.id.xtd = 1; + header.id.extid = frame->can_id & CAN_EFF_MASK; + } + else + { + header.id.xtd = 0; + header.id.stdid = frame->can_id & CAN_SFF_MASK; + } + + const bool brs = + (priv->arbi_timing.bitrate == priv->data_timing.bitrate) ? 0 : 1; + + header.id.esi = (frame->can_id & CAN_ERR_FLAG) ? 1 : 0; + header.id.rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; + header.dlc = len_to_can_dlc[frame->len]; + header.brs = brs; /* Bitrate switching */ + header.fdf = 1; /* CAN-FD frame */ + header.efc = 0; /* Don't store Tx events */ + header.mm = mbi; /* Mailbox Marker for our own use; just store FIFO index */ + + /* Store into message RAM */ + + mb->header.w1 = header.w1; + mb->header.w0 = header.w0; + + uint32_t *frame_data_word = (uint32_t *)&frame->data[0]; + + for (int i = 0; i < (frame->len + 4 - 1) / 4; i++) + { + mb->data[i].word = frame_data_word[i]; + } + } +#endif + + /* GO - Submit the transmission request for this element */ + + putreg32(1 << mbi, priv->base + STM32_FDCAN_TXBAR_OFFSET); + + /* Increment statistics */ + + NETDEV_TXPACKETS(&priv->dev); + + priv->txmb[mbi].pending = TX_BUSY; + +#ifdef TX_TIMEOUT_WQ + /* Setup the TX timeout watchdog (perhaps restarting the timer) */ + + if (timeout > 0) + { + wd_start(&priv->txmb[mbi].txtimeout, timeout + 1, + fdcan_txtimeout_expiry, (wdparm_t)priv); + } +#endif + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Function: fdcan_txpoll + * + * Description: + * The transmitter is available, check if the network has any outgoing + * packets ready to send. This is a callback from devif_poll(). + * devif_poll() may be called: + * + * 1. When the preceding TX packet send is complete, + * 2. When the preceding TX packet send timesout and the interface is reset + * 3. During normal TX polling + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int fdcan_txpoll(struct net_driver_s *dev) +{ + FAR struct fdcan_driver_s *priv = + (FAR struct fdcan_driver_s *)dev->d_private; + + /* If the polling resulted in data that should be sent out on the network, + * the field d_len is set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + if (!devif_loopback(&priv->dev)) + { + /* Send the packet */ + + fdcan_transmit(priv); + + /* Check if there is room in the device to hold another packet. If + * not, return a non-zero value to terminate the poll. + */ + + if (fdcan_txringfull(priv)) + { + return -EBUSY; + } + } + } + + /* If zero is returned, the polling will continue until all connections + * have been examined. + */ + + return 0; +} + +/**************************************************************************** + * Function: fdcan_receive + * + * Description: + * An interrupt was received indicating the availability of a new RX packet + * Schedule the message receipt and socket notification + * + * Input Parameters: + * priv - Reference to the driver state structure + * + ****************************************************************************/ + +static void fdcan_receive(FAR struct fdcan_driver_s *priv) +{ + /* Check the interrupt value to determine which FIFO to read */ + + uint32_t regval = getreg32(priv->base + STM32_FDCAN_IR_OFFSET); + + const uint32_t ir_fifo0 = FDCAN_IR_RF0N | FDCAN_IR_RF0F; + const uint32_t ir_fifo1 = FDCAN_IR_RF1N | FDCAN_IR_RF1F; + + if (regval & ir_fifo0) + { + regval = ir_fifo0; + } + else if (regval & ir_fifo1) + { + regval = ir_fifo1; + } + else + { + nerr("ERROR: Bad RX IR flags"); + return; + } + + /* Store the Rx FIFO IR flags for use in the deferred work function */ + + priv->irflags = regval; + + /* Write the corresponding interrupt bits to reset these interrupts */ + + putreg32(regval, priv->base + STM32_FDCAN_IR_OFFSET); + + /* Schedule the actual Rx work immediately from HPWORK context */ + + work_queue(CANWORK, &priv->rxwork, fdcan_receive_work, priv, 0); +} + +/**************************************************************************** + * Function: fdcan_receive_work + * + * Description: + * An frame was received; read the frame into the intermediate rx_pool and + * notify the upper-half driver. + * While we're here, also check for errors and timeouts. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Scheduled in worker thread (HPWORK / LPWORK) + * + ****************************************************************************/ + +static void fdcan_receive_work(FAR void *arg) +{ + irqstate_t flags = enter_critical_section(); + + FAR struct fdcan_driver_s *priv = (FAR struct fdcan_driver_s *)arg; + + /* Check which FIFO triggered this work */ + + uint32_t irflags = priv->irflags; + + const uint32_t ir_fifo0 = FDCAN_IR_RF0N | FDCAN_IR_RF0F; + const uint32_t ir_fifo1 = FDCAN_IR_RF1N | FDCAN_IR_RF1F; + uint8_t fifo_id; + + if (irflags & ir_fifo0) + { + fifo_id = 0; + } + else if (irflags & ir_fifo1) + { + fifo_id = 1; + } + else + { + nerr("ERROR: Bad RX IR flags"); + leave_critical_section(flags); + return; + } + + /* Bitwise register definitions are the same for FIFO 0/1 + * + * FDCAN_RXFnC_F0S: Rx FIFO Size + * FDCAN_RXFnS_RF0L: Rx Message Lost + * FDCAN_RXFnS_F0FL: Rx FIFO Fill Level + * FDCAN_RXFnS_F0GI: Rx FIFO Get Index + * + * So we will use only the RX FIFO0 register definitions for simplicity + */ + + uint32_t offset_rxfnc = (fifo_id == 0) ? STM32_FDCAN_RXF0C_OFFSET + : STM32_FDCAN_RXF1C_OFFSET; + uint32_t offset_rxfns = (fifo_id == 0) ? STM32_FDCAN_RXF0S_OFFSET + : STM32_FDCAN_RXF1S_OFFSET; + uint32_t offset_rxfna = (fifo_id == 0) ? STM32_FDCAN_RXF0A_OFFSET + : STM32_FDCAN_RXF1A_OFFSET; + + volatile uint32_t *const rxfnc = (uint32_t *)(priv->base + offset_rxfnc); + volatile uint32_t *const rxfns = (uint32_t *)(priv->base + offset_rxfns); + volatile uint32_t *const rxfna = (uint32_t *)(priv->base + offset_rxfna); + + /* Check number of elements in message RAM allocated to this FIFO */ + + if ((*rxfnc & FDCAN_RXF0C_F0S) == 0) + { + nerr("ERROR: No RX FIFO elements allocated"); + leave_critical_section(flags); + return; + } + + /* Check for message lost; count an error */ + + if ((*rxfns & FDCAN_RXF0S_RF0L) != 0) + { + NETDEV_RXERRORS(&priv->dev); + } + + /* Check number of elements available (fill level) */ + + const uint8_t n_elem = (*rxfns & FDCAN_RXF0S_F0FL); + + if (n_elem == 0) + { + nerr("RX interrupt but 0 frames available"); + leave_critical_section(flags); + return; + } + + struct rx_fifo_s *rf = NULL; + + while ((*rxfns & FDCAN_RXF0S_F0FL) > 0) + { + /* Copy the frame from message RAM */ + + const uint8_t index = (*rxfns & FDCAN_RXF0S_F0GI) >> + FDCAN_RXF0S_F0GI_SHIFT; + + rf = &priv->rx[index]; + + /* Read the frame contents */ + +#ifdef CONFIG_NET_CAN_CANFD + if (rf->header.fdf) /* CAN FD frame */ + { + struct canfd_frame *frame = (struct canfd_frame *)priv->rx_pool; + + if (rf->header.id.xtd) + { + frame->can_id = CAN_EFF_MASK & rf->header.id.extid; + frame->can_id |= CAN_EFF_FLAG; + } + else + { + frame->can_id = CAN_SFF_MASK & rf->header.id.stdid; + } + + if (rf->header.id.rtr) + { + frame->can_id |= CAN_RTR_FLAG; + } + + frame->len = can_dlc_to_len[rf->header.dlc]; + + uint32_t *frame_data_word = (uint32_t *)&frame->data[0]; + + for (int i = 0; i < (frame->len + 4 - 1) / 4; i++) + { + frame_data_word[i] = rf->data[i].word; + } + + /* Acknowledge receipt of this FIFO element */ + + putreg32(index, rxfna); + + /* Copy the buffer pointer to priv->dev + * Set amount of data in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct canfd_frame); + priv->dev.d_buf = (uint8_t *)frame; + } + else /* CAN 2.0 Frame */ +#endif + { + struct can_frame *frame = (struct can_frame *)priv->rx_pool; + + if (rf->header.id.xtd) + { + frame->can_id = CAN_EFF_MASK & rf->header.id.extid; + frame->can_id |= CAN_EFF_FLAG; + } + else + { + frame->can_id = CAN_SFF_MASK & rf->header.id.stdid; + } + + if (rf->header.id.rtr) + { + frame->can_id |= CAN_RTR_FLAG; + } + + frame->can_dlc = rf->header.dlc; + + *(uint32_t *)&frame->data[0] = rf->data[0].word; + *(uint32_t *)&frame->data[4] = rf->data[1].word; + + /* Acknowledge receipt of this FIFO element */ + + putreg32(index, rxfna); + + /* Copy the buffer pointer to priv->dev + * Set amount of data in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct can_frame); + priv->dev.d_buf = (uint8_t *)frame; + } + + /* Send to socket interface */ + + can_input(&priv->dev); + + /* Update iface statistics */ + + NETDEV_RXPACKETS(&priv->dev); + + /* Point the packet buffer back to the next Tx buffer that will be + * used during the next write. If the write queue is full, then + * this will point at an active buffer, which must not be written + * to. This is OK because devif_poll won't be called unless the + * queue is not full. + */ + + priv->dev.d_buf = priv->tx_pool; + } + + /* Check for errors and abort-transmission requests */ + + fdcan_check_errors(priv); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Function: fdcan_txdone + * + * Description: + * An interrupt was received indicating that the last TX packet(s) is done + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called from interrupt context + * + ****************************************************************************/ + +static void fdcan_txdone(FAR struct fdcan_driver_s *priv) +{ + /* Read and reset the interrupt flag */ + + uint32_t ir = getreg32(priv->base + STM32_FDCAN_IR_OFFSET); + if (ir & FDCAN_IR_TC) + { + putreg32(FDCAN_IR_TC, priv->base + STM32_FDCAN_IR_OFFSET); + } + else + { + nerr("Unexpected FCAN interrupt on line 1\n"); + return; + } + + /* Schedule to perform the TX timeout processing on the worker thread */ + + work_queue(CANWORK, &priv->txdwork, fdcan_txdone_work, priv, 0); +} + +/**************************************************************************** + * Function: fdcan_txdone_work + * + * Description: + * Process completed transmissions, including canceling their watchdog + * timers if applicable + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Scheduled in worker thread (HPWORK / LPWORK) + * + ****************************************************************************/ + +static void fdcan_txdone_work(FAR void *arg) +{ + irqstate_t flags = enter_critical_section(); + + FAR struct fdcan_driver_s *priv = (FAR struct fdcan_driver_s *)arg; + + /* Update counters for successful transmissions */ + + for (uint8_t i = 0; i < NUM_TX_FIFO; i++) + { + if ((getreg32(priv->base + STM32_FDCAN_TXBTO_OFFSET) & (1 << i)) > 0) + { + /* Transmission Occurred in buffer i + * (Not necessarily a 'new' transmission, however) + * Check that it's a new transmission, not a previously handled + * transmission + */ + + struct txmbstats *txi = &priv->txmb[i]; + + if (txi->pending == TX_BUSY) + { + /* This is a transmission that just now completed */ + + NETDEV_TXDONE(&priv->dev); + + txi->pending = TX_FREE; + +#ifdef TX_TIMEOUT_WQ + /* We are here because a transmission completed, so the + * corresponding watchdog can be canceled. + */ + + wd_cancel(&priv->txmb[i].txtimeout); +#endif + } + } + } + + /* Check for errors and abort-transmission requests */ + + fdcan_check_errors(priv); + + /* There should be space for a new TX in any event + * Poll the network for new data to transmit + */ + + devif_poll(&priv->dev, fdcan_txpoll); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Function: fdcan_interrupt + * + * Description: + * Common handler for all enabled FDCAN interrupts + * + * Input Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * arg - Unused + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int fdcan_interrupt(int irq, FAR void *context, + FAR void *arg) +{ + switch (irq) + { +#ifdef CONFIG_STM32H7_FDCAN1 + case STM32_IRQ_FDCAN1_0: + fdcan_receive(&g_fdcan0); + break; + + case STM32_IRQ_FDCAN1_1: + fdcan_txdone(&g_fdcan0); + break; +#endif + +#ifdef CONFIG_STM32H7_FDCAN2 + case STM32_IRQ_FDCAN2_0: + fdcan_receive(&g_fdcan1); + break; + + case STM32_IRQ_FDCAN2_1: + fdcan_txdone(&g_fdcan1); + break; +#endif + +#ifdef CONFIG_STM32H7_FDCAN3 + case STM32_IRQ_FDCAN3_0: + fdcan_receive(&g_fdcan2); + break; + + case STM32_IRQ_FDCAN3_1: + fdcan_txdone(&g_fdcan2); + break; +#endif + + default: + nerr("Unexpected IRQ [%d]\n", irq); + return -EINVAL; + } + + return OK; +} + +/**************************************************************************** + * Function: fdcan_check_errors + * + * Description: + * Check error flags and cancel any timed out transmissions + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static void fdcan_check_errors(FAR struct fdcan_driver_s *priv) +{ + /* Read CAN Error Logging counter (This also resets the error counter) */ + + uint32_t regval = getreg32(priv->base + STM32_FDCAN_ECR_OFFSET) + & FDCAN_ECR_CEL; + const uint8_t cel = (uint8_t)(regval >> FDCAN_ECR_CEL_SHIFT); + + if (cel > 0) + { + /* We've had some errors; check the status of the device */ + + regval = getreg32(priv->base + STM32_FDCAN_CCCR_OFFSET); + bool restricted_op_mode = (regval & FDCAN_CCCR_ASM) > 0; + + if (restricted_op_mode) + { + nerr("Tx handler message RAM error -- resctricted mode enabled\n"); + + /* Reset the CCCR.ASM register to exit restricted op mode */ + + putreg32(regval & ~FDCAN_CCCR_ASM, + priv->base + STM32_FDCAN_CCCR_OFFSET); + } + } + + /* Serve abort requests */ + + for (uint8_t i = 0; i < NUM_TX_FIFO; i++) + { + struct txmbstats *txi = &priv->txmb[i]; + + regval = getreg32(priv->base + STM32_FDCAN_TXBRP_OFFSET); + if (txi->pending == TX_ABORT && ((1 << i) & regval)) + { + /* Request to Cancel Tx item */ + + putreg32(1 << i, priv->base + STM32_FDCAN_TXBCR_OFFSET); + txi->pending = TX_FREE; + NETDEV_TXERRORS(&priv->dev); +#ifdef TX_TIMEOUT_WQ + wd_cancel(&priv->txmb[i].txtimeout); +#endif + } + } +} + +#ifdef TX_TIMEOUT_WQ +/**************************************************************************** + * Function: fdcan_txtimeout_work + * + * Description: + * Perform TX timeout related work from the worker thread + * + * Input Parameters: + * arg - The argument passed when work_queue() as called. + * + * Assumptions: + * + ****************************************************************************/ + +static void fdcan_txtimeout_work(FAR void *arg) +{ + FAR struct fdcan_driver_s *priv = (FAR struct fdcan_driver_s *)arg; + + struct timespec ts; + struct timeval *now = (struct timeval *)&ts; + clock_systime_timespec(&ts); + now->tv_usec = ts.tv_nsec / 1000; /* timespec to timeval conversion */ + + /* The watchdog timed out, yet we still check mailboxes in case the + * transmit function transmitted a new frame + */ + + for (int mbi = 0; mbi < NUM_TX_FIFO; mbi++) + { + if (priv->txmb[mbi].deadline.tv_sec != 0 + && (now->tv_sec > priv->txmb[mbi].deadline.tv_sec + || now->tv_usec > priv->txmb[mbi].deadline.tv_usec)) + { + NETDEV_TXTIMEOUTS(&priv->dev); + priv->txmb[mbi].pending = TX_ABORT; + } + } + + fdcan_check_errors(priv); +} + +/**************************************************************************** + * Function: fdcan_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * + * Input Parameters: + * arg - Pointer to the private FDCAN driver state structure + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void fdcan_txtimeout_expiry(wdparm_t arg) +{ + FAR struct fdcan_driver_s *priv = (FAR struct fdcan_driver_s *)arg; + + /* Schedule to perform the TX timeout processing on the worker thread */ + + work_queue(CANWORK, &priv->txcwork, fdcan_txtimeout_work, priv, 0); +} +#endif + +/**************************************************************************** + * Function: fdcan_apb1hreset + * + * Description: + * Reset the periheral bus clock used by FDCAN + * Note that this will reset all configuration of all FDCAN peripherals + * + ****************************************************************************/ + +static void fdcan_apb1hreset(void) +{ + /* Reset the FDCAN's peripheral bus clock */ + + modifyreg32(STM32_RCC_APB1HRSTR, 0, RCC_APB1HRSTR_FDCANRST); + modifyreg32(STM32_RCC_APB1HRSTR, RCC_APB1HRSTR_FDCANRST, 0); +} + +/**************************************************************************** + * Function: fdcan_setinit + * + * Description: + * Enter / Exit initialization mode + * + * Input Parameters: + * base - The base pointer of the FDCAN peripheral + * init - true: Enter init mode; false: Exit init mode + * + ****************************************************************************/ + +static void fdcan_setinit(uint32_t base, uint32_t init) +{ + if (init) + { + /* Enter hardware initialization mode */ + + modifyreg32(base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_INIT); + fdcan_waitccr_change(base, FDCAN_CCCR_INIT, FDCAN_CCCR_INIT); + } + else + { + /* Exit hardware initialization mode */ + + modifyreg32(base + STM32_FDCAN_CCCR_OFFSET, FDCAN_CCCR_INIT, 0); + fdcan_waitccr_change(base, FDCAN_CCCR_INIT, 0); + } +} + +/**************************************************************************** + * Function: fdcan_setenable + * + * Description: + * Power On / Power Off the device with the Clock Stop Request bit + * + * Input Parameters: + * base - The base pointer of the FDCAN peripheral + * init - true: Power on the device; false: Power off the device + * + ****************************************************************************/ + +static void fdcan_setenable(uint32_t base, uint32_t enable) +{ + if (enable) + { + /* Clear CSR bit */ + + modifyreg32(base + STM32_FDCAN_CCCR_OFFSET, FDCAN_CCCR_CSR, 0); + fdcan_waitccr_change(base, FDCAN_CCCR_CSA, 0); + } + else + { + /* Set CSR bit */ + + modifyreg32(base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_CSR); + fdcan_waitccr_change(base, FDCAN_CCCR_CSA, 1); + } +} + +/**************************************************************************** + * Function: fdcan_setconfig + * + * Description: + * Enter / Exit Configuration Changes Enabled mode + * + * Input Parameters: + * base - The base pointer of the FDCAN peripheral + * init - true: Enter config mode; false: Exit config mode + * + ****************************************************************************/ + +static void fdcan_setconfig(uint32_t base, uint32_t config_enable) +{ + if (config_enable) + { + /* Configuration Changes Enabled (CCE) mode */ + + modifyreg32(base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_CCE); + fdcan_waitccr_change(base, FDCAN_CCCR_CCE, 1); + } + else + { + /* Exit CCE mode */ + + modifyreg32(base + STM32_FDCAN_CCCR_OFFSET, FDCAN_CCCR_CCE, 0); + fdcan_waitccr_change(base, FDCAN_CCCR_CCE, 0); + } +} + +/**************************************************************************** + * Function: fdcan_waitccr_change + * + * Description: + * Wait for the CCR register to accept a requested change. + * Timeout after ~10ms. + * + * Input Parameters: + * base - The base pointer of the FDCAN peripheral + * mask - Mask to apply to the CCR register value + * target_state - Target masked value to wait for + * + * Returned Value: + * true on success; false on timeout + * + ****************************************************************************/ + +static bool fdcan_waitccr_change(uint32_t base, uint32_t mask, + uint32_t target_state) +{ + const unsigned timeout = 1000; + for (unsigned wait_ack = 0; wait_ack < timeout; wait_ack++) + { + const bool state = (getreg32(base + STM32_FDCAN_CCCR_OFFSET) & mask); + if (state == target_state) + { + return true; + } + + up_udelay(10); + } + + return false; +} + +/**************************************************************************** + * Function: fdcan_enable_interrupts + * + * Description: + * Enable all interrupts used by this driver + * + * Input Parameters: + * priv - Pointer to the private FDCAN driver state structure + * + * Assumptions: + * The peripheral is in Configuration Changes Enabled (CCE) mode + * + ****************************************************************************/ + +static void fdcan_enable_interrupts(struct fdcan_driver_s *priv) +{ + /* Enable both interrupt lines at the device level */ + + const uint32_t ile = FDCAN_ILE_EINT0 | FDCAN_ILE_EINT1; + modifyreg32(priv->base + STM32_FDCAN_ILE_OFFSET, 0, ile); + + /* Enable both lines at the NVIC level */ + + up_enable_irq(priv->config->mb_irq[0]); + up_enable_irq(priv->config->mb_irq[1]); +} + +/**************************************************************************** + * Function: fdcan_disable_interrupts + * + * Description: + * Disable all interrupts used by this driver + * + * Input Parameters: + * priv - Pointer to the private FDCAN driver state structure + * + * Assumptions: + * The peripheral is in Configuration Changes Enabled (CCE) mode + * + ****************************************************************************/ + +static void fdcan_disable_interrupts(struct fdcan_driver_s *priv) +{ + /* Disable both lines at the NVIC level */ + + up_disable_irq(priv->config->mb_irq[0]); + up_disable_irq(priv->config->mb_irq[1]); + + /* Disable both interrupt lines at the device level */ + + const uint32_t ile = FDCAN_ILE_EINT0 | FDCAN_ILE_EINT1; + modifyreg32(priv->base + STM32_FDCAN_ILE_OFFSET, ile, 0); +} + +/**************************************************************************** + * Function: fdcan_ifup + * + * Description: + * NuttX Callback: Bring up the CAN interface when a socket is opened + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The device is initialized and waiting to be brought online + ****************************************************************************/ + +static int fdcan_ifup(struct net_driver_s *dev) +{ + FAR struct fdcan_driver_s *priv = + (FAR struct fdcan_driver_s *)dev->d_private; + + /* Wake up the device and perform all initialization */ + + irqstate_t flags = enter_critical_section(); + + fdcan_initialize(priv); + + fdcan_setinit(priv->base, 1); + fdcan_setconfig(priv->base, 1); + + /* Enable interrupts (at both device and NVIC level) */ + + fdcan_enable_interrupts(priv); + + /* Leave init mode */ + + fdcan_setinit(priv->base, 0); + +#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + fdcan_dumpregs(priv); +#endif + + leave_critical_section(flags); + + priv->bifup = true; + + return OK; +} + +/**************************************************************************** + * Function: fdcan_ifdown + * + * Description: + * NuttX Callback: Stop the interface. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int fdcan_ifdown(struct net_driver_s *dev) +{ + FAR struct fdcan_driver_s *priv = + (FAR struct fdcan_driver_s *)dev->d_private; + + fdcan_reset(priv); + + priv->bifup = false; + + return OK; +} + +/**************************************************************************** + * Function: fdcan_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Input Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +static void fdcan_txavail_work(FAR void *arg) +{ + FAR struct fdcan_driver_s *priv = (FAR struct fdcan_driver_s *)arg; + + /* Ignore the notification if the interface is not yet up */ + + net_lock(); + if (priv->bifup) + { + /* Check if there is room in the hardware to hold another outgoing + * packet. + */ + + if (!fdcan_txringfull(priv)) + { + /* There is space for another transfer. Poll the network for + * new XMIT data. + */ + + devif_poll(&priv->dev, fdcan_txpoll); + } + } + + net_unlock(); +} + +/**************************************************************************** + * Function: fdcan_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus to perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int fdcan_txavail(struct net_driver_s *dev) +{ + FAR struct fdcan_driver_s *priv = + (FAR struct fdcan_driver_s *)dev->d_private; + + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->pollwork)) + { + /* Schedule to serialize the poll on the worker thread. */ + + fdcan_txavail_work(priv); + } + + return OK; +} + +/**************************************************************************** + * Function: fdcan_netdev_ioctl + * + * Description: + * PHY ioctl command handler + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * cmd - ioctl command + * arg - Argument accompanying the command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NETDEV_IOCTL +static int fdcan_netdev_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg) +{ + FAR struct fdcan_driver_s *priv = dev->d_private; + + int ret; + + switch (cmd) + { +#ifdef CONFIG_NETDEV_CAN_BITRATE_IOCTL + case SIOCGCANBITRATE: /* Get bitrate from a CAN controller */ + { + struct can_ioctl_data_s *req = + (struct can_ioctl_data_s *)((uintptr_t)arg); + req->arbi_bitrate = priv->arbi_timing.bitrate / 1000; /* kbit/s */ +#ifdef CONFIG_NET_CAN_CANFD + req->data_bitrate = priv->data_timing.bitrate / 1000; /* kbit/s */ +#else + req->data_bitrate = 0; +#endif + ret = OK; + } + break; + + case SIOCSCANBITRATE: /* Set bitrate of a CAN controller */ + { + struct can_ioctl_data_s *req = + (struct can_ioctl_data_s *)((uintptr_t)arg); + + priv->arbi_timing.bitrate = req->arbi_bitrate * 1000; +#ifdef CONFIG_NET_CAN_CANFD + priv->data_timing.bitrate = req->data_bitrate * 1000; +#endif + + /* Reset CAN controller and start with new timings */ + + ret = fdcan_initialize(priv); + + if (ret == OK) + { + ret = fdcan_ifup(dev); + } + } + break; +#endif /* CONFIG_NETDEV_CAN_BITRATE_IOCTL */ + +#ifdef CONFIG_NETDEV_CAN_FILTER_IOCTL + case SIOCACANEXTFILTER: + { + /* TODO: Add hardware-level filter... */ + + stm32_addextfilter(priv, (FAR struct canioc_extfilter_s *)arg); + } + break; + + case SIOCDCANEXTFILTER: + { + /* TODO: Delete hardware-level filter... */ + + stm32_delextfilter(priv, (FAR struct canioc_extfilter_s *)arg); + } + break; + + case SIOCACANSTDFILTER: + { + /* TODO: Add hardware-level filter... */ + + stm32_addstdfilter(priv, (FAR struct canioc_stdfilter_s *)arg); + } + break; + + case SIOCDCANSTDFILTER: + { + /* TODO: Delete hardware-level filter... */ + + stm32_delstdfilter(priv, (FAR struct canioc_stdfilter_s *)arg); + } + break; +#endif + + default: + ret = -ENOTSUP; + break; + } + + return ret; +} +#endif /* CONFIG_NETDEV_IOCTL */ + +/**************************************************************************** + * Function: fdcan_initialize + * + * Description: + * Initialize FDCAN device + * + * Input Parameters: + * priv - Pointer to the private FDCAN driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int fdcan_initialize(struct fdcan_driver_s *priv) +{ + uint32_t regval; + + irqstate_t flags = enter_critical_section(); + + /* Reset the peripheral clock bus (only do this once) */ + + if (!g_apb1h_init) + { + fdcan_apb1hreset(); + g_apb1h_init = true; + } + + /* Exit Power-down / Sleep mode */ + + fdcan_setenable(priv->base, 1); + + /* Enter Initialization mode */ + + fdcan_setinit(priv->base, 1); + + /* Enter Configuration Changes Enabled mode */ + + fdcan_setconfig(priv->base, 1); + + /* Disable interrupts while we configure the hardware */ + + putreg32(0, priv->base + STM32_FDCAN_IE_OFFSET); + + /* Compute CAN bit timings for this bitrate */ + + /* Nominal / arbitration phase bitrate */ + + if (fdcan_bittiming(&priv->arbi_timing) != OK) + { + fdcan_setinit(priv->base, 0); + leave_critical_section(flags); + return -EIO; + } + +#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + const fdcan_bitseg *tim = &priv->arbi_timing; + ninfo("[fdcan][arbi] Timings: presc=%u sjw=%u bs1=%u bs2=%u\r\n", + tim->prescaler, tim->sjw, tim->bs1, tim->bs2); +#endif + + /* Set bit timings and prescalers (Nominal bitrate) */ + + regval = ((priv->arbi_timing.sjw << FDCAN_NBTP_NSJW_SHIFT) | + (priv->arbi_timing.bs1 << FDCAN_NBTP_NTSEG1_SHIFT) | + (priv->arbi_timing.bs2 << FDCAN_NBTP_TSEG2_SHIFT) | + (priv->arbi_timing.prescaler << FDCAN_NBTP_NBRP_SHIFT)); + putreg32(regval, priv->base + STM32_FDCAN_NBTP_OFFSET); + +#ifdef CONFIG_NET_CAN_CANFD + /* CAN-FD Data phase bitrate */ + + if (fdcan_bittiming(&priv->data_timing) != OK) + { + fdcan_setinit(priv->base, 0); + leave_critical_section(flags); + return -EIO; + } + +#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + const fdcan_bitseg *tim = &priv->data_timing; + ninfo("[fdcan][data] Timings: presc=%u sjw=%u bs1=%u bs2=%u\r\n", + tim->prescaler, tim->sjw, tim->bs1, tim->bs2); +#endif + + /* Set bit timings and prescalers (Data bitrate) */ + + regval = ((priv->data_timing.sjw << FDCAN_DBTP_DSJW_SHIFT) | + (priv->data_timing.bs1 << FDCAN_DBTP_DTSEG1_SHIFT) | + (priv->data_timing.bs2 << FDCAN_DBTP_DTSEG2_SHIFT) | + (priv->data_timing.prescaler << FDCAN_DBTP_DBRP_SHIFT)); +#endif /* CONFIG_NET_CAN_CANFD */ + + /* Be sure to fill data-phase register even if we're not using CAN FD */ + + putreg32(regval, priv->base + STM32_FDCAN_DBTP_OFFSET); + + /* Operation Configuration */ + +#ifdef STM32H7_FDCAN_LOOPBACK + /* Enable External Loopback Mode (Rx pin disconnected) (RM0433 pg 2494) */ + + modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_TEST); + modifyreg32(priv->base + STM32_FDCAN_TEST_OFFSET, 0, FDCAN_TEST_LBCK); +#endif + +#ifdef STM32H7_FDCAN_LOOPBACK_INTERNAL + /* Enable Bus Monitoring / Restricted Op Mode (RM0433 pg 2492, 2494) */ + + modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_MON); +#endif + +#ifdef CONFIG_NET_CAN_CANFD + /* Enable CAN-FD frames, including bitrate switching if needed */ + + modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_FDOE); + if (priv->arbi_timing.bitrate != priv->data_timing.bitrate) + { + modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_BRSE); + } +#else + /* Disable CAN-FD communications ("classic" CAN only) */ + + modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, FDCAN_CCCR_FDOE, 0); +#endif + +#if 0 + /* Disable Automatic Retransmission of frames upon error + * NOTE: This will even disable automatic retry due to lost arbitration!! + */ + + modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_DAR); +#endif + + /* Configure Interrupts */ + + /* Clear all interrupt flags + * Note: A flag is cleared by writing a 1 to the corresponding bit position + */ + + putreg32(FDCAN_IR_MASK, priv->base + STM32_FDCAN_IR_OFFSET); + + /* Enable relevant interrupts */ + + regval = FDCAN_IE_TCE /* Transmit Complete */ + | FDCAN_IE_RF0NE /* Rx FIFO 0 new message */ + | FDCAN_IE_RF0FE /* Rx FIFO 0 FIFO full */ + | FDCAN_IE_RF1NE /* Rx FIFO 1 new message */ + | FDCAN_IE_RF1FE; /* Rx FIFO 1 FIFO full */ + putreg32(regval, priv->base + STM32_FDCAN_IE_OFFSET); + + /* Keep Rx interrupts on Line 0; move Tx to Line 1 + * TC (Tx Complete) interrupt on line 1 + */ + + regval = getreg32(priv->base + STM32_FDCAN_ILS_OFFSET); + regval |= FDCAN_ILS_TCL; + putreg32(FDCAN_ILS_TCL, priv->base + STM32_FDCAN_ILS_OFFSET); + + /* Enable Tx buffer transmission interrupts + * Note: Still need fdcan_enable_interrupts() to set ILE (IR line enable) + */ + + putreg32(FDCAN_TXBTIE_TIE, priv->base + STM32_FDCAN_TXBTIE_OFFSET); + + /* Configure Message RAM + * + * The available 2560 words (10 kiB) of RAM are shared between both FDCAN + * interfaces. It is up to us to ensure each interface has its own non- + * overlapping region of RAM assigned to it by properly assigning the start + * and end addresses for all regions of RAM. + * + * We will give each interface half of the available RAM. + * + * Rx buffers are only used in conjunction with acceptance filters; we + * don't have any specific need for this, so we will only use Rx FIFOs. + * + * Each FIFO can hold up to 64 elements, where each element (for a classic + * CAN 2.0B frame) is up to 4 words long (8 bytes data + header bits) + * + * Let's make use of the full 64 FIFO elements for FIFO0. We have no need + * to separate messages between FIFO0 and FIFO1, so ignore FIFO1 for + * simplicity. + * + * Note that the start addresses given to FDCAN are in terms of _words_, + * not bytes, so when we go to read/write to/from the message RAM, there + * will be a factor of 4 necessary in the address relative to the SA + * register values. + */ + + /* Location of this interface's message RAM - address in CPU memory address + * and relative address (in words) used for configuration + */ + + const uint32_t iface_ram_base = (2560 / 2) * priv->iface_idx; + const uint32_t gl_ram_base = STM32_CANRAM_BASE; + uint32_t ram_offset = iface_ram_base; + + /* Standard ID Filters: Allow space for 128 filters (128 words) */ + + const uint8_t n_stdid = 128; + priv->message_ram.filt_stdid_addr = gl_ram_base + ram_offset * WORD_LENGTH; + + regval = (n_stdid << FDCAN_SIDFC_LSS_SHIFT) & FDCAN_SIDFC_LSS_MASK; + regval |= ram_offset << FDCAN_SIDFC_FLSSA_SHIFT; + putreg32(regval, priv->base + STM32_FDCAN_SIDFC_OFFSET); + ram_offset += n_stdid; + + /* Extended ID Filters: Allow space for 128 filters (128 words) */ + + const uint8_t n_extid = 128; + priv->message_ram.filt_extid_addr = gl_ram_base + ram_offset * WORD_LENGTH; + + regval = (n_extid << FDCAN_XIDFC_LSE_SHIFT) & FDCAN_XIDFC_LSE_MASK; + regval |= ram_offset << FDCAN_XIDFC_FLESA_SHIFT; + putreg32(regval, priv->base + STM32_FDCAN_XIDFC_OFFSET); + ram_offset += n_extid; + + /* Set size of each element in the Rx/Tx buffers and FIFOs */ + +#ifdef CONFIG_NET_CAN_CANFD + /* Set full 64 byte space for every Rx/Tx FIFO element */ + + modifyreg32(priv->base + STM32_FDCAN_RXESC_OFFSET, 0, FDCAN_RXESC_RBDS); /* Rx Buffer */ + modifyreg32(priv->base + STM32_FDCAN_RXESC_OFFSET, 0, FDCAN_RXESC_F0DS); /* Rx FIFO 0 */ + modifyreg32(priv->base + STM32_FDCAN_RXESC_OFFSET, 0, FDCAN_RXESC_F1DS); /* Rx FIFO 1 */ + modifyreg32(priv->base + STM32_FDCAN_TXESC_OFFSET, 0, FDCAN_TXESC_TBDS); /* Tx Buffer */ +#else + putreg32(0, priv->base + STM32_FDCAN_RXESC_OFFSET); /* 8 byte space for every element (Rx buffer, FIFO1, FIFO0) */ + putreg32(0, priv->base + STM32_FDCAN_TXESC_OFFSET); /* 8 byte space for every element (Tx buffer) */ +#endif + + priv->message_ram.n_rxfifo0 = NUM_RX_FIFO0; + priv->message_ram.n_rxfifo1 = NUM_RX_FIFO1; + priv->message_ram.n_txfifo = NUM_TX_FIFO; + + /* Assign Rx Mailbox pointer in the driver structure */ + + priv->message_ram.rxfifo0_addr = gl_ram_base + ram_offset * WORD_LENGTH; + priv->rx = (struct rx_fifo_s *)(priv->message_ram.rxfifo0_addr); + + /* Set Rx FIFO0 size (64 elements max) */ + + regval = (ram_offset << FDCAN_RXF0C_F0SA_SHIFT) & FDCAN_RXF0C_F0SA_MASK; + regval |= (NUM_RX_FIFO0 << FDCAN_RXF0C_F0S_SHIFT) & FDCAN_RXF0C_F0S_MASK; + putreg32(regval, priv->base + STM32_FDCAN_RXF0C_OFFSET); + ram_offset += NUM_RX_FIFO0 * FIFO_ELEMENT_SIZE; + + /* Not using Rx FIFO1 */ + + /* Assign Tx Mailbox pointer in the driver structure */ + + priv->message_ram.txfifo_addr = gl_ram_base + ram_offset * WORD_LENGTH; + priv->tx = (struct tx_fifo_s *)(priv->message_ram.txfifo_addr); + + /* Set Tx FIFO size (32 elements max) */ + + regval = (NUM_TX_FIFO << FDCAN_TXBC_TFQS_SHIFT) & FDCAN_TXBC_TFQS_MASK; + regval &= ~FDCAN_TXBC_TFQM; /* Use FIFO */ + regval |= (ram_offset << FDCAN_TXBC_TBSA_SHIFT) & FDCAN_TXBC_TBSA_MASK; + putreg32(regval, priv->base + STM32_FDCAN_TXBC_OFFSET); + + /* Default filter configuration - Accept all messages into Rx FIFO0 */ + + regval = getreg32(priv->base + STM32_FDCAN_GFC_OFFSET); + regval &= ~FDCAN_GFC_ANFS; /* Accept non-matching stdid frames into FIFO0 */ + regval &= ~FDCAN_GFC_ANFE; /* Accept non-matching extid frames into FIFO0 */ + putreg32(regval, priv->base + STM32_FDCAN_GFC_OFFSET); + +#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + fdcan_dumpregs(priv); +#endif + + /* Exit Initialization mode */ + + fdcan_setinit(priv->base, 0); + +#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + fdcan_dumpregs(priv); +#endif + + leave_critical_section(flags); + + return 0; +} + +/**************************************************************************** + * Function: fdcan_reset + * + * Description: + * Put the device in the non-operational, reset state + * + * Input Parameters: + * priv - Pointer to the private FDCAN driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The device has previously been initialized, including message RAM + ****************************************************************************/ + +static void fdcan_reset(struct fdcan_driver_s *priv) +{ + /* Request Init Mode */ + + irqstate_t flags = enter_critical_section(); + + fdcan_setenable(priv->base, 1); + fdcan_setinit(priv->base, 1); + + /* Enable Configuration Change Mode */ + + fdcan_setconfig(priv->base, 1); + + /* Disable interrupts and clear all interrupt flags */ + + fdcan_disable_interrupts(priv); + + putreg32(FDCAN_IR_MASK, priv->base + STM32_FDCAN_IR_OFFSET); + + /* Clear all message RAM mailboxes if initialized */ + +#ifdef CONFIG_NET_CAN_CANFD + const uint8_t n_data_words = 16; +#else + const uint8_t n_data_words = 2; +#endif + + if (priv->rx) + { + for (uint32_t i = 0; i < NUM_RX_FIFO0; i++) + { + #ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + ninfo("[fdcan] MB RX %i %p\r\n", i, &priv->rx[i]); + #endif + priv->rx[i].header.w1 = 0x0; + priv->rx[i].header.w0 = 0x0; + for (uint8_t j = 0; j < n_data_words; j++) + { + priv->rx[i].data[j].word = 0x0; + } + } + } + + if (priv->tx) + { + for (uint32_t i = 0; i < NUM_TX_FIFO; i++) + { + #ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + ninfo("[fdcan] MB TX %i %p\r\n", i, &priv->tx[i]); + #endif + priv->tx[i].header.w1 = 0x0; + priv->tx[i].header.w0 = 0x0; + for (uint8_t j = 0; j < n_data_words; j++) + { + priv->tx[i].data[j].word = 0x0; + } + } + } + + /* Power off the device -- See RM0433 pg 2493 */ + + fdcan_setinit(priv->base, 0); + fdcan_setenable(priv->base, 0); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: stm32_fdcansockinitialize + * + * Description: + * Initialize the selected CAN peripheral and network (socket) interface + * + * Input Parameters: + * intf - In the case where there are multiple interfaces, this value + * identifies which interface is to be initialized. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int stm32_fdcansockinitialize(int intf) +{ + struct fdcan_driver_s *priv; + + switch (intf) + { +#ifdef CONFIG_STM32H7_FDCAN1 + case 0: + priv = &g_fdcan0; + memset(priv, 0, sizeof(struct fdcan_driver_s)); + priv->base = STM32_FDCAN1_BASE; + priv->iface_idx = 0; + priv->config = &stm32_fdcan0_config; + + /* Default bitrate configuration */ + +# ifdef CONFIG_NET_CAN_CANFD + priv->arbi_timing.bitrate = CONFIG_FDCAN1_ARBI_BITRATE; + priv->data_timing.bitrate = CONFIG_FDCAN1_DATA_BITRATE; +# else + priv->arbi_timing.bitrate = CONFIG_FDCAN1_BITRATE; +# endif + break; +#endif + +#ifdef CONFIG_STM32H7_FDCAN2 + case 1: + priv = &g_fdcan1; + memset(priv, 0, sizeof(struct fdcan_driver_s)); + priv->base = STM32_FDCAN2_BASE; + priv->iface_idx = 1; + priv->config = &stm32_fdcan1_config; + + /* Default bitrate configuration */ + +# ifdef CONFIG_NET_CAN_CANFD + priv->arbi_timing.bitrate = CONFIG_FDCAN2_ARBI_BITRATE; + priv->data_timing.bitrate = CONFIG_FDCAN2_DATA_BITRATE; +# else + priv->arbi_timing.bitrate = CONFIG_FDCAN2_BITRATE; +# endif + break; +#endif + +#ifdef CONFIG_STM32H7_FDCAN3 + case 2: + priv = &g_fdcan2 + memset(priv, 0, sizeof(struct fdcan_driver_s)); + priv->base = STM32_FDCAN3_BASE; + priv->iface_idx = 2; + priv->config = &stm32_fdcan2_config; + + /* Default bitrate configuration */ + +# ifdef CONFIG_NET_CAN_CANFD + priv->arbi_timing.bitrate = CONFIG_FDCAN3_ARBI_BITRATE; + priv->data_timing.bitrate = CONFIG_FDCAN3_DATA_BITRATE; +# else + priv->arbi_timing.bitrate = CONFIG_FDCAN3_BITRATE; +# endif + break; +#endif + + default: + return -ENODEV; + } + + if (fdcan_bittiming(&priv->arbi_timing) != OK) + { + printf("ERROR: Invalid CAN timings\n"); + return -1; + } + +#ifdef CONFIG_NET_CAN_CANFD + if (fdcan_bittiming(&priv->data_timing) != OK) + { + printf("ERROR: Invalid CAN data phase timings\n"); + return -1; + } +#endif + + /* Configure the pins we're using to interface to the controller */ + + stm32_configgpio(priv->config->tx_pin); + stm32_configgpio(priv->config->rx_pin); + + /* Attach the fdcan interrupt handlers */ + + if (irq_attach(priv->config->mb_irq[0], fdcan_interrupt, NULL)) + { + /* We could not attach the ISR to the interrupt */ + + printf("ERROR: Failed to attach CAN RX IRQ\n"); + return -EAGAIN; + } + + if (irq_attach(priv->config->mb_irq[1], fdcan_interrupt, NULL)) + { + /* We could not attach the ISR to the interrupt */ + + printf("ERROR: Failed to attach CAN TX IRQ\n"); + return -EAGAIN; + } + + /* Initialize the driver structure */ + + priv->dev.d_ifup = fdcan_ifup; /* I/F up callback */ + priv->dev.d_ifdown = fdcan_ifdown; /* I/F down callback */ + priv->dev.d_txavail = fdcan_txavail; /* New TX data callback */ +#ifdef CONFIG_NETDEV_IOCTL + priv->dev.d_ioctl = fdcan_netdev_ioctl; /* Support CAN ioctl() calls */ +#endif + priv->dev.d_private = (void *)priv; /* Used to recover private state from dev */ + + priv->dev.d_buf = priv->tx_pool; + + priv->rx = NULL; + priv->tx = NULL; + + /* Put the interface in the down state (disable interrupts, power off) */ + + fdcan_ifdown(&priv->dev); + + /* Register the device with the OS so that socket IOCTLs can be performed */ + + netdev_register(&priv->dev, NET_LL_CAN); + +#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + fdcan_dumpregs(priv); +#endif + + return OK; +} + +/**************************************************************************** + * Name: arm_netinitialize + * + * Description: + * Initialize the CAN device interfaces. If there is more than one device + * interface in the chip, then board-specific logic will have to provide + * this function to determine which, if any, CAN interfaces should be + * initialized. + * + ****************************************************************************/ + +#if !defined(CONFIG_NETDEV_LATEINIT) +void arm_netinitialize(void) +{ +#ifdef CONFIG_STM32H7_FDCAN1 + stm32_fdcansockinitialize(0); +#endif + +#ifdef CONFIG_STM32H7_FDCAN2 + stm32_fdcansockinitialize(1); +#endif + +#ifdef CONFIG_STM32H7_FDCAN3 + stm32_fdcansockinitialize(2); +#endif +} +#endif diff --git a/arch/arm/src/stm32h7/stm32_fdcan_sock.h b/arch/arm/src/stm32h7/stm32_fdcan_sock.h new file mode 100644 index 0000000000..8325cb3418 --- /dev/null +++ b/arch/arm/src/stm32h7/stm32_fdcan_sock.h @@ -0,0 +1,107 @@ +/**************************************************************************** + * arch/arm/src/stm32h7/stm32_fdcan_sock.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H7_STM32_FDCAN_SOCK_H +#define __ARCH_ARM_SRC_STM32H7_STM32_FDCAN_SOCK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "hardware/stm32_fdcan.h" + +#ifdef CONFIG_STM32H7_FDCAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#ifndef CONFIG_NETDEV_LATEINIT + +/**************************************************************************** + * Function: arm_netinitialize + * + * Description: + * Initialize the first network interface. If there is more than one + * interface in the chip, then board-specific logic will have to provide + * this function to determine which, if any, CAN interfaces should be + * initialized. Also prototyped in up_internal.h. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * Called very early in the initialization sequence. + * + ****************************************************************************/ + +void arm_netinitialize(void); + +#else + +/**************************************************************************** + * Function: stm32_fdcansockinitialize + * + * Description: + * Initialize the CAN controller and driver + * + * Input Parameters: + * intf - In the case where there are multiple CAN interfaces, this value + * identifies which CAN interface is to be initialized. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int stm32_fdcansockinitialize(int intf); + +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_STM32H7_FDCAN */ +#endif /* __ARCH_ARM_SRC_STM32H7_STM32_FDCAN_SOCK_H */ diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index 9218861409..c6a5f457b8 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -432,13 +432,15 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1LENR_I2C3EN; #endif - /* TODO: ... */ - putreg32(regval, STM32_RCC_APB1LENR); /* Enable APB1L peripherals */ regval = getreg32(STM32_RCC_APB1HENR); - /* TODO: ... */ +#ifdef CONFIG_STM32H7_FDCAN + /* FDCAN clock enable */ + + regval |= RCC_APB1HENR_FDCANEN; +#endif putreg32(regval, STM32_RCC_APB1HENR); /* Enable APB1H peripherals */ }