diff --git a/arch/arm/include/kl/chip.h b/arch/arm/include/kl/chip.h
index ec29e1805c..df1029eecb 100644
--- a/arch/arm/include/kl/chip.h
+++ b/arch/arm/include/kl/chip.h
@@ -171,7 +171,7 @@
 /* NVIC priority levels *************************************************************/
 /* Each priority field holds a priority value, 0-15. The lower the value, the greater
  * the priority of the corresponding interrupt. The processor implements only
- * bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
+ * bits[7:6] of each field, bits[5:0] read as zero and ignore writes.
  */
 
 #define NVIC_SYSH_PRIORITY_MIN     0xc0 /* All bits[7:6] set is minimum priority */
diff --git a/arch/arm/include/lpc11xx/chip.h b/arch/arm/include/lpc11xx/chip.h
index 92d2a1d9b1..4434463236 100644
--- a/arch/arm/include/lpc11xx/chip.h
+++ b/arch/arm/include/lpc11xx/chip.h
@@ -69,13 +69,13 @@
 /* NVIC priority levels *************************************************************/
 /* Each priority field holds a priority value, 0-31. The lower the value, the greater
  * the priority of the corresponding interrupt. The processor implements only
- * bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
+ * bits[7:6] of each field, bits[5:0] read as zero and ignore writes.
  */
 
-#define NVIC_SYSH_PRIORITY_MIN     0xf8 /* All bits[7:3] set is minimum priority */
+#define NVIC_SYSH_PRIORITY_MIN     0xc0 /* All bits[7:6] set is minimum priority */
 #define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
 #define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
-#define NVIC_SYSH_PRIORITY_STEP    0x08 /* Five bits of interrupt priority used */
+#define NVIC_SYSH_PRIORITY_STEP    0x40 /* Two bits of interrupt priority used */
 
 /* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
  * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
diff --git a/arch/arm/include/samv7/chip.h b/arch/arm/include/samv7/chip.h
index 3d45bc7d3b..ae5e5e59d9 100644
--- a/arch/arm/include/samv7/chip.h
+++ b/arch/arm/include/samv7/chip.h
@@ -389,7 +389,7 @@
 /* NVIC priority levels *************************************************************/
 /* Each priority field holds a priority value, 0-15. The lower the value, the greater
  * the priority of the corresponding interrupt. The processor implements only
- * bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
+ * bits[7:6] of each field, bits[5:0] read as zero and ignore writes.
  */
 
 #define NVIC_SYSH_PRIORITY_MIN        0xc0 /* All bits[7:6] set is minimum priority */
diff --git a/arch/arm/include/tiva/chip.h b/arch/arm/include/tiva/chip.h
index 7f19a50c06..5319ec282d 100644
--- a/arch/arm/include/tiva/chip.h
+++ b/arch/arm/include/tiva/chip.h
@@ -322,7 +322,7 @@
  * value
  */
 
-#define NVIC_SYSH_PRIORITY_MIN     0xe0 /* Bits [5:7] set in minimum priority */
+#define NVIC_SYSH_PRIORITY_MIN     0xe0 /* Bits [7:5] set in minimum priority */
 #define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
 #define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
 #define NVIC_SYSH_PRIORITY_STEP    0x20 /* Three bits of interrupt priority used */